mach-ap152.c 3.7 KB

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  1. /*
  2. * Qualcomm Atheros AP152 reference board support
  3. *
  4. * Copyright (c) 2015 Qualcomm Atheros
  5. * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
  6. *
  7. * Permission to use, copy, modify, and/or distribute this software for any
  8. * purpose with or without fee is hereby granted, provided that the above
  9. * copyright notice and this permission notice appear in all copies.
  10. *
  11. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18. *
  19. */
  20. #include <linux/platform_device.h>
  21. #include <linux/ath9k_platform.h>
  22. #include <linux/ar8216_platform.h>
  23. #include <asm/mach-ath79/ar71xx_regs.h>
  24. #include "common.h"
  25. #include "dev-m25p80.h"
  26. #include "machtypes.h"
  27. #include "pci.h"
  28. #include "dev-eth.h"
  29. #include "dev-gpio-buttons.h"
  30. #include "dev-leds-gpio.h"
  31. #include "dev-spi.h"
  32. #include "dev-usb.h"
  33. #include "dev-wmac.h"
  34. #define AP152_GPIO_LED_USB0 7
  35. #define AP152_GPIO_LED_USB1 8
  36. #define AP152_GPIO_BTN_RESET 2
  37. #define AP152_GPIO_BTN_WPS 1
  38. #define AP152_KEYS_POLL_INTERVAL 20 /* msecs */
  39. #define AP152_KEYS_DEBOUNCE_INTERVAL (3 * AP152_KEYS_POLL_INTERVAL)
  40. #define AP152_MAC0_OFFSET 0
  41. #define AP152_WMAC_CALDATA_OFFSET 0x1000
  42. static struct gpio_led ap152_leds_gpio[] __initdata = {
  43. {
  44. .name = "ap152:green:usb0",
  45. .gpio = AP152_GPIO_LED_USB0,
  46. .active_low = 1,
  47. },
  48. {
  49. .name = "ap152:green:usb1",
  50. .gpio = AP152_GPIO_LED_USB1,
  51. .active_low = 1,
  52. },
  53. };
  54. static struct gpio_keys_button ap152_gpio_keys[] __initdata = {
  55. {
  56. .desc = "WPS button",
  57. .type = EV_KEY,
  58. .code = KEY_WPS_BUTTON,
  59. .debounce_interval = AP152_KEYS_DEBOUNCE_INTERVAL,
  60. .gpio = AP152_GPIO_BTN_WPS,
  61. .active_low = 1,
  62. },
  63. {
  64. .desc = "Reset button",
  65. .type = EV_KEY,
  66. .code = KEY_RESTART,
  67. .debounce_interval = AP152_KEYS_DEBOUNCE_INTERVAL,
  68. .gpio = AP152_GPIO_BTN_RESET,
  69. .active_low = 1,
  70. },
  71. };
  72. static struct ar8327_pad_cfg ap152_ar8337_pad0_cfg = {
  73. .mode = AR8327_PAD_MAC_SGMII,
  74. .sgmii_delay_en = true,
  75. };
  76. static struct ar8327_platform_data ap152_ar8337_data = {
  77. .pad0_cfg = &ap152_ar8337_pad0_cfg,
  78. .port0_cfg = {
  79. .force_link = 1,
  80. .speed = AR8327_PORT_SPEED_1000,
  81. .duplex = 1,
  82. .txpause = 1,
  83. .rxpause = 1,
  84. },
  85. };
  86. static struct mdio_board_info ap152_mdio0_info[] = {
  87. {
  88. .bus_id = "ag71xx-mdio.0",
  89. .phy_addr = 0,
  90. .platform_data = &ap152_ar8337_data,
  91. },
  92. };
  93. static void __init ap152_setup(void)
  94. {
  95. u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  96. ath79_register_m25p80(NULL);
  97. ath79_register_leds_gpio(-1, ARRAY_SIZE(ap152_leds_gpio),
  98. ap152_leds_gpio);
  99. ath79_register_gpio_keys_polled(-1, AP152_KEYS_POLL_INTERVAL,
  100. ARRAY_SIZE(ap152_gpio_keys),
  101. ap152_gpio_keys);
  102. ath79_register_usb();
  103. platform_device_register(&ath79_mdio0_device);
  104. mdiobus_register_board_info(ap152_mdio0_info,
  105. ARRAY_SIZE(ap152_mdio0_info));
  106. ath79_register_wmac(art + AP152_WMAC_CALDATA_OFFSET, NULL);
  107. ath79_register_pci();
  108. ath79_init_mac(ath79_eth0_data.mac_addr, art + AP152_MAC0_OFFSET, 0);
  109. /* GMAC0 is connected to an AR8337 switch */
  110. ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  111. ath79_eth0_data.speed = SPEED_1000;
  112. ath79_eth0_data.duplex = DUPLEX_FULL;
  113. ath79_eth0_data.phy_mask = BIT(0);
  114. ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  115. ath79_register_eth(0);
  116. }
  117. MIPS_MACHINE(ATH79_MACH_AP152, "AP152", "Qualcomm Atheros AP152 reference board",
  118. ap152_setup);