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mach-ap96.c 3.7 KB

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  1. /*
  2. * Atheros AP96 board support
  3. *
  4. * Copyright (C) 2009 Marco Porsch
  5. * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  6. * Copyright (C) 2010 Atheros Communications
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License version 2 as published
  10. * by the Free Software Foundation.
  11. */
  12. #include <linux/platform_device.h>
  13. #include <linux/delay.h>
  14. #include <asm/mach-ath79/ath79.h>
  15. #include "dev-ap9x-pci.h"
  16. #include "dev-eth.h"
  17. #include "dev-gpio-buttons.h"
  18. #include "dev-leds-gpio.h"
  19. #include "dev-m25p80.h"
  20. #include "dev-usb.h"
  21. #include "machtypes.h"
  22. #define AP96_GPIO_LED_12_GREEN 0
  23. #define AP96_GPIO_LED_3_GREEN 1
  24. #define AP96_GPIO_LED_2_GREEN 2
  25. #define AP96_GPIO_LED_WPS_GREEN 4
  26. #define AP96_GPIO_LED_5_GREEN 5
  27. #define AP96_GPIO_LED_4_ORANGE 6
  28. /* Reset button - next to the power connector */
  29. #define AP96_GPIO_BTN_RESET 3
  30. /* WPS button - next to a led on right */
  31. #define AP96_GPIO_BTN_WPS 8
  32. #define AP96_KEYS_POLL_INTERVAL 20 /* msecs */
  33. #define AP96_KEYS_DEBOUNCE_INTERVAL (3 * AP96_KEYS_POLL_INTERVAL)
  34. #define AP96_WMAC0_MAC_OFFSET 0x120c
  35. #define AP96_WMAC1_MAC_OFFSET 0x520c
  36. #define AP96_CALDATA0_OFFSET 0x1000
  37. #define AP96_CALDATA1_OFFSET 0x5000
  38. /*
  39. * AP96 has 12 unlabeled leds in the front; these are numbered from 1 to 12
  40. * below (from left to right on the board). Led 1 seems to be on whenever the
  41. * board is powered. Led 11 shows LAN link activity actity. Led 3 is orange;
  42. * others are green.
  43. *
  44. * In addition, there is one led next to a button on the right side for WPS.
  45. */
  46. static struct gpio_led ap96_leds_gpio[] __initdata = {
  47. {
  48. .name = "ap96:green:led2",
  49. .gpio = AP96_GPIO_LED_2_GREEN,
  50. .active_low = 1,
  51. }, {
  52. .name = "ap96:green:led3",
  53. .gpio = AP96_GPIO_LED_3_GREEN,
  54. .active_low = 1,
  55. }, {
  56. .name = "ap96:orange:led4",
  57. .gpio = AP96_GPIO_LED_4_ORANGE,
  58. .active_low = 1,
  59. }, {
  60. .name = "ap96:green:led5",
  61. .gpio = AP96_GPIO_LED_5_GREEN,
  62. .active_low = 1,
  63. }, {
  64. .name = "ap96:green:led12",
  65. .gpio = AP96_GPIO_LED_12_GREEN,
  66. .active_low = 1,
  67. }, { /* next to a button on right */
  68. .name = "ap96:green:wps",
  69. .gpio = AP96_GPIO_LED_WPS_GREEN,
  70. .active_low = 1,
  71. }
  72. };
  73. static struct gpio_keys_button ap96_gpio_keys[] __initdata = {
  74. {
  75. .desc = "reset",
  76. .type = EV_KEY,
  77. .code = KEY_RESTART,
  78. .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL,
  79. .gpio = AP96_GPIO_BTN_RESET,
  80. .active_low = 1,
  81. }, {
  82. .desc = "wps",
  83. .type = EV_KEY,
  84. .code = KEY_WPS_BUTTON,
  85. .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL,
  86. .gpio = AP96_GPIO_BTN_WPS,
  87. .active_low = 1,
  88. }
  89. };
  90. #define AP96_WAN_PHYMASK 0x10
  91. #define AP96_LAN_PHYMASK 0x0f
  92. static void __init ap96_setup(void)
  93. {
  94. u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  95. ath79_register_mdio(0, ~(AP96_WAN_PHYMASK | AP96_LAN_PHYMASK));
  96. ath79_init_mac(ath79_eth0_data.mac_addr, art, 0);
  97. ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  98. ath79_eth0_data.phy_mask = AP96_LAN_PHYMASK;
  99. ath79_eth0_data.speed = SPEED_1000;
  100. ath79_eth0_data.duplex = DUPLEX_FULL;
  101. ath79_register_eth(0);
  102. ath79_init_mac(ath79_eth1_data.mac_addr, art, 1);
  103. ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  104. ath79_eth1_data.phy_mask = AP96_WAN_PHYMASK;
  105. ath79_eth1_pll_data.pll_1000 = 0x1f000000;
  106. ath79_register_eth(1);
  107. ath79_register_usb();
  108. ath79_register_m25p80(NULL);
  109. ath79_register_leds_gpio(-1, ARRAY_SIZE(ap96_leds_gpio),
  110. ap96_leds_gpio);
  111. ath79_register_gpio_keys_polled(-1, AP96_KEYS_POLL_INTERVAL,
  112. ARRAY_SIZE(ap96_gpio_keys),
  113. ap96_gpio_keys);
  114. ap94_pci_init(art + AP96_CALDATA0_OFFSET,
  115. art + AP96_WMAC0_MAC_OFFSET,
  116. art + AP96_CALDATA1_OFFSET,
  117. art + AP96_WMAC1_MAC_OFFSET);
  118. }
  119. MIPS_MACHINE(ATH79_MACH_AP96, "AP96", "Atheros AP96", ap96_setup);