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mach-dgl-5500-a1.c 3.8 KB

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  1. /*
  2. * D-Link DGL-5500 board support
  3. *
  4. * Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>
  5. * Copyright (C) 2014 Imre Kaloz <kaloz@openwrt.org>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published
  9. * by the Free Software Foundation.
  10. */
  11. #include <linux/gpio.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/ar8216_platform.h>
  14. #include <asm/mach-ath79/ar71xx_regs.h>
  15. #include "common.h"
  16. #include "pci.h"
  17. #include "dev-gpio-buttons.h"
  18. #include "dev-eth.h"
  19. #include "dev-leds-gpio.h"
  20. #include "dev-m25p80.h"
  21. #include "dev-usb.h"
  22. #include "dev-wmac.h"
  23. #include "machtypes.h"
  24. #define DGL_5500_A1_GPIO_LED_POWER_ORANGE 14
  25. #define DGL_5500_A1_GPIO_LED_POWER_GREEN 19
  26. #define DGL_5500_A1_GPIO_LED_PLANET_GREEN 22
  27. #define DGL_5500_A1_GPIO_LED_PLANET_ORANGE 23
  28. #define DGL_5500_A1_GPIO_BTN_WPS 16
  29. #define DGL_5500_A1_GPIO_BTN_RESET 17
  30. #define DGL_5500_A1_KEYS_POLL_INTERVAL 20 /* msecs */
  31. #define DGL_5500_A1_KEYS_DEBOUNCE_INTERVAL \
  32. (3 * DGL_5500_A1_KEYS_POLL_INTERVAL)
  33. #define DGL_5500_A1_WMAC_CALDATA_OFFSET 0x1000
  34. #define DGL_5500_A1_LAN_MAC_OFFSET 0x04
  35. #define DGL_5500_A1_WAN_MAC_OFFSET 0x16
  36. static struct gpio_led dgl_5500_a1_leds_gpio[] __initdata = {
  37. {
  38. .name = "d-link:green:power",
  39. .gpio = DGL_5500_A1_GPIO_LED_POWER_GREEN,
  40. .active_low = 1,
  41. },
  42. {
  43. .name = "d-link:orange:power",
  44. .gpio = DGL_5500_A1_GPIO_LED_POWER_ORANGE,
  45. .active_low = 1,
  46. },
  47. {
  48. .name = "d-link:green:planet",
  49. .gpio = DGL_5500_A1_GPIO_LED_PLANET_GREEN,
  50. .active_low = 1,
  51. },
  52. {
  53. .name = "d-link:orange:planet",
  54. .gpio = DGL_5500_A1_GPIO_LED_PLANET_ORANGE,
  55. .active_low = 1,
  56. },
  57. };
  58. static struct gpio_keys_button dgl_5500_a1_gpio_keys[] __initdata = {
  59. {
  60. .desc = "Reset button",
  61. .type = EV_KEY,
  62. .code = KEY_RESTART,
  63. .debounce_interval = DGL_5500_A1_KEYS_DEBOUNCE_INTERVAL,
  64. .gpio = DGL_5500_A1_GPIO_BTN_RESET,
  65. .active_low = 1,
  66. },
  67. {
  68. .desc = "WPS button",
  69. .type = EV_KEY,
  70. .code = KEY_WPS_BUTTON,
  71. .debounce_interval = DGL_5500_A1_KEYS_DEBOUNCE_INTERVAL,
  72. .gpio = DGL_5500_A1_GPIO_BTN_WPS,
  73. .active_low = 1,
  74. },
  75. };
  76. static struct ar8327_pad_cfg dgl_5500_a1_ar8327_pad0_cfg = {
  77. /* Use the SGMII interface for the GMAC0 of the AR8327 switch */
  78. .mode = AR8327_PAD_MAC_SGMII,
  79. .sgmii_delay_en = true,
  80. };
  81. static struct ar8327_platform_data dgl_5500_a1_ar8327_data = {
  82. .pad0_cfg = &dgl_5500_a1_ar8327_pad0_cfg,
  83. .port0_cfg = {
  84. .force_link = 1,
  85. .speed = AR8327_PORT_SPEED_1000,
  86. .duplex = 1,
  87. .txpause = 1,
  88. .rxpause = 1,
  89. },
  90. };
  91. static struct mdio_board_info dgl_5500_a1_mdio0_info[] = {
  92. {
  93. .bus_id = "ag71xx-mdio.0",
  94. .phy_addr = 0,
  95. .platform_data = &dgl_5500_a1_ar8327_data,
  96. },
  97. };
  98. static void __init dgl_5500_a1_setup(void)
  99. {
  100. u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000);
  101. u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  102. u8 lan_mac[ETH_ALEN];
  103. ath79_parse_ascii_mac(mac + DGL_5500_A1_LAN_MAC_OFFSET, lan_mac);
  104. ath79_register_m25p80(NULL);
  105. ath79_register_leds_gpio(-1, ARRAY_SIZE(dgl_5500_a1_leds_gpio),
  106. dgl_5500_a1_leds_gpio);
  107. ath79_register_gpio_keys_polled(-1, DGL_5500_A1_KEYS_POLL_INTERVAL,
  108. ARRAY_SIZE(dgl_5500_a1_gpio_keys),
  109. dgl_5500_a1_gpio_keys);
  110. ath79_register_wmac(art + DGL_5500_A1_WMAC_CALDATA_OFFSET, lan_mac);
  111. ath79_register_mdio(0, 0x0);
  112. mdiobus_register_board_info(dgl_5500_a1_mdio0_info,
  113. ARRAY_SIZE(dgl_5500_a1_mdio0_info));
  114. ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0);
  115. /* GMAC1 is connected to an AR8327N switch via the SMGII interface */
  116. ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  117. ath79_eth1_data.phy_mask = BIT(0);
  118. ath79_eth1_data.mii_bus_dev = &ath79_mdio0_device.dev;
  119. ath79_eth1_pll_data.pll_1000 = 0x03000101;
  120. ath79_register_eth(1);
  121. ath79_register_usb();
  122. ath79_register_pci();
  123. }
  124. MIPS_MACHINE(ATH79_MACH_DGL_5500_A1, "DGL-5500-A1", "D-Link DGL-5500 rev. A1",
  125. dgl_5500_a1_setup);