mach-mynet-n750.c 6.0 KB

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  1. /*
  2. * WD My Net N750 board support
  3. *
  4. * Copyright (C) 2013 Felix Kaechele <felix@fetzig.org>
  5. * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published
  9. * by the Free Software Foundation.
  10. */
  11. #include <linux/pci.h>
  12. #include <linux/phy.h>
  13. #include <linux/gpio.h>
  14. #include <linux/delay.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/ath9k_platform.h>
  17. #include <linux/ar8216_platform.h>
  18. #include <asm/mach-ath79/ar71xx_regs.h>
  19. #include "common.h"
  20. #include "dev-ap9x-pci.h"
  21. #include "dev-eth.h"
  22. #include "dev-gpio-buttons.h"
  23. #include "dev-leds-gpio.h"
  24. #include "dev-m25p80.h"
  25. #include "dev-spi.h"
  26. #include "dev-usb.h"
  27. #include "dev-wmac.h"
  28. #include "machtypes.h"
  29. #include "nvram.h"
  30. /*
  31. * Taken from GPL bootloader source:
  32. * board/ar7240/db12x/alpha_gpio.c
  33. */
  34. #define MYNET_N750_GPIO_LED_WIFI 11
  35. #define MYNET_N750_GPIO_LED_INTERNET 12
  36. #define MYNET_N750_GPIO_LED_WPS 13
  37. #define MYNET_N750_GPIO_LED_POWER 14
  38. #define MYNET_N750_GPIO_BTN_RESET 17
  39. #define MYNET_N750_GPIO_BTN_WPS 19
  40. #define MYNET_N750_GPIO_EXTERNAL_LNA0 15
  41. #define MYNET_N750_GPIO_EXTERNAL_LNA1 18
  42. #define MYNET_N750_KEYS_POLL_INTERVAL 20 /* msecs */
  43. #define MYNET_N750_KEYS_DEBOUNCE_INTERVAL (3 * MYNET_N750_KEYS_POLL_INTERVAL)
  44. #define MYNET_N750_WMAC_CALDATA_OFFSET 0x1000
  45. #define MYNET_N750_PCIE_CALDATA_OFFSET 0x5000
  46. #define MYNET_N750_NVRAM_ADDR 0x1f058010
  47. #define MYNET_N750_NVRAM_SIZE 0x7ff0
  48. static struct gpio_led mynet_n750_leds_gpio[] __initdata = {
  49. {
  50. .name = "wd:blue:power",
  51. .gpio = MYNET_N750_GPIO_LED_POWER,
  52. .active_low = 0,
  53. },
  54. {
  55. .name = "wd:blue:wps",
  56. .gpio = MYNET_N750_GPIO_LED_WPS,
  57. .active_low = 0,
  58. },
  59. {
  60. .name = "wd:blue:wireless",
  61. .gpio = MYNET_N750_GPIO_LED_WIFI,
  62. .active_low = 0,
  63. },
  64. {
  65. .name = "wd:blue:internet",
  66. .gpio = MYNET_N750_GPIO_LED_INTERNET,
  67. .active_low = 0,
  68. },
  69. };
  70. static struct gpio_keys_button mynet_n750_gpio_keys[] __initdata = {
  71. {
  72. .desc = "Reset button",
  73. .type = EV_KEY,
  74. .code = KEY_RESTART,
  75. .debounce_interval = MYNET_N750_KEYS_DEBOUNCE_INTERVAL,
  76. .gpio = MYNET_N750_GPIO_BTN_RESET,
  77. .active_low = 1,
  78. },
  79. {
  80. .desc = "WPS button",
  81. .type = EV_KEY,
  82. .code = KEY_WPS_BUTTON,
  83. .debounce_interval = MYNET_N750_KEYS_DEBOUNCE_INTERVAL,
  84. .gpio = MYNET_N750_GPIO_BTN_WPS,
  85. .active_low = 1,
  86. },
  87. };
  88. static const struct ar8327_led_info mynet_n750_leds_ar8327[] __initconst = {
  89. AR8327_LED_INFO(PHY0_0, HW, "wd:green:lan1"),
  90. AR8327_LED_INFO(PHY1_0, HW, "wd:green:lan2"),
  91. AR8327_LED_INFO(PHY2_0, HW, "wd:green:lan3"),
  92. AR8327_LED_INFO(PHY3_0, HW, "wd:green:lan4"),
  93. AR8327_LED_INFO(PHY4_0, HW, "wd:green:wan"),
  94. AR8327_LED_INFO(PHY0_1, HW, "wd:yellow:lan1"),
  95. AR8327_LED_INFO(PHY1_1, HW, "wd:yellow:lan2"),
  96. AR8327_LED_INFO(PHY2_1, HW, "wd:yellow:lan3"),
  97. AR8327_LED_INFO(PHY3_1, HW, "wd:yellow:lan4"),
  98. AR8327_LED_INFO(PHY4_1, HW, "wd:yellow:wan"),
  99. };
  100. static struct ar8327_pad_cfg mynet_n750_ar8327_pad0_cfg = {
  101. .mode = AR8327_PAD_MAC_RGMII,
  102. .txclk_delay_en = true,
  103. .rxclk_delay_en = true,
  104. .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  105. .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  106. };
  107. static struct ar8327_led_cfg mynet_n750_ar8327_led_cfg = {
  108. .led_ctrl0 = 0xcc35cc35,
  109. .led_ctrl1 = 0xca35ca35,
  110. .led_ctrl2 = 0xc935c935,
  111. .led_ctrl3 = 0x03ffff00,
  112. .open_drain = false,
  113. };
  114. static struct ar8327_platform_data mynet_n750_ar8327_data = {
  115. .pad0_cfg = &mynet_n750_ar8327_pad0_cfg,
  116. .port0_cfg = {
  117. .force_link = 1,
  118. .speed = AR8327_PORT_SPEED_1000,
  119. .duplex = 1,
  120. .txpause = 1,
  121. .rxpause = 1,
  122. },
  123. .led_cfg = &mynet_n750_ar8327_led_cfg,
  124. .num_leds = ARRAY_SIZE(mynet_n750_leds_ar8327),
  125. .leds = mynet_n750_leds_ar8327,
  126. };
  127. static struct mdio_board_info mynet_n750_mdio0_info[] = {
  128. {
  129. .bus_id = "ag71xx-mdio.0",
  130. .phy_addr = 0,
  131. .platform_data = &mynet_n750_ar8327_data,
  132. },
  133. };
  134. static void mynet_n750_get_mac(const char *name, char *mac)
  135. {
  136. u8 *nvram = (u8 *) KSEG1ADDR(MYNET_N750_NVRAM_ADDR);
  137. int err;
  138. err = ath79_nvram_parse_mac_addr(nvram, MYNET_N750_NVRAM_SIZE,
  139. name, mac);
  140. if (err)
  141. pr_err("no MAC address found for %s\n", name);
  142. }
  143. /*
  144. * The bootloader on this board powers down all PHYs on the switch
  145. * before booting the kernel. We bring all PHYs back up so that they are
  146. * discoverable by the mdio bus scan and the switch is detected
  147. * correctly.
  148. */
  149. static void mynet_n750_mdio_fixup(struct mii_bus *bus)
  150. {
  151. int i;
  152. for (i = 0; i < 5; i++)
  153. bus->write(bus, i, MII_BMCR,
  154. (BMCR_RESET | BMCR_ANENABLE | BMCR_SPEED1000));
  155. mdelay(1000);
  156. }
  157. static void __init mynet_n750_setup(void)
  158. {
  159. u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  160. u8 tmpmac[ETH_ALEN];
  161. ath79_register_m25p80(NULL);
  162. ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_n750_leds_gpio),
  163. mynet_n750_leds_gpio);
  164. ath79_register_gpio_keys_polled(-1, MYNET_N750_KEYS_POLL_INTERVAL,
  165. ARRAY_SIZE(mynet_n750_gpio_keys),
  166. mynet_n750_gpio_keys);
  167. /*
  168. * Control signal for external LNAs 0 and 1
  169. * Taken from GPL bootloader source:
  170. * board/ar7240/db12x/alpha_gpio.c
  171. */
  172. ath79_wmac_set_ext_lna_gpio(0, MYNET_N750_GPIO_EXTERNAL_LNA0);
  173. ath79_wmac_set_ext_lna_gpio(1, MYNET_N750_GPIO_EXTERNAL_LNA1);
  174. mynet_n750_get_mac("wlan24mac=", tmpmac);
  175. ath79_register_wmac(art + MYNET_N750_WMAC_CALDATA_OFFSET, tmpmac);
  176. mynet_n750_get_mac("wlan5mac=", tmpmac);
  177. ap91_pci_init(art + MYNET_N750_PCIE_CALDATA_OFFSET, tmpmac);
  178. ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
  179. mdiobus_register_board_info(mynet_n750_mdio0_info,
  180. ARRAY_SIZE(mynet_n750_mdio0_info));
  181. ath79_mdio0_data.reset = mynet_n750_mdio_fixup;
  182. ath79_register_mdio(0, 0x0);
  183. mynet_n750_get_mac("lanmac=", ath79_eth0_data.mac_addr);
  184. /* GMAC0 is connected to an AR8327N switch */
  185. ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  186. ath79_eth0_data.phy_mask = BIT(0);
  187. ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  188. ath79_eth0_pll_data.pll_1000 = 0x06000000;
  189. ath79_register_eth(0);
  190. ath79_register_usb();
  191. }
  192. MIPS_MACHINE(ATH79_MACH_MYNET_N750, "MYNET-N750", "WD My Net N750",
  193. mynet_n750_setup);