mach-tl-wr1043nd-v2.c 6.0 KB

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  1. /*
  2. * TP-LINK TL-WR1043ND v2 board support
  3. *
  4. * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
  5. *
  6. * Based on the Qualcomm Atheros AP135/AP136 reference board support code
  7. * Copyright (c) 2012 Qualcomm Atheros
  8. *
  9. * Permission to use, copy, modify, and/or distribute this software for any
  10. * purpose with or without fee is hereby granted, provided that the above
  11. * copyright notice and this permission notice appear in all copies.
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  14. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  15. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  16. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  17. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  18. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  19. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  20. *
  21. */
  22. #include <linux/phy.h>
  23. #include <linux/gpio.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/ar8216_platform.h>
  26. #include <asm/mach-ath79/ar71xx_regs.h>
  27. #include "common.h"
  28. #include "dev-eth.h"
  29. #include "dev-gpio-buttons.h"
  30. #include "dev-leds-gpio.h"
  31. #include "dev-m25p80.h"
  32. #include "dev-spi.h"
  33. #include "dev-usb.h"
  34. #include "dev-wmac.h"
  35. #include "machtypes.h"
  36. #define TL_WR1043_V2_GPIO_LED_WLAN 12
  37. #define TL_WR1043_V2_GPIO_LED_USB 15
  38. #define TL_WR1043_V2_GPIO_LED_WPS 18
  39. #define TL_WR1043_V2_GPIO_LED_SYSTEM 19
  40. #define TL_WR1043_V2_GPIO_BTN_RESET 16
  41. #define TL_WR1043_V2_GPIO_BTN_RFKILL 17
  42. #define TL_WR1043_V2_GPIO_USB_POWER 21
  43. #define TL_WR1043_V2_KEYS_POLL_INTERVAL 20 /* msecs */
  44. #define TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1043_V2_KEYS_POLL_INTERVAL)
  45. #define TL_WR1043_V2_WMAC_CALDATA_OFFSET 0x1000
  46. static const char *wr1043nd_v2_part_probes[] = {
  47. "tp-link",
  48. NULL,
  49. };
  50. static struct flash_platform_data wr1043nd_v2_flash_data = {
  51. .part_probes = wr1043nd_v2_part_probes,
  52. };
  53. static struct gpio_led tl_wr1043_v2_leds_gpio[] __initdata = {
  54. {
  55. .name = "tp-link:green:wps",
  56. .gpio = TL_WR1043_V2_GPIO_LED_WPS,
  57. .active_low = 1,
  58. },
  59. {
  60. .name = "tp-link:green:system",
  61. .gpio = TL_WR1043_V2_GPIO_LED_SYSTEM,
  62. .active_low = 1,
  63. },
  64. {
  65. .name = "tp-link:green:wlan",
  66. .gpio = TL_WR1043_V2_GPIO_LED_WLAN,
  67. .active_low = 1,
  68. },
  69. {
  70. .name = "tp-link:green:usb",
  71. .gpio = TL_WR1043_V2_GPIO_LED_USB,
  72. .active_low = 1,
  73. },
  74. };
  75. static struct gpio_keys_button tl_wr1043_v2_gpio_keys[] __initdata = {
  76. {
  77. .desc = "Reset button",
  78. .type = EV_KEY,
  79. .code = KEY_RESTART,
  80. .debounce_interval = TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL,
  81. .gpio = TL_WR1043_V2_GPIO_BTN_RESET,
  82. .active_low = 1,
  83. },
  84. {
  85. .desc = "RFKILL button",
  86. .type = EV_KEY,
  87. .code = KEY_RFKILL,
  88. .debounce_interval = TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL,
  89. .gpio = TL_WR1043_V2_GPIO_BTN_RFKILL,
  90. .active_low = 1,
  91. },
  92. };
  93. static const struct ar8327_led_info tl_wr1043_leds_ar8327[] = {
  94. AR8327_LED_INFO(PHY0_0, HW, "tp-link:green:lan4"),
  95. AR8327_LED_INFO(PHY1_0, HW, "tp-link:green:lan3"),
  96. AR8327_LED_INFO(PHY2_0, HW, "tp-link:green:lan2"),
  97. AR8327_LED_INFO(PHY3_0, HW, "tp-link:green:lan1"),
  98. AR8327_LED_INFO(PHY4_0, HW, "tp-link:green:wan"),
  99. };
  100. /* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */
  101. static struct ar8327_pad_cfg wr1043nd_v2_ar8327_pad0_cfg = {
  102. .mode = AR8327_PAD_MAC_SGMII,
  103. .sgmii_delay_en = true,
  104. };
  105. /* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */
  106. static struct ar8327_pad_cfg wr1043nd_v2_ar8327_pad6_cfg = {
  107. .mode = AR8327_PAD_MAC_RGMII,
  108. .txclk_delay_en = true,
  109. .rxclk_delay_en = true,
  110. .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  111. .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  112. };
  113. static struct ar8327_led_cfg wr1043nd_v2_ar8327_led_cfg = {
  114. .led_ctrl0 = 0xcc35cc35,
  115. .led_ctrl1 = 0xca35ca35,
  116. .led_ctrl2 = 0xc935c935,
  117. .led_ctrl3 = 0x03ffff00,
  118. .open_drain = true,
  119. };
  120. static struct ar8327_platform_data wr1043nd_v2_ar8327_data = {
  121. .pad0_cfg = &wr1043nd_v2_ar8327_pad0_cfg,
  122. .pad6_cfg = &wr1043nd_v2_ar8327_pad6_cfg,
  123. .port0_cfg = {
  124. .force_link = 1,
  125. .speed = AR8327_PORT_SPEED_1000,
  126. .duplex = 1,
  127. .txpause = 1,
  128. .rxpause = 1,
  129. },
  130. .port6_cfg = {
  131. .force_link = 1,
  132. .speed = AR8327_PORT_SPEED_1000,
  133. .duplex = 1,
  134. .txpause = 1,
  135. .rxpause = 1,
  136. },
  137. .led_cfg = &wr1043nd_v2_ar8327_led_cfg,
  138. .num_leds = ARRAY_SIZE(tl_wr1043_leds_ar8327),
  139. .leds = tl_wr1043_leds_ar8327,
  140. };
  141. static struct mdio_board_info wr1043nd_v2_mdio0_info[] = {
  142. {
  143. .bus_id = "ag71xx-mdio.0",
  144. .phy_addr = 0,
  145. .platform_data = &wr1043nd_v2_ar8327_data,
  146. },
  147. };
  148. static void __init tl_wr1043nd_v2_setup(void)
  149. {
  150. u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  151. u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  152. ath79_register_m25p80(&wr1043nd_v2_flash_data);
  153. ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043_v2_leds_gpio),
  154. tl_wr1043_v2_leds_gpio);
  155. ath79_register_gpio_keys_polled(-1, TL_WR1043_V2_KEYS_POLL_INTERVAL,
  156. ARRAY_SIZE(tl_wr1043_v2_gpio_keys),
  157. tl_wr1043_v2_gpio_keys);
  158. ath79_register_wmac(art + TL_WR1043_V2_WMAC_CALDATA_OFFSET, mac);
  159. mdiobus_register_board_info(wr1043nd_v2_mdio0_info,
  160. ARRAY_SIZE(wr1043nd_v2_mdio0_info));
  161. ath79_register_mdio(0, 0x0);
  162. ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  163. /* GMAC0 is connected to the RMGII interface */
  164. ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  165. ath79_eth0_data.phy_mask = BIT(0);
  166. ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  167. ath79_eth0_pll_data.pll_1000 = 0x56000000;
  168. ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  169. ath79_register_eth(0);
  170. /* GMAC1 is connected to the SGMII interface */
  171. ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  172. ath79_eth1_data.speed = SPEED_1000;
  173. ath79_eth1_data.duplex = DUPLEX_FULL;
  174. ath79_eth1_pll_data.pll_1000 = 0x03000101;
  175. ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  176. ath79_register_eth(1);
  177. ath79_register_usb();
  178. gpio_request_one(TL_WR1043_V2_GPIO_USB_POWER,
  179. GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  180. "USB power");
  181. }
  182. MIPS_MACHINE(ATH79_MACH_TL_WR1043ND_V2, "TL-WR1043ND-v2",
  183. "TP-LINK TL-WR1043ND v2", tl_wr1043nd_v2_setup);