mach-wpj342.c 4.6 KB

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  1. /*
  2. * Compex WPJ342 board support
  3. *
  4. * Copyright (c) 2011 Qualcomm Atheros
  5. * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  6. *
  7. * Permission to use, copy, modify, and/or distribute this software for any
  8. * purpose with or without fee is hereby granted, provided that the above
  9. * copyright notice and this permission notice appear in all copies.
  10. *
  11. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18. *
  19. */
  20. #include <linux/irq.h>
  21. #include <linux/pci.h>
  22. #include <linux/phy.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/ath9k_platform.h>
  25. #include <linux/ar8216_platform.h>
  26. #include <linux/export.h>
  27. #include <asm/mach-ath79/ar71xx_regs.h>
  28. #include "pci.h"
  29. #include "common.h"
  30. #include "dev-ap9x-pci.h"
  31. #include "dev-eth.h"
  32. #include "dev-gpio-buttons.h"
  33. #include "dev-leds-gpio.h"
  34. #include "dev-m25p80.h"
  35. #include "dev-nfc.h"
  36. #include "dev-spi.h"
  37. #include "dev-usb.h"
  38. #include "dev-wmac.h"
  39. #include "machtypes.h"
  40. #define WPJ342_GPIO_LED_STATUS 11
  41. #define WPJ342_GPIO_LED_SIG1 14
  42. #define WPJ342_GPIO_LED_SIG2 13
  43. #define WPJ342_GPIO_LED_SIG3 12
  44. #define WPJ342_GPIO_LED_SIG4 11
  45. #define WPJ342_GPIO_BUZZER 15
  46. #define WPJ342_GPIO_BTN_RESET 17
  47. #define WPJ342_KEYS_POLL_INTERVAL 20 /* msecs */
  48. #define WPJ342_KEYS_DEBOUNCE_INTERVAL (3 * WPJ342_KEYS_POLL_INTERVAL)
  49. #define WPJ342_MAC0_OFFSET 0x10
  50. #define WPJ342_MAC1_OFFSET 0x18
  51. #define WPJ342_WMAC_CALDATA_OFFSET 0x1000
  52. #define WPJ342_PCIE_CALDATA_OFFSET 0x5000
  53. #define WPJ342_ART_SIZE 0x8000
  54. static struct gpio_led wpj342_leds_gpio[] __initdata = {
  55. {
  56. .name = "wpj342:red:sig1",
  57. .gpio = WPJ342_GPIO_LED_SIG1,
  58. .active_low = 1,
  59. },
  60. {
  61. .name = "wpj342:yellow:sig2",
  62. .gpio = WPJ342_GPIO_LED_SIG2,
  63. .active_low = 1,
  64. },
  65. {
  66. .name = "wpj342:green:sig3",
  67. .gpio = WPJ342_GPIO_LED_SIG3,
  68. .active_low = 1,
  69. },
  70. {
  71. .name = "wpj342:green:sig4",
  72. .gpio = WPJ342_GPIO_LED_SIG4,
  73. .active_low = 1,
  74. },
  75. {
  76. .name = "wpj342:buzzer",
  77. .gpio = WPJ342_GPIO_BUZZER,
  78. .active_low = 0,
  79. }
  80. };
  81. static struct gpio_keys_button wpj342_gpio_keys[] __initdata = {
  82. {
  83. .desc = "reset",
  84. .type = EV_KEY,
  85. .code = KEY_RESTART,
  86. .debounce_interval = WPJ342_KEYS_DEBOUNCE_INTERVAL,
  87. .gpio = WPJ342_GPIO_BTN_RESET,
  88. .active_low = 1,
  89. },
  90. };
  91. static struct ar8327_pad_cfg wpj342_ar8327_pad0_cfg = {
  92. .mode = AR8327_PAD_MAC_RGMII,
  93. .txclk_delay_en = true,
  94. .rxclk_delay_en = true,
  95. .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  96. .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  97. };
  98. static struct ar8327_led_cfg wpj342_ar8327_led_cfg = {
  99. .led_ctrl0 = 0x00000000,
  100. .led_ctrl1 = 0xc737c737,
  101. .led_ctrl2 = 0x00000000,
  102. .led_ctrl3 = 0x00c30c00,
  103. .open_drain = true,
  104. };
  105. static struct ar8327_platform_data wpj342_ar8327_data = {
  106. .pad0_cfg = &wpj342_ar8327_pad0_cfg,
  107. .port0_cfg = {
  108. .force_link = 1,
  109. .speed = AR8327_PORT_SPEED_1000,
  110. .duplex = 1,
  111. .txpause = 1,
  112. .rxpause = 1,
  113. },
  114. .led_cfg = &wpj342_ar8327_led_cfg,
  115. };
  116. static struct mdio_board_info wpj342_mdio0_info[] = {
  117. {
  118. .bus_id = "ag71xx-mdio.0",
  119. .phy_addr = 0,
  120. .platform_data = &wpj342_ar8327_data,
  121. },
  122. };
  123. static void __init wpj342_setup(void)
  124. {
  125. u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  126. u8 *mac = (u8 *) KSEG1ADDR(0x1f02e000);
  127. ath79_register_m25p80(NULL);
  128. ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj342_leds_gpio),
  129. wpj342_leds_gpio);
  130. ath79_register_gpio_keys_polled(-1, WPJ342_KEYS_POLL_INTERVAL,
  131. ARRAY_SIZE(wpj342_gpio_keys),
  132. wpj342_gpio_keys);
  133. ath79_register_usb();
  134. ath79_register_wmac(art + WPJ342_WMAC_CALDATA_OFFSET, NULL);
  135. ath79_register_pci();
  136. mdiobus_register_board_info(wpj342_mdio0_info,
  137. ARRAY_SIZE(wpj342_mdio0_info));
  138. ath79_register_mdio(1, 0x0);
  139. ath79_register_mdio(0, 0x0);
  140. ath79_init_mac(ath79_eth0_data.mac_addr, mac + WPJ342_MAC0_OFFSET, 0);
  141. ath79_init_mac(ath79_eth1_data.mac_addr, mac + WPJ342_MAC1_OFFSET, 0);
  142. ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_MII_GMAC0);
  143. /* GMAC0 is connected to an AR8236 switch */
  144. ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  145. ath79_eth0_data.phy_mask = BIT(0);
  146. ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  147. ath79_eth0_pll_data.pll_1000 = 0x06000000;
  148. ath79_register_eth(0);
  149. }
  150. MIPS_MACHINE(ATH79_MACH_WPJ342, "WPJ342", "Compex WPJ342", wpj342_setup);