mach-wzr-450hp2.c 5.9 KB

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  1. /*
  2. * Buffalo WZR-450HP2 board support
  3. *
  4. * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
  5. *
  6. * Based on the Qualcomm Atheros AP135/AP136 reference board support code
  7. * Copyright (c) 2012 Qualcomm Atheros
  8. *
  9. * Permission to use, copy, modify, and/or distribute this software for any
  10. * purpose with or without fee is hereby granted, provided that the above
  11. * copyright notice and this permission notice appear in all copies.
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  14. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  15. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  16. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  17. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  18. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  19. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  20. *
  21. */
  22. #include <linux/phy.h>
  23. #include <linux/gpio.h>
  24. #include <linux/mtd/mtd.h>
  25. #include <linux/mtd/partitions.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/ar8216_platform.h>
  28. #include <asm/mach-ath79/ar71xx_regs.h>
  29. #include "common.h"
  30. #include "dev-eth.h"
  31. #include "dev-gpio-buttons.h"
  32. #include "dev-leds-gpio.h"
  33. #include "dev-m25p80.h"
  34. #include "dev-spi.h"
  35. #include "dev-usb.h"
  36. #include "dev-wmac.h"
  37. #include "machtypes.h"
  38. #define WZR_450HP2_KEYS_POLL_INTERVAL 20 /* msecs */
  39. #define WZR_450HP2_KEYS_DEBOUNCE_INTERVAL (3 * WZR_450HP2_KEYS_POLL_INTERVAL)
  40. #define WZR_450HP2_WMAC_CALDATA_OFFSET 0x1000
  41. static struct mtd_partition wzrhpg450h_partitions[] = {
  42. {
  43. .name = "u-boot",
  44. .offset = 0,
  45. .size = 0x0040000,
  46. .mask_flags = MTD_WRITEABLE,
  47. }, {
  48. .name = "u-boot-env",
  49. .offset = 0x0040000,
  50. .size = 0x0010000,
  51. }, {
  52. .name = "ART",
  53. .offset = 0x0ff0000,
  54. .size = 0x0010000,
  55. .mask_flags = MTD_WRITEABLE,
  56. }, {
  57. .name = "firmware",
  58. .offset = 0x0050000,
  59. .size = 0x0f90000,
  60. }, {
  61. .name = "user_property",
  62. .offset = 0x0fe0000,
  63. .size = 0x0010000,
  64. }
  65. };
  66. static struct flash_platform_data wzr_450hp2_flash_data = {
  67. .parts = wzrhpg450h_partitions,
  68. .nr_parts = ARRAY_SIZE(wzrhpg450h_partitions),
  69. };
  70. static struct gpio_led wzr_450hp2_leds_gpio[] __initdata = {
  71. {
  72. .name = "buffalo:green:wps",
  73. .gpio = 3,
  74. .active_low = 1,
  75. },
  76. {
  77. .name = "buffalo:green:system",
  78. .gpio = 20,
  79. .active_low = 1,
  80. },
  81. {
  82. .name = "buffalo:green:wlan",
  83. .gpio = 18,
  84. .active_low = 1,
  85. },
  86. };
  87. static struct gpio_keys_button wzr_450hp2_gpio_keys[] __initdata = {
  88. {
  89. .desc = "Reset button",
  90. .type = EV_KEY,
  91. .code = KEY_RESTART,
  92. .debounce_interval = WZR_450HP2_KEYS_DEBOUNCE_INTERVAL,
  93. .gpio = 17,
  94. .active_low = 1,
  95. },
  96. {
  97. .desc = "RFKILL button",
  98. .type = EV_KEY,
  99. .code = KEY_RFKILL,
  100. .debounce_interval = WZR_450HP2_KEYS_DEBOUNCE_INTERVAL,
  101. .gpio = 21,
  102. .active_low = 1,
  103. },
  104. };
  105. static const struct ar8327_led_info wzr_450hp2_leds_ar8327[] = {
  106. AR8327_LED_INFO(PHY0_0, HW, "buffalo:green:lan1"),
  107. AR8327_LED_INFO(PHY1_0, HW, "buffalo:green:lan2"),
  108. AR8327_LED_INFO(PHY2_0, HW, "buffalo:green:lan3"),
  109. AR8327_LED_INFO(PHY3_0, HW, "buffalo:green:lan4"),
  110. AR8327_LED_INFO(PHY4_0, HW, "buffalo:green:wan"),
  111. };
  112. /* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */
  113. static struct ar8327_pad_cfg wzr_450hp2_ar8327_pad0_cfg = {
  114. .mode = AR8327_PAD_MAC_SGMII,
  115. .sgmii_delay_en = true,
  116. };
  117. /* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */
  118. static struct ar8327_pad_cfg wzr_450hp2_ar8327_pad6_cfg = {
  119. .mode = AR8327_PAD_MAC_RGMII,
  120. .txclk_delay_en = true,
  121. .rxclk_delay_en = true,
  122. .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  123. .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  124. };
  125. static struct ar8327_led_cfg wzr_450hp2_ar8327_led_cfg = {
  126. .led_ctrl0 = 0xcc35cc35,
  127. .led_ctrl1 = 0xca35ca35,
  128. .led_ctrl2 = 0xc935c935,
  129. .led_ctrl3 = 0x03ffff00,
  130. .open_drain = true,
  131. };
  132. static struct ar8327_platform_data wzr_450hp2_ar8327_data = {
  133. .pad0_cfg = &wzr_450hp2_ar8327_pad0_cfg,
  134. .pad6_cfg = &wzr_450hp2_ar8327_pad6_cfg,
  135. .port0_cfg = {
  136. .force_link = 1,
  137. .speed = AR8327_PORT_SPEED_1000,
  138. .duplex = 1,
  139. .txpause = 1,
  140. .rxpause = 1,
  141. },
  142. .port6_cfg = {
  143. .force_link = 1,
  144. .speed = AR8327_PORT_SPEED_1000,
  145. .duplex = 1,
  146. .txpause = 1,
  147. .rxpause = 1,
  148. },
  149. .led_cfg = &wzr_450hp2_ar8327_led_cfg,
  150. .num_leds = ARRAY_SIZE(wzr_450hp2_leds_ar8327),
  151. .leds = wzr_450hp2_leds_ar8327,
  152. };
  153. static struct mdio_board_info wzr_450hp2_mdio0_info[] = {
  154. {
  155. .bus_id = "ag71xx-mdio.0",
  156. .phy_addr = 0,
  157. .platform_data = &wzr_450hp2_ar8327_data,
  158. },
  159. };
  160. static void __init wzr_450hp2_setup(void)
  161. {
  162. u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  163. u8 *mac_wan = art;
  164. u8 *mac_lan = mac_wan + ETH_ALEN;
  165. ath79_register_m25p80(&wzr_450hp2_flash_data);
  166. ath79_register_leds_gpio(-1, ARRAY_SIZE(wzr_450hp2_leds_gpio),
  167. wzr_450hp2_leds_gpio);
  168. ath79_register_gpio_keys_polled(-1, WZR_450HP2_KEYS_POLL_INTERVAL,
  169. ARRAY_SIZE(wzr_450hp2_gpio_keys),
  170. wzr_450hp2_gpio_keys);
  171. ath79_register_wmac(art + WZR_450HP2_WMAC_CALDATA_OFFSET, mac_lan);
  172. mdiobus_register_board_info(wzr_450hp2_mdio0_info,
  173. ARRAY_SIZE(wzr_450hp2_mdio0_info));
  174. ath79_register_mdio(0, 0x0);
  175. ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  176. /* GMAC0 is connected to the RMGII interface */
  177. ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  178. ath79_eth0_data.phy_mask = BIT(0);
  179. ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  180. ath79_eth0_pll_data.pll_1000 = 0x56000000;
  181. ath79_init_mac(ath79_eth0_data.mac_addr, mac_wan, 0);
  182. ath79_register_eth(0);
  183. /* GMAC1 is connected to the SGMII interface */
  184. ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  185. ath79_eth1_data.speed = SPEED_1000;
  186. ath79_eth1_data.duplex = DUPLEX_FULL;
  187. ath79_eth1_pll_data.pll_1000 = 0x03000101;
  188. ath79_init_mac(ath79_eth1_data.mac_addr, mac_lan, 0);
  189. ath79_register_eth(1);
  190. ath79_register_usb();
  191. }
  192. MIPS_MACHINE(ATH79_MACH_WZR_450HP2, "WZR-450HP2",
  193. "Buffalo WZR-450HP2", wzr_450hp2_setup);