606-MIPS-ath79-pb44-fixes.patch 3.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146
  1. --- a/arch/mips/ath79/mach-pb44.c
  2. +++ b/arch/mips/ath79/mach-pb44.c
  3. @@ -8,23 +8,48 @@
  4. * by the Free Software Foundation.
  5. */
  6. +#include <linux/delay.h>
  7. #include <linux/init.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/i2c.h>
  10. #include <linux/i2c-gpio.h>
  11. #include <linux/i2c/pcf857x.h>
  12. +#include <linux/i2c/pcf857x.h>
  13. +#include <linux/spi/flash.h>
  14. +#include <linux/spi/vsc7385.h>
  15. -#include "machtypes.h"
  16. +#include <asm/mach-ath79/ar71xx_regs.h>
  17. +#include <asm/mach-ath79/ath79.h>
  18. +
  19. +#include "dev-eth.h"
  20. #include "dev-gpio-buttons.h"
  21. #include "dev-leds-gpio.h"
  22. #include "dev-spi.h"
  23. #include "dev-usb.h"
  24. +#include "machtypes.h"
  25. #include "pci.h"
  26. #define PB44_GPIO_I2C_SCL 0
  27. #define PB44_GPIO_I2C_SDA 1
  28. +#define PB44_PCF8757_VSC7395_CS 0
  29. +#define PB44_PCF8757_STEREO_CS 1
  30. +#define PB44_PCF8757_SLIC_CS0 2
  31. +#define PB44_PCF8757_SLIC_TEST 3
  32. +#define PB44_PCF8757_SLIC_INT0 4
  33. +#define PB44_PCF8757_SLIC_INT1 5
  34. +#define PB44_PCF8757_SW_RESET 6
  35. +#define PB44_PCF8757_SW_JUMP 8
  36. +#define PB44_PCF8757_LED_JUMP1 9
  37. +#define PB44_PCF8757_LED_JUMP2 10
  38. +#define PB44_PCF8757_TP24 11
  39. +#define PB44_PCF8757_TP25 12
  40. +#define PB44_PCF8757_TP26 13
  41. +#define PB44_PCF8757_TP27 14
  42. +#define PB44_PCF8757_TP28 15
  43. +
  44. #define PB44_GPIO_EXP_BASE 16
  45. +#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS)
  46. #define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6)
  47. #define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8)
  48. #define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9)
  49. @@ -87,20 +112,59 @@ static struct gpio_keys_button pb44_gpio
  50. }
  51. };
  52. +static void pb44_vsc7395_reset(void)
  53. +{
  54. + ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
  55. + udelay(10);
  56. + ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
  57. + mdelay(50);
  58. +}
  59. +
  60. +static struct vsc7385_platform_data pb44_vsc7395_data = {
  61. + .reset = pb44_vsc7395_reset,
  62. + .ucode_name = "vsc7395_ucode_pb44.bin",
  63. + .mac_cfg = {
  64. + .tx_ipg = 6,
  65. + .bit2 = 1,
  66. + .clk_sel = 0,
  67. + },
  68. +};
  69. +
  70. +static const char *pb44_part_probes[] = {
  71. + "RedBoot",
  72. + NULL,
  73. +};
  74. +
  75. +static struct flash_platform_data pb44_flash_data = {
  76. + .part_probes = pb44_part_probes,
  77. +};
  78. +
  79. static struct spi_board_info pb44_spi_info[] = {
  80. {
  81. .bus_num = 0,
  82. .chip_select = 0,
  83. .max_speed_hz = 25000000,
  84. .modalias = "m25p64",
  85. + .platform_data = &pb44_flash_data,
  86. },
  87. + {
  88. + .bus_num = 0,
  89. + .chip_select = 1,
  90. + .max_speed_hz = 25000000,
  91. + .modalias = "spi-vsc7385",
  92. + .platform_data = &pb44_vsc7395_data,
  93. + }
  94. };
  95. static struct ath79_spi_platform_data pb44_spi_data = {
  96. .bus_num = 0,
  97. - .num_chipselect = 1,
  98. + .num_chipselect = 2,
  99. };
  100. +#define PB44_WAN_PHYMASK BIT(0)
  101. +#define PB44_LAN_PHYMASK 0
  102. +#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK)
  103. +
  104. static void __init pb44_init(void)
  105. {
  106. i2c_register_board_info(0, pb44_i2c_board_info,
  107. @@ -116,6 +180,22 @@ static void __init pb44_init(void)
  108. ARRAY_SIZE(pb44_spi_info));
  109. ath79_register_usb();
  110. ath79_register_pci();
  111. +
  112. + ath79_register_mdio(0, ~PB44_MDIO_PHYMASK);
  113. +
  114. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  115. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  116. + ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK;
  117. +
  118. + ath79_register_eth(0);
  119. +
  120. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
  121. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  122. + ath79_eth1_data.speed = SPEED_1000;
  123. + ath79_eth1_data.duplex = DUPLEX_FULL;
  124. + ath79_eth1_pll_data.pll_1000 = 0x110000;
  125. +
  126. + ath79_register_eth(1);
  127. }
  128. MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
  129. --- a/arch/mips/ath79/Kconfig
  130. +++ b/arch/mips/ath79/Kconfig
  131. @@ -57,6 +57,7 @@ config ATH79_MACH_DB120
  132. config ATH79_MACH_PB44
  133. bool "Atheros PB44 reference board"
  134. select SOC_AR71XX
  135. + select ATH79_DEV_ETH
  136. select ATH79_DEV_GPIO_BUTTONS
  137. select ATH79_DEV_LEDS_GPIO
  138. select ATH79_DEV_SPI