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mt7628an.dtsi 8.2 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "ralink,mtk7628an-soc";
  5. cpus {
  6. cpu@0 {
  7. compatible = "mips,mips24KEc";
  8. };
  9. };
  10. chosen {
  11. bootargs = "console=ttyS0,57600";
  12. };
  13. aliases {
  14. serial0 = &uartlite;
  15. };
  16. cpuintc: cpuintc@0 {
  17. #address-cells = <0>;
  18. #interrupt-cells = <1>;
  19. interrupt-controller;
  20. compatible = "mti,cpu-interrupt-controller";
  21. };
  22. palmbus: palmbus@10000000 {
  23. compatible = "palmbus";
  24. reg = <0x10000000 0x200000>;
  25. ranges = <0x0 0x10000000 0x1FFFFF>;
  26. #address-cells = <1>;
  27. #size-cells = <1>;
  28. sysc: sysc@0 {
  29. compatible = "ralink,mt7620a-sysc";
  30. reg = <0x0 0x100>;
  31. };
  32. watchdog: watchdog@120 {
  33. compatible = "ralink,mt7628an-wdt", "mtk,mt7621-wdt";
  34. reg = <0x120 0x10>;
  35. resets = <&rstctrl 8>;
  36. reset-names = "wdt";
  37. interrupt-parent = <&intc>;
  38. interrupts = <24>;
  39. };
  40. intc: intc@200 {
  41. compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
  42. reg = <0x200 0x100>;
  43. resets = <&rstctrl 9>;
  44. reset-names = "intc";
  45. interrupt-controller;
  46. #interrupt-cells = <1>;
  47. interrupt-parent = <&cpuintc>;
  48. interrupts = <2>;
  49. ralink,intc-registers = <0x9c 0xa0
  50. 0x6c 0xa4
  51. 0x80 0x78>;
  52. };
  53. memc: memc@300 {
  54. compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
  55. reg = <0x300 0x100>;
  56. resets = <&rstctrl 20>;
  57. reset-names = "mc";
  58. interrupt-parent = <&intc>;
  59. interrupts = <3>;
  60. };
  61. gpio@600 {
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
  65. reg = <0x600 0x100>;
  66. interrupt-parent = <&intc>;
  67. interrupts = <6>;
  68. gpio0: bank@0 {
  69. reg = <0>;
  70. compatible = "mtk,mt7621-gpio-bank";
  71. gpio-controller;
  72. #gpio-cells = <2>;
  73. };
  74. gpio1: bank@1 {
  75. reg = <1>;
  76. compatible = "mtk,mt7621-gpio-bank";
  77. gpio-controller;
  78. #gpio-cells = <2>;
  79. };
  80. gpio2: bank@2 {
  81. reg = <2>;
  82. compatible = "mtk,mt7621-gpio-bank";
  83. gpio-controller;
  84. #gpio-cells = <2>;
  85. };
  86. };
  87. i2c: i2c@900 {
  88. compatible = "mediatek,mt7621-i2c";
  89. reg = <0x900 0x100>;
  90. resets = <&rstctrl 16>;
  91. reset-names = "i2c";
  92. #address-cells = <1>;
  93. #size-cells = <0>;
  94. status = "disabled";
  95. pinctrl-names = "default";
  96. pinctrl-0 = <&i2c_pins>;
  97. };
  98. i2s: i2s@a00 {
  99. compatible = "mediatek,mt7628-i2s";
  100. reg = <0xa00 0x100>;
  101. resets = <&rstctrl 17>;
  102. reset-names = "i2s";
  103. interrupt-parent = <&intc>;
  104. interrupts = <10>;
  105. txdma-req = <2>;
  106. rxdma-req = <3>;
  107. dmas = <&gdma 4>,
  108. <&gdma 6>;
  109. dma-names = "tx", "rx";
  110. status = "disabled";
  111. };
  112. spi0: spi@b00 {
  113. compatible = "ralink,mt7621-spi";
  114. reg = <0xb00 0x100>;
  115. resets = <&rstctrl 18>;
  116. reset-names = "spi";
  117. #address-cells = <1>;
  118. #size-cells = <0>;
  119. pinctrl-names = "default";
  120. pinctrl-0 = <&spi_pins>;
  121. status = "disabled";
  122. };
  123. uartlite: uartlite@c00 {
  124. compatible = "ns16550a";
  125. reg = <0xc00 0x100>;
  126. reg-shift = <2>;
  127. reg-io-width = <4>;
  128. no-loopback-test;
  129. clock-frequency = <40000000>;
  130. resets = <&rstctrl 12>;
  131. reset-names = "uartl";
  132. interrupt-parent = <&intc>;
  133. interrupts = <20>;
  134. pinctrl-names = "default";
  135. pinctrl-0 = <&uart0_pins>;
  136. };
  137. uart1: uart1@d00 {
  138. compatible = "ns16550a";
  139. reg = <0xd00 0x100>;
  140. reg-shift = <2>;
  141. reg-io-width = <4>;
  142. no-loopback-test;
  143. clock-frequency = <40000000>;
  144. resets = <&rstctrl 19>;
  145. reset-names = "uart1";
  146. interrupt-parent = <&intc>;
  147. interrupts = <21>;
  148. pinctrl-names = "default";
  149. pinctrl-0 = <&uart1_pins>;
  150. status = "disabled";
  151. };
  152. uart2: uart2@e00 {
  153. compatible = "ns16550a";
  154. reg = <0xe00 0x100>;
  155. reg-shift = <2>;
  156. reg-io-width = <4>;
  157. no-loopback-test;
  158. clock-frequency = <40000000>;
  159. resets = <&rstctrl 20>;
  160. reset-names = "uart2";
  161. interrupt-parent = <&intc>;
  162. interrupts = <22>;
  163. pinctrl-names = "default";
  164. pinctrl-0 = <&uart2_pins>;
  165. status = "disabled";
  166. };
  167. pwm: pwm@5000 {
  168. compatible = "mediatek,mt7628-pwm";
  169. reg = <0x5000 0x1000>;
  170. resets = <&rstctrl 31>;
  171. reset-names = "pwm";
  172. pinctrl-names = "default";
  173. pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
  174. status = "disabled";
  175. };
  176. pcm: pcm@2000 {
  177. compatible = "ralink,mt7620a-pcm";
  178. reg = <0x2000 0x800>;
  179. resets = <&rstctrl 11>;
  180. reset-names = "pcm";
  181. interrupt-parent = <&intc>;
  182. interrupts = <4>;
  183. status = "disabled";
  184. };
  185. gdma: gdma@2800 {
  186. compatible = "ralink,rt3883-gdma";
  187. reg = <0x2800 0x800>;
  188. resets = <&rstctrl 14>;
  189. reset-names = "dma";
  190. interrupt-parent = <&intc>;
  191. interrupts = <7>;
  192. #dma-cells = <1>;
  193. #dma-channels = <16>;
  194. #dma-requests = <16>;
  195. status = "disabled";
  196. };
  197. };
  198. pinctrl: pinctrl {
  199. compatible = "ralink,rt2880-pinmux";
  200. pinctrl-names = "default";
  201. pinctrl-0 = <&state_default>;
  202. state_default: pinctrl0 {
  203. };
  204. spi_pins: spi {
  205. spi {
  206. ralink,group = "spi";
  207. ralink,function = "spi";
  208. };
  209. };
  210. spi_cs1_pins: spi_cs1 {
  211. spi_cs1 {
  212. ralink,group = "spi cs1";
  213. ralink,function = "spi cs1";
  214. };
  215. };
  216. i2c_pins: i2c {
  217. i2c {
  218. ralink,group = "i2c";
  219. ralink,function = "i2c";
  220. };
  221. };
  222. uart0_pins: uartlite {
  223. uartlite {
  224. ralink,group = "uart0";
  225. ralink,function = "uart0";
  226. };
  227. };
  228. uart1_pins: uart1 {
  229. uart1 {
  230. ralink,group = "uart1";
  231. ralink,function = "uart1";
  232. };
  233. };
  234. uart2_pins: uart2 {
  235. uart2 {
  236. ralink,group = "uart2";
  237. ralink,function = "uart2";
  238. };
  239. };
  240. sdxc_pins: sdxc {
  241. sdxc {
  242. ralink,group = "sdmode";
  243. ralink,function = "sdxc";
  244. };
  245. };
  246. pwm0_pins: pwm0 {
  247. pwm0 {
  248. ralink,group = "pwm0";
  249. ralink,function = "pwm0";
  250. };
  251. };
  252. pwm1_pins: pwm1 {
  253. pwm1 {
  254. ralink,group = "pwm1";
  255. ralink,function = "pwm1";
  256. };
  257. };
  258. pcm_i2s_pins: i2s {
  259. i2s {
  260. ralink,group = "i2s";
  261. ralink,function = "pcm";
  262. };
  263. };
  264. };
  265. rstctrl: rstctrl {
  266. compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
  267. #reset-cells = <1>;
  268. };
  269. clkctrl: clkctrl {
  270. compatible = "ralink,rt2880-clock";
  271. #clock-cells = <1>;
  272. };
  273. usbphy: usbphy@10120000 {
  274. compatible = "ralink,mt7628an-usbphy", "mediatek,mt7620-usbphy";
  275. reg = <0x10120000 0x1000>;
  276. #phy-cells = <1>;
  277. resets = <&rstctrl 22 &rstctrl 25>;
  278. reset-names = "host", "device";
  279. clocks = <&clkctrl 22 &clkctrl 25>;
  280. clock-names = "host", "device";
  281. };
  282. sdhci: sdhci@10130000 {
  283. compatible = "ralink,mt7620-sdhci";
  284. reg = <0x10130000 0x4000>;
  285. interrupt-parent = <&intc>;
  286. interrupts = <14>;
  287. pinctrl-names = "default";
  288. pinctrl-0 = <&sdxc_pins>;
  289. status = "disabled";
  290. };
  291. ehci: ehci@101c0000 {
  292. compatible = "generic-ehci";
  293. reg = <0x101c0000 0x1000>;
  294. phys = <&usbphy 1>;
  295. phy-names = "usb";
  296. interrupt-parent = <&intc>;
  297. interrupts = <18>;
  298. };
  299. ohci: ohci@101c1000 {
  300. compatible = "generic-ohci";
  301. reg = <0x101c1000 0x1000>;
  302. phys = <&usbphy 1>;
  303. phy-names = "usb";
  304. interrupt-parent = <&intc>;
  305. interrupts = <18>;
  306. };
  307. ethernet: ethernet@10100000 {
  308. compatible = "ralink,rt5350-eth";
  309. reg = <0x10100000 0x10000>;
  310. interrupt-parent = <&cpuintc>;
  311. interrupts = <5>;
  312. resets = <&rstctrl 21 &rstctrl 23>;
  313. reset-names = "fe", "esw";
  314. mediatek,switch = <&esw>;
  315. };
  316. esw: esw@10110000 {
  317. compatible = "mediatek,mt7628-esw", "ralink,rt3050-esw";
  318. reg = <0x10110000 0x8000>;
  319. resets = <&rstctrl 23>;
  320. reset-names = "esw";
  321. interrupt-parent = <&intc>;
  322. interrupts = <17>;
  323. };
  324. pcie: pcie@10140000 {
  325. compatible = "mediatek,mt7620-pci";
  326. reg = <0x10140000 0x100
  327. 0x10142000 0x100>;
  328. #address-cells = <3>;
  329. #size-cells = <2>;
  330. interrupt-parent = <&cpuintc>;
  331. interrupts = <4>;
  332. resets = <&rstctrl 26 &rstctrl 27>;
  333. reset-names = "pcie0", "pcie1";
  334. clocks = <&clkctrl 26 &clkctrl 27>;
  335. clock-names = "pcie0", "pcie1";
  336. status = "disabled";
  337. device_type = "pci";
  338. bus-range = <0 255>;
  339. ranges = <
  340. 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
  341. 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
  342. >;
  343. pcie-bridge {
  344. reg = <0x0000 0 0 0 0>;
  345. #address-cells = <3>;
  346. #size-cells = <2>;
  347. device_type = "pci";
  348. };
  349. };
  350. wmac: wmac@10300000 {
  351. compatible = "mediatek,mt7628-wmac";
  352. reg = <0x10300000 0x100000>;
  353. interrupt-parent = <&cpuintc>;
  354. interrupts = <6>;
  355. status = "disabled";
  356. mediatek,mtd-eeprom = <&factory 0x0000>;
  357. mediatek,5ghz = <0>;
  358. };
  359. };