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0001-arch-mips-ralink-add-mt7621-support.patch 12 KB

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  1. From 450b6e8257e22708173d0c1c86d34394fba0c5eb Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Mon, 7 Dec 2015 17:08:31 +0100
  4. Subject: [PATCH 01/53] arch: mips: ralink: add mt7621 support
  5. Signed-off-by: John Crispin <blogic@openwrt.org>
  6. ---
  7. arch/mips/include/asm/mach-ralink/irq.h | 9 +
  8. arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++
  9. arch/mips/kernel/mips-cm.c | 4 +-
  10. arch/mips/kernel/vmlinux.lds.S | 1 +
  11. arch/mips/ralink/Kconfig | 18 ++
  12. arch/mips/ralink/Makefile | 7 +-
  13. arch/mips/ralink/Platform | 5 +
  14. arch/mips/ralink/irq-gic.c | 268 ++++++++++++++++++++++++++++
  15. arch/mips/ralink/malta-amon.c | 81 +++++++++
  16. arch/mips/ralink/mt7621.c | 209 ++++++++++++++++++++++
  17. 10 files changed, 638 insertions(+), 3 deletions(-)
  18. create mode 100644 arch/mips/include/asm/mach-ralink/irq.h
  19. create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
  20. create mode 100644 arch/mips/ralink/irq-gic.c
  21. create mode 100644 arch/mips/ralink/malta-amon.c
  22. create mode 100644 arch/mips/ralink/mt7621.c
  23. --- /dev/null
  24. +++ b/arch/mips/include/asm/mach-ralink/irq.h
  25. @@ -0,0 +1,9 @@
  26. +#ifndef __ASM_MACH_RALINK_IRQ_H
  27. +#define __ASM_MACH_RALINK_IRQ_H
  28. +
  29. +#define GIC_NUM_INTRS 64
  30. +#define NR_IRQS 256
  31. +
  32. +#include_next <irq.h>
  33. +
  34. +#endif
  35. --- /dev/null
  36. +++ b/arch/mips/include/asm/mach-ralink/mt7621.h
  37. @@ -0,0 +1,42 @@
  38. +/*
  39. + * This program is free software; you can redistribute it and/or modify it
  40. + * under the terms of the GNU General Public License version 2 as published
  41. + * by the Free Software Foundation.
  42. + *
  43. + * Parts of this file are based on Ralink's 2.6.21 BSP
  44. + *
  45. + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  46. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  47. + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  48. + */
  49. +
  50. +#ifndef _MT7621_REGS_H_
  51. +#define _MT7621_REGS_H_
  52. +
  53. +#define MT7621_PALMBUS_BASE 0x1C000000
  54. +#define MT7621_PALMBUS_SIZE 0x03FFFFFF
  55. +
  56. +#define MT7621_SYSC_BASE 0x1E000000
  57. +
  58. +#define SYSC_REG_CHIP_NAME0 0x00
  59. +#define SYSC_REG_CHIP_NAME1 0x04
  60. +#define SYSC_REG_CHIP_REV 0x0c
  61. +#define SYSC_REG_SYSTEM_CONFIG0 0x10
  62. +#define SYSC_REG_SYSTEM_CONFIG1 0x14
  63. +
  64. +#define CHIP_REV_PKG_MASK 0x1
  65. +#define CHIP_REV_PKG_SHIFT 16
  66. +#define CHIP_REV_VER_MASK 0xf
  67. +#define CHIP_REV_VER_SHIFT 8
  68. +#define CHIP_REV_ECO_MASK 0xf
  69. +
  70. +#define MT7621_DRAM_BASE 0x0
  71. +#define MT7621_DDR2_SIZE_MIN 32
  72. +#define MT7621_DDR2_SIZE_MAX 256
  73. +
  74. +#define MT7621_CHIP_NAME0 0x3637544D
  75. +#define MT7621_CHIP_NAME1 0x20203132
  76. +
  77. +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
  78. +
  79. +#endif
  80. --- a/arch/mips/kernel/vmlinux.lds.S
  81. +++ b/arch/mips/kernel/vmlinux.lds.S
  82. @@ -53,6 +53,7 @@ SECTIONS
  83. /* read-only */
  84. _text = .; /* Text and read-only data */
  85. .text : {
  86. + /*. = . + 0x8000; */
  87. TEXT_TEXT
  88. SCHED_TEXT
  89. LOCK_TEXT
  90. --- a/arch/mips/ralink/Kconfig
  91. +++ b/arch/mips/ralink/Kconfig
  92. @@ -12,6 +12,11 @@ config RALINK_ILL_ACC
  93. depends on SOC_RT305X
  94. default y
  95. +config IRQ_INTC
  96. + bool
  97. + default y
  98. + depends on !SOC_MT7621
  99. +
  100. choice
  101. prompt "Ralink SoC selection"
  102. default SOC_RT305X
  103. @@ -34,6 +39,16 @@ choice
  104. config SOC_MT7620
  105. bool "MT7620/8"
  106. + config SOC_MT7621
  107. + bool "MT7621"
  108. + select MIPS_CPU_SCACHE
  109. + select SYS_SUPPORTS_MULTITHREADING
  110. + select SYS_SUPPORTS_SMP
  111. + select SYS_SUPPORTS_MIPS_CPS
  112. + select MIPS_GIC
  113. + select COMMON_CLK
  114. + select CLKSRC_MIPS_GIC
  115. + select HW_HAS_PCI
  116. endchoice
  117. choice
  118. @@ -65,6 +80,10 @@ choice
  119. depends on SOC_MT7620
  120. select BUILTIN_DTB
  121. + config DTB_MT7621_EVAL
  122. + bool "MT7621 eval kit"
  123. + depends on SOC_MT7621
  124. +
  125. endchoice
  126. endif
  127. --- a/arch/mips/ralink/Makefile
  128. +++ b/arch/mips/ralink/Makefile
  129. @@ -6,16 +6,24 @@
  130. # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  131. # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  132. -obj-y := prom.o of.o reset.o clk.o irq.o timer.o
  133. +obj-y := prom.o of.o reset.o
  134. +
  135. +ifndef CONFIG_MIPS_GIC
  136. + obj-y += clk.o timer.o
  137. +endif
  138. obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
  139. obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
  140. +obj-$(CONFIG_IRQ_INTC) += irq.o
  141. +obj-$(CONFIG_MIPS_GIC) += irq-gic.o timer-gic.o
  142. +
  143. obj-$(CONFIG_SOC_RT288X) += rt288x.o
  144. obj-$(CONFIG_SOC_RT305X) += rt305x.o
  145. obj-$(CONFIG_SOC_RT3883) += rt3883.o
  146. obj-$(CONFIG_SOC_MT7620) += mt7620.o
  147. +obj-$(CONFIG_SOC_MT7621) += mt7621.o
  148. obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
  149. --- a/arch/mips/ralink/Platform
  150. +++ b/arch/mips/ralink/Platform
  151. @@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr
  152. #
  153. load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
  154. cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
  155. +
  156. +# Ralink MT7621
  157. +#
  158. +load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
  159. +cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
  160. --- /dev/null
  161. +++ b/arch/mips/ralink/irq-gic.c
  162. @@ -0,0 +1,18 @@
  163. +#include <linux/init.h>
  164. +
  165. +#include <linux/of.h>
  166. +#include <linux/irqchip.h>
  167. +#include <linux/irqchip/mips-gic.h>
  168. +
  169. +int get_c0_perfcount_int(void)
  170. +{
  171. + return gic_get_c0_perfcount_int();
  172. +}
  173. +EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
  174. +
  175. +void __init
  176. +arch_init_irq(void)
  177. +{
  178. + irqchip_init();
  179. +}
  180. +
  181. --- /dev/null
  182. +++ b/arch/mips/ralink/mt7621.c
  183. @@ -0,0 +1,223 @@
  184. +/*
  185. + * This program is free software; you can redistribute it and/or modify it
  186. + * under the terms of the GNU General Public License version 2 as published
  187. + * by the Free Software Foundation.
  188. + *
  189. + * Parts of this file are based on Ralink's 2.6.21 BSP
  190. + *
  191. + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  192. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  193. + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  194. + */
  195. +
  196. +#include <linux/kernel.h>
  197. +#include <linux/init.h>
  198. +#include <linux/module.h>
  199. +
  200. +#include <asm/mipsregs.h>
  201. +#include <asm/smp-ops.h>
  202. +#include <asm/mips-cm.h>
  203. +#include <asm/mips-cpc.h>
  204. +#include <asm/mach-ralink/ralink_regs.h>
  205. +#include <asm/mach-ralink/mt7621.h>
  206. +
  207. +#include <pinmux.h>
  208. +
  209. +#include "common.h"
  210. +
  211. +#define SYSC_REG_SYSCFG 0x10
  212. +#define SYSC_REG_CPLL_CLKCFG0 0x2c
  213. +#define SYSC_REG_CUR_CLK_STS 0x44
  214. +#define CPU_CLK_SEL (BIT(30) | BIT(31))
  215. +
  216. +#define MT7621_GPIO_MODE_UART1 1
  217. +#define MT7621_GPIO_MODE_I2C 2
  218. +#define MT7621_GPIO_MODE_UART3_MASK 0x3
  219. +#define MT7621_GPIO_MODE_UART3_SHIFT 3
  220. +#define MT7621_GPIO_MODE_UART3_GPIO 1
  221. +#define MT7621_GPIO_MODE_UART2_MASK 0x3
  222. +#define MT7621_GPIO_MODE_UART2_SHIFT 5
  223. +#define MT7621_GPIO_MODE_UART2_GPIO 1
  224. +#define MT7621_GPIO_MODE_JTAG 7
  225. +#define MT7621_GPIO_MODE_WDT_MASK 0x3
  226. +#define MT7621_GPIO_MODE_WDT_SHIFT 8
  227. +#define MT7621_GPIO_MODE_WDT_GPIO 1
  228. +#define MT7621_GPIO_MODE_PCIE_RST 0
  229. +#define MT7621_GPIO_MODE_PCIE_REF 2
  230. +#define MT7621_GPIO_MODE_PCIE_MASK 0x3
  231. +#define MT7621_GPIO_MODE_PCIE_SHIFT 10
  232. +#define MT7621_GPIO_MODE_PCIE_GPIO 1
  233. +#define MT7621_GPIO_MODE_MDIO_MASK 0x3
  234. +#define MT7621_GPIO_MODE_MDIO_SHIFT 12
  235. +#define MT7621_GPIO_MODE_MDIO_GPIO 1
  236. +#define MT7621_GPIO_MODE_RGMII1 14
  237. +#define MT7621_GPIO_MODE_RGMII2 15
  238. +#define MT7621_GPIO_MODE_SPI_MASK 0x3
  239. +#define MT7621_GPIO_MODE_SPI_SHIFT 16
  240. +#define MT7621_GPIO_MODE_SPI_GPIO 1
  241. +#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
  242. +#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
  243. +#define MT7621_GPIO_MODE_SDHCI_GPIO 1
  244. +
  245. +static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
  246. +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
  247. +static struct rt2880_pmx_func uart3_grp[] = {
  248. + FUNC("uart3", 0, 5, 4),
  249. + FUNC("i2s", 2, 5, 4),
  250. + FUNC("spdif3", 3, 5, 4),
  251. +};
  252. +static struct rt2880_pmx_func uart2_grp[] = {
  253. + FUNC("uart2", 0, 9, 4),
  254. + FUNC("pcm", 2, 9, 4),
  255. + FUNC("spdif2", 3, 9, 4),
  256. +};
  257. +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
  258. +static struct rt2880_pmx_func wdt_grp[] = {
  259. + FUNC("wdt rst", 0, 18, 1),
  260. + FUNC("wdt refclk", 2, 18, 1),
  261. +};
  262. +static struct rt2880_pmx_func pcie_rst_grp[] = {
  263. + FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
  264. + FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
  265. +};
  266. +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
  267. +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
  268. +static struct rt2880_pmx_func spi_grp[] = {
  269. + FUNC("spi", 0, 34, 7),
  270. + FUNC("nand1", 2, 34, 7),
  271. +};
  272. +static struct rt2880_pmx_func sdhci_grp[] = {
  273. + FUNC("sdhci", 0, 41, 8),
  274. + FUNC("nand2", 2, 41, 8),
  275. +};
  276. +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
  277. +
  278. +static struct rt2880_pmx_group mt7621_pinmux_data[] = {
  279. + GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
  280. + GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
  281. + GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
  282. + MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
  283. + GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
  284. + MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
  285. + GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
  286. + GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
  287. + MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
  288. + GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
  289. + MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
  290. + GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
  291. + MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
  292. + GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
  293. + GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
  294. + MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
  295. + GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
  296. + MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
  297. + GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
  298. + { 0 }
  299. +};
  300. +
  301. +phys_addr_t mips_cpc_default_phys_base() {
  302. + panic("Cannot detect cpc address");
  303. +}
  304. +
  305. +void __init ralink_clk_init(void)
  306. +{
  307. + int cpu_fdiv = 0;
  308. + int cpu_ffrac = 0;
  309. + int fbdiv = 0;
  310. + u32 clk_sts, syscfg;
  311. + u8 clk_sel = 0, xtal_mode;
  312. + u32 cpu_clk;
  313. +
  314. + if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
  315. + clk_sel = 1;
  316. +
  317. + switch (clk_sel) {
  318. + case 0:
  319. + clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
  320. + cpu_fdiv = ((clk_sts >> 8) & 0x1F);
  321. + cpu_ffrac = (clk_sts & 0x1F);
  322. + cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
  323. + break;
  324. +
  325. + case 1:
  326. + fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
  327. + syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
  328. + xtal_mode = (syscfg >> 6) & 0x7;
  329. + if(xtal_mode >= 6) { //25Mhz Xtal
  330. + cpu_clk = 25 * fbdiv * 1000 * 1000;
  331. + } else if(xtal_mode >=3) { //40Mhz Xtal
  332. + cpu_clk = 40 * fbdiv * 1000 * 1000;
  333. + } else { // 20Mhz Xtal
  334. + cpu_clk = 20 * fbdiv * 1000 * 1000;
  335. + }
  336. + break;
  337. + }
  338. +}
  339. +
  340. +void __init ralink_of_remap(void)
  341. +{
  342. + rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
  343. + rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
  344. +
  345. + if (!rt_sysc_membase || !rt_memc_membase)
  346. + panic("Failed to remap core resources");
  347. +}
  348. +
  349. +void prom_soc_init(struct ralink_soc_info *soc_info)
  350. +{
  351. + void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
  352. + unsigned char *name = NULL;
  353. + u32 n0;
  354. + u32 n1;
  355. + u32 rev;
  356. +
  357. + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
  358. + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
  359. +
  360. + if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
  361. + name = "MT7621";
  362. + soc_info->compatible = "mtk,mt7621-soc";
  363. + } else {
  364. + panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
  365. + }
  366. +
  367. + rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
  368. +
  369. + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
  370. + "MediaTek %s ver:%u eco:%u",
  371. + name,
  372. + (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
  373. + (rev & CHIP_REV_ECO_MASK));
  374. +
  375. + soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
  376. + soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
  377. + soc_info->mem_base = MT7621_DRAM_BASE;
  378. +
  379. + rt2880_pinmux_data = mt7621_pinmux_data;
  380. +
  381. + /* Early detection of CMP support */
  382. + mips_cm_probe();
  383. + mips_cpc_probe();
  384. +
  385. + if (mips_cm_numiocu()) {
  386. + /* mips_cm_probe() wipes out bootloader
  387. + config for CM regions and we have to configure them
  388. + again. This SoC cannot talk to pamlbus devices
  389. + witout proper iocu region set up.
  390. +
  391. + FIXME: it would be better to do this with values
  392. + from DT, but we need this very early because
  393. + without this we cannot talk to pretty much anything
  394. + including serial.
  395. + */
  396. + write_gcr_reg0_base(MT7621_PALMBUS_BASE);
  397. + write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE | CM_GCR_REGn_MASK_CMTGT_IOCU0);
  398. + }
  399. +
  400. + if (!register_cps_smp_ops())
  401. + return;
  402. + if (!register_cmp_smp_ops())
  403. + return;
  404. + if (!register_vsmp_smp_ops())
  405. + return;
  406. +}
  407. --- /dev/null
  408. +++ b/arch/mips/ralink/timer-gic.c
  409. @@ -0,0 +1,15 @@
  410. +#include <linux/init.h>
  411. +
  412. +#include <linux/of.h>
  413. +#include <linux/clk-provider.h>
  414. +#include <linux/clocksource.h>
  415. +
  416. +#include "common.h"
  417. +
  418. +void __init plat_time_init(void)
  419. +{
  420. + ralink_of_remap();
  421. +
  422. + of_clk_init(NULL);
  423. + clocksource_probe();
  424. +}