0009-PCI-MIPS-adds-mt7620a-pcie-driver.patch 11 KB

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  1. From 41aa7fc236fdb1f4c9b8b10df9b71f0d248cb36b Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Mon, 7 Dec 2015 17:11:12 +0100
  4. Subject: [PATCH 09/53] PCI: MIPS: adds mt7620a pcie driver
  5. Signed-off-by: John Crispin <blogic@openwrt.org>
  6. ---
  7. arch/mips/include/asm/mach-ralink/mt7620.h | 1 +
  8. arch/mips/pci/Makefile | 1 +
  9. arch/mips/pci/pci-mt7620.c | 396 ++++++++++++++++++++++++++++
  10. arch/mips/ralink/Kconfig | 1 +
  11. 4 files changed, 399 insertions(+)
  12. create mode 100644 arch/mips/pci/pci-mt7620.c
  13. --- a/arch/mips/pci/Makefile
  14. +++ b/arch/mips/pci/Makefile
  15. @@ -43,6 +43,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
  16. obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
  17. obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
  18. obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
  19. +obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
  20. obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
  21. obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
  22. obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
  23. --- /dev/null
  24. +++ b/arch/mips/pci/pci-mt7620.c
  25. @@ -0,0 +1,396 @@
  26. +/*
  27. + * Ralink MT7620A SoC PCI support
  28. + *
  29. + * Copyright (C) 2007-2013 Bruce Chang
  30. + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  31. + *
  32. + * This program is free software; you can redistribute it and/or modify it
  33. + * under the terms of the GNU General Public License version 2 as published
  34. + * by the Free Software Foundation.
  35. + */
  36. +
  37. +#include <linux/types.h>
  38. +#include <linux/pci.h>
  39. +#include <linux/io.h>
  40. +#include <linux/init.h>
  41. +#include <linux/delay.h>
  42. +#include <linux/interrupt.h>
  43. +#include <linux/module.h>
  44. +#include <linux/of.h>
  45. +#include <linux/of_irq.h>
  46. +#include <linux/of_pci.h>
  47. +#include <linux/reset.h>
  48. +#include <linux/platform_device.h>
  49. +
  50. +#include <asm/mach-ralink/ralink_regs.h>
  51. +#include <asm/mach-ralink/mt7620.h>
  52. +
  53. +#define RALINK_PCI_MM_MAP_BASE 0x20000000
  54. +#define RALINK_PCI_IO_MAP_BASE 0x10160000
  55. +
  56. +#define RALINK_INT_PCIE0 4
  57. +#define RALINK_SYSCFG1 0x14
  58. +#define RALINK_CLKCFG1 0x30
  59. +#define RALINK_GPIOMODE 0x60
  60. +#define RALINK_PCIE_CLK_GEN 0x7c
  61. +#define RALINK_PCIE_CLK_GEN1 0x80
  62. +#define PCIEPHY0_CFG 0x90
  63. +#define PPLL_CFG1 0x9c
  64. +#define PPLL_DRV 0xa0
  65. +#define PDRV_SW_SET (1<<31)
  66. +#define LC_CKDRVPD_ (1<<19)
  67. +
  68. +#define RALINK_PCI_CONFIG_ADDR 0x20
  69. +#define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
  70. +#define MEMORY_BASE 0x0
  71. +#define RALINK_PCIE0_RST (1<<26)
  72. +#define RALINK_PCI_BASE 0xB0140000
  73. +#define RALINK_PCI_MEMBASE 0x28
  74. +#define RALINK_PCI_IOBASE 0x2C
  75. +
  76. +#define RT6855_PCIE0_OFFSET 0x2000
  77. +
  78. +#define RALINK_PCI_PCICFG_ADDR 0x00
  79. +#define RALINK_PCI0_BAR0SETUP_ADDR 0x10
  80. +#define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
  81. +#define RALINK_PCI0_ID 0x30
  82. +#define RALINK_PCI0_CLASS 0x34
  83. +#define RALINK_PCI0_SUBID 0x38
  84. +#define RALINK_PCI0_STATUS 0x50
  85. +#define RALINK_PCI_PCIMSK_ADDR 0x0C
  86. +
  87. +#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
  88. +#define RALINK_PCIE0_CLK_EN (1 << 26)
  89. +
  90. +#define BUSY 0x80000000
  91. +#define WAITRETRY_MAX 10
  92. +#define WRITE_MODE (1UL << 23)
  93. +#define DATA_SHIFT 0
  94. +#define ADDR_SHIFT 8
  95. +
  96. +static void __iomem *bridge_base;
  97. +static void __iomem *pcie_base;
  98. +
  99. +static struct reset_control *rstpcie0;
  100. +
  101. +static inline void bridge_w32(u32 val, unsigned reg)
  102. +{
  103. + iowrite32(val, bridge_base + reg);
  104. +}
  105. +
  106. +static inline u32 bridge_r32(unsigned reg)
  107. +{
  108. + return ioread32(bridge_base + reg);
  109. +}
  110. +
  111. +static inline void pcie_w32(u32 val, unsigned reg)
  112. +{
  113. + iowrite32(val, pcie_base + reg);
  114. +}
  115. +
  116. +static inline u32 pcie_r32(unsigned reg)
  117. +{
  118. + return ioread32(pcie_base + reg);
  119. +}
  120. +
  121. +static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
  122. +{
  123. + u32 val = pcie_r32(reg);
  124. +
  125. + val &= ~clr;
  126. + val |= set;
  127. + pcie_w32(val, reg);
  128. +}
  129. +
  130. +static int wait_pciephy_busy(void)
  131. +{
  132. + unsigned long reg_value = 0x0, retry = 0;
  133. +
  134. + while (1) {
  135. + reg_value = pcie_r32(PCIEPHY0_CFG);
  136. +
  137. + if (reg_value & BUSY)
  138. + mdelay(100);
  139. + else
  140. + break;
  141. + if (retry++ > WAITRETRY_MAX){
  142. + printk("PCIE-PHY retry failed.\n");
  143. + return -1;
  144. + }
  145. + }
  146. + return 0;
  147. +}
  148. +
  149. +static void pcie_phy(unsigned long addr, unsigned long val)
  150. +{
  151. + wait_pciephy_busy();
  152. + pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
  153. + mdelay(1);
  154. + wait_pciephy_busy();
  155. +}
  156. +
  157. +static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
  158. +{
  159. + unsigned int slot = PCI_SLOT(devfn);
  160. + u8 func = PCI_FUNC(devfn);
  161. + u32 address;
  162. + u32 data;
  163. + u32 num = 0;
  164. +
  165. + if (bus)
  166. + num = bus->number;
  167. +
  168. + address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
  169. + bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
  170. + data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
  171. +
  172. + switch (size) {
  173. + case 1:
  174. + *val = (data >> ((where & 3) << 3)) & 0xff;
  175. + break;
  176. + case 2:
  177. + *val = (data >> ((where & 3) << 3)) & 0xffff;
  178. + break;
  179. + case 4:
  180. + *val = data;
  181. + break;
  182. + }
  183. +
  184. + return PCIBIOS_SUCCESSFUL;
  185. +}
  186. +
  187. +static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
  188. +{
  189. + unsigned int slot = PCI_SLOT(devfn);
  190. + u8 func = PCI_FUNC(devfn);
  191. + u32 address;
  192. + u32 data;
  193. + u32 num = 0;
  194. +
  195. + if (bus)
  196. + num = bus->number;
  197. +
  198. + address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
  199. + bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
  200. + data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
  201. +
  202. + switch (size) {
  203. + case 1:
  204. + data = (data & ~(0xff << ((where & 3) << 3))) |
  205. + (val << ((where & 3) << 3));
  206. + break;
  207. + case 2:
  208. + data = (data & ~(0xffff << ((where & 3) << 3))) |
  209. + (val << ((where & 3) << 3));
  210. + break;
  211. + case 4:
  212. + data = val;
  213. + break;
  214. + }
  215. +
  216. + bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
  217. +
  218. + return PCIBIOS_SUCCESSFUL;
  219. +}
  220. +
  221. +struct pci_ops mt7620_pci_ops= {
  222. + .read = pci_config_read,
  223. + .write = pci_config_write,
  224. +};
  225. +
  226. +static struct resource mt7620_res_pci_mem1;
  227. +static struct resource mt7620_res_pci_io1;
  228. +struct pci_controller mt7620_controller = {
  229. + .pci_ops = &mt7620_pci_ops,
  230. + .mem_resource = &mt7620_res_pci_mem1,
  231. + .mem_offset = 0x00000000UL,
  232. + .io_resource = &mt7620_res_pci_io1,
  233. + .io_offset = 0x00000000UL,
  234. + .io_map_base = 0xa0000000,
  235. +};
  236. +
  237. +static int mt7620_pci_hw_init(struct platform_device *pdev) {
  238. + /* PCIE: bypass PCIe DLL */
  239. + pcie_phy(0x0, 0x80);
  240. + pcie_phy(0x1, 0x04);
  241. +
  242. + /* PCIE: Elastic buffer control */
  243. + pcie_phy(0x68, 0xB4);
  244. +
  245. + pcie_m32(0, BIT(1), RALINK_PCI_PCICFG_ADDR);
  246. +
  247. + reset_control_assert(rstpcie0);
  248. +
  249. + rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
  250. + rt_sysc_m32(BIT(19), BIT(31), PPLL_DRV);
  251. +
  252. + reset_control_deassert(rstpcie0);
  253. + rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
  254. +
  255. + mdelay(100);
  256. +
  257. + if (!(rt_sysc_r32(PPLL_CFG1) & BIT(23))) {
  258. + dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
  259. + reset_control_assert(rstpcie0);
  260. + rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
  261. + return -1;
  262. + }
  263. + rt_sysc_m32(BIT(18) | BIT(17), BIT(19) | BIT(31), PPLL_DRV);
  264. +
  265. + return 0;
  266. +}
  267. +
  268. +static int mt7628_pci_hw_init(struct platform_device *pdev) {
  269. + u32 val = 0;
  270. +
  271. + rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
  272. + reset_control_deassert(rstpcie0);
  273. + rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
  274. + mdelay(100);
  275. +
  276. + pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
  277. +
  278. + pci_config_read(NULL, 0, 0x70c, 4, &val);
  279. + val &= ~(0xff) << 8;
  280. + val |= 0x50 << 8;
  281. + pci_config_write(NULL, 0, 0x70c, 4, val);
  282. +
  283. + pci_config_read(NULL, 0, 0x70c, 4, &val);
  284. + dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
  285. +
  286. + return 0;
  287. +}
  288. +
  289. +static int mt7620_pci_probe(struct platform_device *pdev)
  290. +{
  291. + struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  292. + struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  293. + u32 val = 0;
  294. +
  295. + rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
  296. + if (IS_ERR(rstpcie0))
  297. + return PTR_ERR(rstpcie0);
  298. +
  299. + bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
  300. + if (!bridge_base)
  301. + return -ENOMEM;
  302. +
  303. + pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
  304. + if (!pcie_base)
  305. + return -ENOMEM;
  306. +
  307. + iomem_resource.start = 0;
  308. + iomem_resource.end = ~0;
  309. + ioport_resource.start = 0;
  310. + ioport_resource.end = ~0;
  311. +
  312. + /* bring up the pci core */
  313. + switch (ralink_soc) {
  314. + case MT762X_SOC_MT7620A:
  315. + if (mt7620_pci_hw_init(pdev))
  316. + return -1;
  317. + break;
  318. +
  319. + case MT762X_SOC_MT7628AN:
  320. + if (mt7628_pci_hw_init(pdev))
  321. + return -1;
  322. + break;
  323. +
  324. + default:
  325. + dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
  326. + return -1;
  327. + }
  328. + mdelay(50);
  329. +
  330. + /* enable write access */
  331. + pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
  332. + mdelay(100);
  333. +
  334. + /* check if there is a card present */
  335. + if ((pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
  336. + reset_control_assert(rstpcie0);
  337. + rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
  338. + if (ralink_soc == MT762X_SOC_MT7620A)
  339. + rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
  340. + dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
  341. + return -1;
  342. + }
  343. +
  344. + /* setup ranges */
  345. + bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
  346. + bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
  347. +
  348. + pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
  349. + pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
  350. + pcie_w32(0x06040001, RALINK_PCI0_CLASS);
  351. +
  352. + /* enable interrupts */
  353. + pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
  354. +
  355. + /* voodoo from the SDK driver */
  356. + pci_config_read(NULL, 0, 4, 4, &val);
  357. + pci_config_write(NULL, 0, 4, 4, val | 0x7);
  358. +
  359. + pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
  360. + register_pci_controller(&mt7620_controller);
  361. +
  362. + return 0;
  363. +}
  364. +
  365. +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  366. +{
  367. + u16 cmd;
  368. + u32 val;
  369. + int irq = 0;
  370. +
  371. + if ((dev->bus->number == 0) && (slot == 0)) {
  372. + pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
  373. + pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
  374. + pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
  375. + } else if ((dev->bus->number == 1) && (slot == 0x0)) {
  376. + irq = RALINK_INT_PCIE0;
  377. + } else {
  378. + dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
  379. + return 0;
  380. + }
  381. + dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", dev->bus->number, slot, irq);
  382. +
  383. + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
  384. + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
  385. + pci_read_config_word(dev, PCI_COMMAND, &cmd);
  386. +
  387. + // FIXME
  388. + cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
  389. + pci_write_config_word(dev, PCI_COMMAND, cmd);
  390. + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
  391. + //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
  392. +
  393. + return irq;
  394. +}
  395. +
  396. +int pcibios_plat_dev_init(struct pci_dev *dev)
  397. +{
  398. + return 0;
  399. +}
  400. +
  401. +static const struct of_device_id mt7620_pci_ids[] = {
  402. + { .compatible = "mediatek,mt7620-pci" },
  403. + {},
  404. +};
  405. +MODULE_DEVICE_TABLE(of, mt7620_pci_ids);
  406. +
  407. +static struct platform_driver mt7620_pci_driver = {
  408. + .probe = mt7620_pci_probe,
  409. + .driver = {
  410. + .name = "mt7620-pci",
  411. + .owner = THIS_MODULE,
  412. + .of_match_table = of_match_ptr(mt7620_pci_ids),
  413. + },
  414. +};
  415. +
  416. +static int __init mt7620_pci_init(void)
  417. +{
  418. + return platform_driver_register(&mt7620_pci_driver);
  419. +}
  420. +
  421. +arch_initcall(mt7620_pci_init);
  422. --- a/arch/mips/ralink/Kconfig
  423. +++ b/arch/mips/ralink/Kconfig
  424. @@ -43,6 +43,7 @@ choice
  425. config SOC_MT7620
  426. bool "MT7620/8"
  427. + select HW_HAS_PCI
  428. config SOC_MT7621
  429. bool "MT7621"