0019-arch-mips-ralink-add-mt7621-cpu-feature-overrides.patch 2.3 KB

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  1. From 43372c2be9fcf68bc40c322039c75893ce4e982c Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Mon, 7 Dec 2015 17:20:47 +0100
  4. Subject: [PATCH 19/53] arch: mips: ralink: add mt7621 cpu-feature-overrides
  5. Signed-off-by: John Crispin <blogic@openwrt.org>
  6. ---
  7. .../asm/mach-ralink/mt7621/cpu-feature-overrides.h | 65 ++++++++++++++++++++
  8. 1 file changed, 65 insertions(+)
  9. create mode 100644 arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h
  10. --- /dev/null
  11. +++ b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h
  12. @@ -0,0 +1,65 @@
  13. +/*
  14. + * Ralink MT7621 specific CPU feature overrides
  15. + *
  16. + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  17. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  18. + * Copyright (C) 2015 Felix Fietkau <nbd@nbd.name>
  19. + *
  20. + * This file was derived from: include/asm-mips/cpu-features.h
  21. + * Copyright (C) 2003, 2004 Ralf Baechle
  22. + * Copyright (C) 2004 Maciej W. Rozycki
  23. + *
  24. + * This program is free software; you can redistribute it and/or modify it
  25. + * under the terms of the GNU General Public License version 2 as published
  26. + * by the Free Software Foundation.
  27. + *
  28. + */
  29. +#ifndef _MT7621_CPU_FEATURE_OVERRIDES_H
  30. +#define _MT7621_CPU_FEATURE_OVERRIDES_H
  31. +
  32. +#define cpu_has_tlb 1
  33. +#define cpu_has_4kex 1
  34. +#define cpu_has_3k_cache 0
  35. +#define cpu_has_4k_cache 1
  36. +#define cpu_has_tx39_cache 0
  37. +#define cpu_has_sb1_cache 0
  38. +#define cpu_has_fpu 0
  39. +#define cpu_has_32fpr 0
  40. +#define cpu_has_counter 1
  41. +#define cpu_has_watch 1
  42. +#define cpu_has_divec 1
  43. +
  44. +#define cpu_has_prefetch 1
  45. +#define cpu_has_ejtag 1
  46. +#define cpu_has_llsc 1
  47. +
  48. +#define cpu_has_mips16 1
  49. +#define cpu_has_mdmx 0
  50. +#define cpu_has_mips3d 0
  51. +#define cpu_has_smartmips 0
  52. +
  53. +#define cpu_has_mips32r1 1
  54. +#define cpu_has_mips32r2 1
  55. +#define cpu_has_mips64r1 0
  56. +#define cpu_has_mips64r2 0
  57. +
  58. +#define cpu_has_dsp 1
  59. +#define cpu_has_dsp2 0
  60. +#define cpu_has_mipsmt 1
  61. +
  62. +#define cpu_has_64bits 0
  63. +#define cpu_has_64bit_zero_reg 0
  64. +#define cpu_has_64bit_gp_regs 0
  65. +#define cpu_has_64bit_addresses 0
  66. +
  67. +#define cpu_dcache_line_size() 32
  68. +#define cpu_icache_line_size() 32
  69. +
  70. +#define cpu_has_dc_aliases 0
  71. +#define cpu_has_vtag_icache 0
  72. +
  73. +#define cpu_has_rixi 0
  74. +#define cpu_has_tlbinv 0
  75. +#define cpu_has_userlocal 1
  76. +
  77. +#endif /* _MT7621_CPU_FEATURE_OVERRIDES_H */