0029-phy-usb-add-ralink-phy.patch 8.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293
  1. From b00b5eafa7e8d059bd0ce844e66f648916953270 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Sun, 3 Jan 2016 19:11:22 +0100
  4. Subject: [PATCH 2/3] phy: ralink-usb: add driver for Mediatek/Ralink
  5. Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
  6. The driver is trivial and only sets up power and host mode.
  7. Signed-off-by: John Crispin <blogic@openwrt.org>
  8. ---
  9. .../devicetree/bindings/phy/ralink-usb-phy.txt | 17 ++
  10. drivers/phy/Kconfig | 8 +
  11. drivers/phy/Makefile | 1 +
  12. drivers/phy/phy-ralink-usb.c | 171 ++++++++++++++++++++
  13. 4 files changed, 197 insertions(+)
  14. create mode 100644 Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
  15. create mode 100644 drivers/phy/phy-ralink-usb.c
  16. --- /dev/null
  17. +++ b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
  18. @@ -0,0 +1,17 @@
  19. +Mediatek/Ralink USB PHY
  20. +
  21. +Required properties:
  22. + - compatible: ralink,rt3352-usbphy or mediatek,mt7620-usbphy
  23. + - #phy-cells: should be 0
  24. + - resets: the two reset controllers for host and device
  25. + - reset-names: the names of the 2 reset controllers
  26. +
  27. +Example:
  28. +
  29. +usbphy: phy {
  30. + compatible = "mediatek,mt7620-usbphy";
  31. + #phy-cells = <0>;
  32. +
  33. + resets = <&rstctrl 22 &rstctrl 25>;
  34. + reset-names = "host", "device";
  35. +};
  36. --- a/drivers/phy/Kconfig
  37. +++ b/drivers/phy/Kconfig
  38. @@ -341,6 +341,14 @@ config PHY_XGENE
  39. help
  40. This option enables support for APM X-Gene SoC multi-purpose PHY.
  41. +config PHY_RALINK_USB
  42. + tristate "Ralink USB PHY driver"
  43. + select GENERIC_PHY
  44. + depends on RALINK
  45. + help
  46. + This option enables support for the Ralink USB PHY found inside
  47. + RT3352 and MT7620.
  48. +
  49. config PHY_STIH407_USB
  50. tristate "STMicroelectronics USB2 picoPHY driver for STiH407 family"
  51. depends on RESET_CONTROLLER
  52. --- a/drivers/phy/Makefile
  53. +++ b/drivers/phy/Makefile
  54. @@ -48,3 +48,4 @@ obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1
  55. obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
  56. obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
  57. obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
  58. +obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
  59. --- /dev/null
  60. +++ b/drivers/phy/phy-ralink-usb.c
  61. @@ -0,0 +1,228 @@
  62. +/*
  63. + * Allwinner ralink USB phy driver
  64. + *
  65. + * Copyright (C) 2016 John Crispin <blogic@openwrt.org>
  66. + *
  67. + * Based on code from
  68. + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  69. + *
  70. + * This program is free software; you can redistribute it and/or modify
  71. + * it under the terms of the GNU General Public License as published by
  72. + * the Free Software Foundation; either version 2 of the License, or
  73. + * (at your option) any later version.
  74. + *
  75. + * This program is distributed in the hope that it will be useful,
  76. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  77. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  78. + * GNU General Public License for more details.
  79. + */
  80. +
  81. +#include <linux/delay.h>
  82. +#include <linux/err.h>
  83. +#include <linux/io.h>
  84. +#include <linux/kernel.h>
  85. +#include <linux/module.h>
  86. +#include <linux/mutex.h>
  87. +#include <linux/phy/phy.h>
  88. +#include <linux/platform_device.h>
  89. +#include <linux/reset.h>
  90. +#include <linux/of_platform.h>
  91. +
  92. +#include <asm/mach-ralink/ralink_regs.h>
  93. +
  94. +#define RT_SYSC_REG_SYSCFG1 0x014
  95. +#define RT_SYSC_REG_CLKCFG1 0x030
  96. +#define RT_SYSC_REG_USB_PHY_CFG 0x05c
  97. +
  98. +#define OFS_U2_PHY_AC0 0x00
  99. +#define OFS_U2_PHY_AC1 0x04
  100. +#define OFS_U2_PHY_AC2 0x08
  101. +#define OFS_U2_PHY_ACR0 0x10
  102. +#define OFS_U2_PHY_ACR1 0x14
  103. +#define OFS_U2_PHY_ACR2 0x18
  104. +#define OFS_U2_PHY_ACR3 0x1C
  105. +#define OFS_U2_PHY_ACR4 0x20
  106. +#define OFS_U2_PHY_AMON0 0x24
  107. +#define OFS_U2_PHY_DCR0 0x60
  108. +#define OFS_U2_PHY_DCR1 0x64
  109. +#define OFS_U2_PHY_DTM0 0x68
  110. +#define OFS_U2_PHY_DTM1 0x6C
  111. +
  112. +#define RT_RSTCTRL_UDEV BIT(25)
  113. +#define RT_RSTCTRL_UHST BIT(22)
  114. +#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
  115. +
  116. +#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
  117. +#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
  118. +#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
  119. +#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
  120. +
  121. +#define USB_PHY_UTMI_8B60M BIT(1)
  122. +#define UDEV_WAKEUP BIT(0)
  123. +
  124. +struct ralink_usb_phy {
  125. + struct reset_control *rstdev;
  126. + struct reset_control *rsthost;
  127. + u32 clk;
  128. + struct phy *phy;
  129. + void __iomem *base;
  130. +};
  131. +
  132. +static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg)
  133. +{
  134. + iowrite32(val, phy->base + reg);
  135. +}
  136. +
  137. +static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg)
  138. +{
  139. + return ioread32(phy->base + reg);
  140. +}
  141. +
  142. +static void
  143. +u2_phy_init(struct ralink_usb_phy *phy)
  144. +{
  145. + u2_phy_r32(phy, OFS_U2_PHY_AC2);
  146. + u2_phy_r32(phy, OFS_U2_PHY_ACR0);
  147. + u2_phy_r32(phy, OFS_U2_PHY_DCR0);
  148. +
  149. + u2_phy_w32(phy, 0x00ffff02, OFS_U2_PHY_DCR0);
  150. + u2_phy_r32(phy, OFS_U2_PHY_DCR0);
  151. + u2_phy_w32(phy, 0x00555502, OFS_U2_PHY_DCR0);
  152. + u2_phy_r32(phy, OFS_U2_PHY_DCR0);
  153. + u2_phy_w32(phy, 0x00aaaa02, OFS_U2_PHY_DCR0);
  154. + u2_phy_r32(phy, OFS_U2_PHY_DCR0);
  155. + u2_phy_w32(phy, 0x00000402, OFS_U2_PHY_DCR0);
  156. + u2_phy_r32(phy, OFS_U2_PHY_DCR0);
  157. + u2_phy_w32(phy, 0x0048086a, OFS_U2_PHY_AC0);
  158. + u2_phy_w32(phy, 0x4400001c, OFS_U2_PHY_AC1);
  159. + u2_phy_w32(phy, 0xc0200000, OFS_U2_PHY_ACR3);
  160. + u2_phy_w32(phy, 0x02000000, OFS_U2_PHY_DTM0);
  161. +}
  162. +
  163. +static int ralink_usb_phy_power_on(struct phy *_phy)
  164. +{
  165. + struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
  166. + u32 t;
  167. +
  168. + /* enable the phy */
  169. + rt_sysc_m32(0, phy->clk, RT_SYSC_REG_CLKCFG1);
  170. +
  171. + /* setup host mode */
  172. + rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
  173. +
  174. + /* deassert the reset lines */
  175. + reset_control_deassert(phy->rsthost);
  176. + reset_control_deassert(phy->rstdev);
  177. +
  178. + /*
  179. + * The SDK kernel had a delay of 100ms. however on device
  180. + * testing showed that 10ms is enough
  181. + */
  182. + mdelay(10);
  183. +
  184. + if (!IS_ERR(phy->base))
  185. + u2_phy_init(phy);
  186. +
  187. + /* print some status info */
  188. + t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
  189. + dev_info(&phy->phy->dev, "remote usb device wakeup %s\n",
  190. + (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
  191. + if (t & USB_PHY_UTMI_8B60M)
  192. + dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n");
  193. + else
  194. + dev_info(&phy->phy->dev, "UTMI 16bit 30MHz\n");
  195. +
  196. + return 0;
  197. +}
  198. +
  199. +static int ralink_usb_phy_power_off(struct phy *_phy)
  200. +{
  201. + struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
  202. +
  203. + /* assert the reset lines */
  204. + reset_control_assert(phy->rstdev);
  205. + reset_control_assert(phy->rsthost);
  206. +
  207. + /* disable the phy */
  208. + rt_sysc_m32(phy->clk, 0, RT_SYSC_REG_CLKCFG1);
  209. +
  210. + return 0;
  211. +}
  212. +
  213. +static struct phy_ops ralink_usb_phy_ops = {
  214. + .power_on = ralink_usb_phy_power_on,
  215. + .power_off = ralink_usb_phy_power_off,
  216. + .owner = THIS_MODULE,
  217. +};
  218. +
  219. +static const struct of_device_id ralink_usb_phy_of_match[] = {
  220. + {
  221. + .compatible = "ralink,rt3352-usbphy",
  222. + .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN |
  223. + RT_CLKCFG1_UPHY0_CLK_EN)
  224. + },
  225. + {
  226. + .compatible = "mediatek,mt7620-usbphy",
  227. + .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN |
  228. + MT7620_CLKCFG1_UPHY0_CLK_EN) },
  229. + { },
  230. +};
  231. +MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
  232. +
  233. +static int ralink_usb_phy_probe(struct platform_device *pdev)
  234. +{
  235. + struct resource *res;
  236. + struct device *dev = &pdev->dev;
  237. + struct phy_provider *phy_provider;
  238. + const struct of_device_id *match;
  239. + struct ralink_usb_phy *phy;
  240. +
  241. + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
  242. + if (!phy)
  243. + return -ENOMEM;
  244. +
  245. + match = of_match_device(ralink_usb_phy_of_match, &pdev->dev);
  246. + if (!match)
  247. + return -ENODEV;
  248. +
  249. + phy->clk = (int) match->data;
  250. +
  251. + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  252. + phy->base = devm_ioremap_resource(&pdev->dev, res);
  253. +
  254. + phy->rsthost = devm_reset_control_get(&pdev->dev, "host");
  255. + if (IS_ERR(phy->rsthost)) {
  256. + dev_err(dev, "host reset is missing\n");
  257. + return PTR_ERR(phy->rsthost);
  258. + }
  259. +
  260. + phy->rstdev = devm_reset_control_get(&pdev->dev, "device");
  261. + if (IS_ERR(phy->rstdev)) {
  262. + dev_err(dev, "device reset is missing\n");
  263. + return PTR_ERR(phy->rstdev);
  264. + }
  265. +
  266. + phy->phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops);
  267. + if (IS_ERR(phy->phy)) {
  268. + dev_err(dev, "failed to create PHY\n");
  269. + return PTR_ERR(phy->phy);
  270. + }
  271. + phy_set_drvdata(phy->phy, phy);
  272. +
  273. + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  274. +
  275. + return PTR_ERR_OR_ZERO(phy_provider);
  276. +}
  277. +
  278. +static struct platform_driver ralink_usb_phy_driver = {
  279. + .probe = ralink_usb_phy_probe,
  280. + .driver = {
  281. + .of_match_table = ralink_usb_phy_of_match,
  282. + .name = "ralink-usb-phy",
  283. + }
  284. +};
  285. +module_platform_driver(ralink_usb_phy_driver);
  286. +
  287. +MODULE_DESCRIPTION("Ralink USB phy driver");
  288. +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
  289. +MODULE_LICENSE("GPL v2");