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0043-spi-add-mt7621-support.patch 12 KB

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  1. From 87a5fcd57c577cd94b5b080deb98885077c13a42 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Sun, 27 Jul 2014 09:49:07 +0100
  4. Subject: [PATCH 43/53] spi: add mt7621 support
  5. Signed-off-by: John Crispin <blogic@openwrt.org>
  6. ---
  7. drivers/spi/Kconfig | 6 +
  8. drivers/spi/Makefile | 1 +
  9. drivers/spi/spi-mt7621.c | 480 ++++++++++++++++++++++++++++++++++++++++++++++
  10. 3 files changed, 487 insertions(+)
  11. create mode 100644 drivers/spi/spi-mt7621.c
  12. --- a/drivers/spi/Kconfig
  13. +++ b/drivers/spi/Kconfig
  14. @@ -483,6 +483,12 @@ config SPI_RT2880
  15. help
  16. This selects a driver for the Ralink RT288x/RT305x SPI Controller.
  17. +config SPI_MT7621
  18. + tristate "MediaTek MT7621 SPI Controller"
  19. + depends on RALINK
  20. + help
  21. + This selects a driver for the MediaTek MT7621 SPI Controller.
  22. +
  23. config SPI_S3C24XX
  24. tristate "Samsung S3C24XX series SPI"
  25. depends on ARCH_S3C24XX
  26. --- a/drivers/spi/Makefile
  27. +++ b/drivers/spi/Makefile
  28. @@ -51,6 +51,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mp
  29. obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
  30. obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
  31. obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
  32. +obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
  33. obj-$(CONFIG_SPI_MXS) += spi-mxs.o
  34. obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
  35. obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
  36. --- /dev/null
  37. +++ b/drivers/spi/spi-mt7621.c
  38. @@ -0,0 +1,483 @@
  39. +/*
  40. + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
  41. + *
  42. + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  43. + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  44. + * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
  45. + *
  46. + * Some parts are based on spi-orion.c:
  47. + * Author: Shadi Ammouri <shadi@marvell.com>
  48. + * Copyright (C) 2007-2008 Marvell Ltd.
  49. + *
  50. + * This program is free software; you can redistribute it and/or modify
  51. + * it under the terms of the GNU General Public License version 2 as
  52. + * published by the Free Software Foundation.
  53. + */
  54. +
  55. +#include <linux/init.h>
  56. +#include <linux/module.h>
  57. +#include <linux/clk.h>
  58. +#include <linux/err.h>
  59. +#include <linux/delay.h>
  60. +#include <linux/io.h>
  61. +#include <linux/reset.h>
  62. +#include <linux/spi/spi.h>
  63. +#include <linux/of_device.h>
  64. +#include <linux/platform_device.h>
  65. +#include <linux/swab.h>
  66. +
  67. +#include <ralink_regs.h>
  68. +
  69. +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
  70. +
  71. +#define DRIVER_NAME "spi-mt7621"
  72. +/* in usec */
  73. +#define RALINK_SPI_WAIT_MAX_LOOP 2000
  74. +
  75. +/* SPISTAT register bit field */
  76. +#define SPISTAT_BUSY BIT(0)
  77. +
  78. +#define MT7621_SPI_TRANS 0x00
  79. +#define SPITRANS_BUSY BIT(16)
  80. +
  81. +#define MT7621_SPI_OPCODE 0x04
  82. +#define MT7621_SPI_DATA0 0x08
  83. +#define MT7621_SPI_DATA4 0x18
  84. +#define SPI_CTL_TX_RX_CNT_MASK 0xff
  85. +#define SPI_CTL_START BIT(8)
  86. +
  87. +#define MT7621_SPI_POLAR 0x38
  88. +#define MT7621_SPI_MASTER 0x28
  89. +#define MT7621_SPI_MOREBUF 0x2c
  90. +#define MT7621_SPI_SPACE 0x3c
  91. +
  92. +#define MT7621_CPHA BIT(5)
  93. +#define MT7621_CPOL BIT(4)
  94. +#define MT7621_LSB_FIRST BIT(3)
  95. +
  96. +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
  97. +
  98. +struct mt7621_spi;
  99. +
  100. +struct mt7621_spi {
  101. + struct spi_master *master;
  102. + void __iomem *base;
  103. + unsigned int sys_freq;
  104. + unsigned int speed;
  105. + struct clk *clk;
  106. + spinlock_t lock;
  107. +
  108. + struct mt7621_spi_ops *ops;
  109. +};
  110. +
  111. +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
  112. +{
  113. + return spi_master_get_devdata(spi->master);
  114. +}
  115. +
  116. +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
  117. +{
  118. + return ioread32(rs->base + reg);
  119. +}
  120. +
  121. +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
  122. +{
  123. + iowrite32(val, rs->base + reg);
  124. +}
  125. +
  126. +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
  127. +{
  128. + u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
  129. +
  130. + master |= 7 << 29;
  131. + master |= 1 << 2;
  132. + if (duplex)
  133. + master |= 1 << 10;
  134. + else
  135. + master &= ~(1 << 10);
  136. +
  137. + mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
  138. +}
  139. +
  140. +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
  141. +{
  142. + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  143. + int cs = spi->chip_select;
  144. + u32 polar = 0;
  145. +
  146. + mt7621_spi_reset(rs, cs);
  147. + if (enable)
  148. + polar = BIT(cs);
  149. + mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
  150. +}
  151. +
  152. +static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
  153. +{
  154. + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  155. + u32 rate;
  156. + u32 reg;
  157. +
  158. + dev_dbg(&spi->dev, "speed:%u\n", speed);
  159. +
  160. + rate = DIV_ROUND_UP(rs->sys_freq, speed);
  161. + dev_dbg(&spi->dev, "rate-1:%u\n", rate);
  162. +
  163. + if (rate > 4097)
  164. + return -EINVAL;
  165. +
  166. + if (rate < 2)
  167. + rate = 2;
  168. +
  169. + reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
  170. + reg &= ~(0xfff << 16);
  171. + reg |= (rate - 2) << 16;
  172. + rs->speed = speed;
  173. +
  174. + reg &= ~MT7621_LSB_FIRST;
  175. + if (spi->mode & SPI_LSB_FIRST)
  176. + reg |= MT7621_LSB_FIRST;
  177. +
  178. + reg &= ~(MT7621_CPHA | MT7621_CPOL);
  179. + switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
  180. + case SPI_MODE_0:
  181. + break;
  182. + case SPI_MODE_1:
  183. + reg |= MT7621_CPHA;
  184. + break;
  185. + case SPI_MODE_2:
  186. + reg |= MT7621_CPOL;
  187. + break;
  188. + case SPI_MODE_3:
  189. + reg |= MT7621_CPOL | MT7621_CPHA;
  190. + break;
  191. + }
  192. + mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
  193. +
  194. + return 0;
  195. +}
  196. +
  197. +static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
  198. +{
  199. + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  200. + int i;
  201. +
  202. + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
  203. + u32 status;
  204. +
  205. + status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
  206. + if ((status & SPITRANS_BUSY) == 0) {
  207. + return 0;
  208. + }
  209. + cpu_relax();
  210. + udelay(1);
  211. + }
  212. +
  213. + return -ETIMEDOUT;
  214. +}
  215. +
  216. +static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
  217. + struct spi_message *m)
  218. +{
  219. + struct mt7621_spi *rs = spi_master_get_devdata(master);
  220. + struct spi_device *spi = m->spi;
  221. + unsigned int speed = spi->max_speed_hz;
  222. + struct spi_transfer *t = NULL;
  223. + int status = 0;
  224. + int i, len = 0;
  225. + int rx_len = 0;
  226. + u32 data[9] = { 0 };
  227. + u32 val;
  228. +
  229. + mt7621_spi_wait_till_ready(spi);
  230. +
  231. + list_for_each_entry(t, &m->transfers, transfer_list) {
  232. + const u8 *buf = t->tx_buf;
  233. +
  234. + if (t->rx_buf)
  235. + rx_len += t->len;
  236. +
  237. + if (!buf)
  238. + continue;
  239. +
  240. + if (t->speed_hz < speed)
  241. + speed = t->speed_hz;
  242. +
  243. + if (WARN_ON(len + t->len > 36)) {
  244. + status = -EIO;
  245. + goto msg_done;
  246. + }
  247. +
  248. + for (i = 0; i < t->len; i++, len++)
  249. + data[len / 4] |= buf[i] << (8 * (len & 3));
  250. + }
  251. +
  252. + if (WARN_ON(rx_len > 32)) {
  253. + status = -EIO;
  254. + goto msg_done;
  255. + }
  256. +
  257. + if (mt7621_spi_prepare(spi, speed)) {
  258. + status = -EIO;
  259. + goto msg_done;
  260. + }
  261. + data[0] = swab32(data[0]);
  262. + if (len < 4)
  263. + data[0] >>= (4 - len) * 8;
  264. +
  265. + for (i = 0; i < len; i += 4)
  266. + mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
  267. +
  268. + val = (min_t(int, len, 4) * 8) << 24;
  269. + if (len > 4)
  270. + val |= (len - 4) * 8;
  271. + val |= (rx_len * 8) << 12;
  272. + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
  273. +
  274. + mt7621_spi_set_cs(spi, 1);
  275. +
  276. + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
  277. + val |= SPI_CTL_START;
  278. + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
  279. +
  280. + mt7621_spi_wait_till_ready(spi);
  281. +
  282. + mt7621_spi_set_cs(spi, 0);
  283. +
  284. + for (i = 0; i < rx_len; i += 4)
  285. + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
  286. +
  287. + m->actual_length = len + rx_len;
  288. +
  289. + len = 0;
  290. + list_for_each_entry(t, &m->transfers, transfer_list) {
  291. + u8 *buf = t->rx_buf;
  292. +
  293. + if (!buf)
  294. + continue;
  295. +
  296. + for (i = 0; i < t->len; i++, len++)
  297. + buf[i] = data[len / 4] >> (8 * (len & 3));
  298. + }
  299. +
  300. +msg_done:
  301. + m->status = status;
  302. + spi_finalize_current_message(master);
  303. +
  304. + return 0;
  305. +}
  306. +
  307. +static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
  308. + struct spi_message *m)
  309. +{
  310. + struct mt7621_spi *rs = spi_master_get_devdata(master);
  311. + struct spi_device *spi = m->spi;
  312. + unsigned int speed = spi->max_speed_hz;
  313. + struct spi_transfer *t = NULL;
  314. + int status = 0;
  315. + int i, len = 0;
  316. + int rx_len = 0;
  317. + u32 data[9] = { 0 };
  318. + u32 val = 0;
  319. +
  320. + mt7621_spi_wait_till_ready(spi);
  321. +
  322. + list_for_each_entry(t, &m->transfers, transfer_list) {
  323. + const u8 *buf = t->tx_buf;
  324. +
  325. + if (t->rx_buf)
  326. + rx_len += t->len;
  327. +
  328. + if (!buf)
  329. + continue;
  330. +
  331. + if (WARN_ON(len + t->len > 16)) {
  332. + status = -EIO;
  333. + goto msg_done;
  334. + }
  335. +
  336. + for (i = 0; i < t->len; i++, len++)
  337. + data[len / 4] |= buf[i] << (8 * (len & 3));
  338. + if (speed > t->speed_hz)
  339. + speed = t->speed_hz;
  340. + }
  341. +
  342. + if (WARN_ON(rx_len > 16)) {
  343. + status = -EIO;
  344. + goto msg_done;
  345. + }
  346. +
  347. + if (mt7621_spi_prepare(spi, speed)) {
  348. + status = -EIO;
  349. + goto msg_done;
  350. + }
  351. +
  352. + for (i = 0; i < len; i += 4)
  353. + mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
  354. +
  355. + val |= len * 8;
  356. + val |= (rx_len * 8) << 12;
  357. + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
  358. +
  359. + mt7621_spi_set_cs(spi, 1);
  360. +
  361. + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
  362. + val |= SPI_CTL_START;
  363. + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
  364. +
  365. + mt7621_spi_wait_till_ready(spi);
  366. +
  367. + mt7621_spi_set_cs(spi, 0);
  368. +
  369. + for (i = 0; i < rx_len; i += 4)
  370. + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
  371. +
  372. + m->actual_length = rx_len;
  373. +
  374. + len = 0;
  375. + list_for_each_entry(t, &m->transfers, transfer_list) {
  376. + u8 *buf = t->rx_buf;
  377. +
  378. + if (!buf)
  379. + continue;
  380. +
  381. + for (i = 0; i < t->len; i++, len++)
  382. + buf[i] = data[len / 4] >> (8 * (len & 3));
  383. + }
  384. +
  385. +msg_done:
  386. + m->status = status;
  387. + spi_finalize_current_message(master);
  388. +
  389. + return 0;
  390. +}
  391. +
  392. +static int mt7621_spi_transfer_one_message(struct spi_master *master,
  393. + struct spi_message *m)
  394. +{
  395. + struct spi_device *spi = m->spi;
  396. + int cs = spi->chip_select;
  397. +
  398. + if (cs)
  399. + return mt7621_spi_transfer_full_duplex(master, m);
  400. + return mt7621_spi_transfer_half_duplex(master, m);
  401. +}
  402. +
  403. +static int mt7621_spi_setup(struct spi_device *spi)
  404. +{
  405. + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  406. +
  407. + if ((spi->max_speed_hz == 0) ||
  408. + (spi->max_speed_hz > (rs->sys_freq / 2)))
  409. + spi->max_speed_hz = (rs->sys_freq / 2);
  410. +
  411. + if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
  412. + dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
  413. + spi->max_speed_hz);
  414. + return -EINVAL;
  415. + }
  416. +
  417. + return 0;
  418. +}
  419. +
  420. +static const struct of_device_id mt7621_spi_match[] = {
  421. + { .compatible = "ralink,mt7621-spi" },
  422. + {},
  423. +};
  424. +MODULE_DEVICE_TABLE(of, mt7621_spi_match);
  425. +
  426. +static int mt7621_spi_probe(struct platform_device *pdev)
  427. +{
  428. + const struct of_device_id *match;
  429. + struct spi_master *master;
  430. + struct mt7621_spi *rs;
  431. + unsigned long flags;
  432. + void __iomem *base;
  433. + struct resource *r;
  434. + int status = 0;
  435. + struct clk *clk;
  436. + struct mt7621_spi_ops *ops;
  437. +
  438. + match = of_match_device(mt7621_spi_match, &pdev->dev);
  439. + if (!match)
  440. + return -EINVAL;
  441. + ops = (struct mt7621_spi_ops *)match->data;
  442. +
  443. + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  444. + base = devm_ioremap_resource(&pdev->dev, r);
  445. + if (IS_ERR(base))
  446. + return PTR_ERR(base);
  447. +
  448. + clk = devm_clk_get(&pdev->dev, NULL);
  449. + if (IS_ERR(clk)) {
  450. + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
  451. + status);
  452. + return PTR_ERR(clk);
  453. + }
  454. +
  455. + status = clk_prepare_enable(clk);
  456. + if (status)
  457. + return status;
  458. +
  459. + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
  460. + if (master == NULL) {
  461. + dev_info(&pdev->dev, "master allocation failed\n");
  462. + return -ENOMEM;
  463. + }
  464. +
  465. + master->mode_bits = RT2880_SPI_MODE_BITS;
  466. +
  467. + master->setup = mt7621_spi_setup;
  468. + master->transfer_one_message = mt7621_spi_transfer_one_message;
  469. + master->bits_per_word_mask = SPI_BPW_MASK(8);
  470. + master->dev.of_node = pdev->dev.of_node;
  471. + master->num_chipselect = 2;
  472. +
  473. + dev_set_drvdata(&pdev->dev, master);
  474. +
  475. + rs = spi_master_get_devdata(master);
  476. + rs->base = base;
  477. + rs->clk = clk;
  478. + rs->master = master;
  479. + rs->sys_freq = clk_get_rate(rs->clk);
  480. + rs->ops = ops;
  481. + dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
  482. + spin_lock_irqsave(&rs->lock, flags);
  483. +
  484. + device_reset(&pdev->dev);
  485. +
  486. + mt7621_spi_reset(rs, 0);
  487. +
  488. + return spi_register_master(master);
  489. +}
  490. +
  491. +static int mt7621_spi_remove(struct platform_device *pdev)
  492. +{
  493. + struct spi_master *master;
  494. + struct mt7621_spi *rs;
  495. +
  496. + master = dev_get_drvdata(&pdev->dev);
  497. + rs = spi_master_get_devdata(master);
  498. +
  499. + clk_disable(rs->clk);
  500. + spi_unregister_master(master);
  501. +
  502. + return 0;
  503. +}
  504. +
  505. +MODULE_ALIAS("platform:" DRIVER_NAME);
  506. +
  507. +static struct platform_driver mt7621_spi_driver = {
  508. + .driver = {
  509. + .name = DRIVER_NAME,
  510. + .owner = THIS_MODULE,
  511. + .of_match_table = mt7621_spi_match,
  512. + },
  513. + .probe = mt7621_spi_probe,
  514. + .remove = mt7621_spi_remove,
  515. +};
  516. +
  517. +module_platform_driver(mt7621_spi_driver);
  518. +
  519. +MODULE_DESCRIPTION("MT7621 SPI driver");
  520. +MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
  521. +MODULE_LICENSE("GPL");