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0044-i2c-MIPS-adds-ralink-I2C-driver.patch 13 KB

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  1. From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Sun, 27 Jul 2014 09:52:56 +0100
  4. Subject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver
  5. Signed-off-by: John Crispin <blogic@openwrt.org>
  6. ---
  7. .../devicetree/bindings/i2c/i2c-ralink.txt | 27 ++
  8. drivers/i2c/busses/Kconfig | 4 +
  9. drivers/i2c/busses/Makefile | 1 +
  10. drivers/i2c/busses/i2c-ralink.c | 327 ++++++++++++++++++++
  11. 4 files changed, 359 insertions(+)
  12. create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
  13. create mode 100644 drivers/i2c/busses/i2c-ralink.c
  14. --- /dev/null
  15. +++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
  16. @@ -0,0 +1,27 @@
  17. +I2C for Ralink platforms
  18. +
  19. +Required properties :
  20. +- compatible : Must be "link,rt3052-i2c"
  21. +- reg: physical base address of the controller and length of memory mapped
  22. + region.
  23. +- #address-cells = <1>;
  24. +- #size-cells = <0>;
  25. +
  26. +Optional properties:
  27. +- Child nodes conforming to i2c bus binding
  28. +
  29. +Example :
  30. +
  31. +palmbus@10000000 {
  32. + i2c@900 {
  33. + compatible = "link,rt3052-i2c";
  34. + reg = <0x900 0x100>;
  35. + #address-cells = <1>;
  36. + #size-cells = <0>;
  37. +
  38. + hwmon@4b {
  39. + compatible = "national,lm92";
  40. + reg = <0x4b>;
  41. + };
  42. + };
  43. +};
  44. --- a/drivers/i2c/busses/Kconfig
  45. +++ b/drivers/i2c/busses/Kconfig
  46. @@ -806,6 +806,11 @@ config I2C_RK3X
  47. This driver can also be built as a module. If so, the module will
  48. be called i2c-rk3x.
  49. +config I2C_RALINK
  50. + tristate "Ralink I2C Controller"
  51. + depends on RALINK && !SOC_MT7621
  52. + select OF_I2C
  53. +
  54. config HAVE_S3C2410_I2C
  55. bool
  56. help
  57. --- a/drivers/i2c/busses/Makefile
  58. +++ b/drivers/i2c/busses/Makefile
  59. @@ -75,6 +75,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
  60. obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
  61. obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
  62. obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
  63. +obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
  64. obj-$(CONFIG_I2C_QUP) += i2c-qup.o
  65. obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
  66. obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
  67. --- /dev/null
  68. +++ b/drivers/i2c/busses/i2c-ralink.c
  69. @@ -0,0 +1,435 @@
  70. +/*
  71. + * drivers/i2c/busses/i2c-ralink.c
  72. + *
  73. + * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
  74. + * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
  75. + *
  76. + * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
  77. + * (C) 2014 Sittisak <sittisaks@hotmail.com>
  78. + *
  79. + * This software is licensed under the terms of the GNU General Public
  80. + * License version 2, as published by the Free Software Foundation, and
  81. + * may be copied, distributed, and modified under those terms.
  82. + *
  83. + * This program is distributed in the hope that it will be useful,
  84. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  85. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  86. + * GNU General Public License for more details.
  87. + *
  88. + */
  89. +
  90. +#include <linux/interrupt.h>
  91. +#include <linux/kernel.h>
  92. +#include <linux/module.h>
  93. +#include <linux/reset.h>
  94. +#include <linux/delay.h>
  95. +#include <linux/slab.h>
  96. +#include <linux/init.h>
  97. +#include <linux/errno.h>
  98. +#include <linux/platform_device.h>
  99. +#include <linux/of_platform.h>
  100. +#include <linux/i2c.h>
  101. +#include <linux/io.h>
  102. +#include <linux/err.h>
  103. +#include <linux/clk.h>
  104. +
  105. +#define REG_CONFIG_REG 0x00
  106. +#define REG_CLKDIV_REG 0x04
  107. +#define REG_DEVADDR_REG 0x08
  108. +#define REG_ADDR_REG 0x0C
  109. +#define REG_DATAOUT_REG 0x10
  110. +#define REG_DATAIN_REG 0x14
  111. +#define REG_STATUS_REG 0x18
  112. +#define REG_STARTXFR_REG 0x1C
  113. +#define REG_BYTECNT_REG 0x20
  114. +
  115. +/* REG_CONFIG_REG */
  116. +#define I2C_ADDRLEN_OFFSET 5
  117. +#define I2C_DEVADLEN_OFFSET 2
  118. +#define I2C_ADDRLEN_MASK 0x3
  119. +#define I2C_ADDR_DIS BIT(1)
  120. +#define I2C_DEVADDR_DIS BIT(0)
  121. +#define I2C_ADDRLEN_8 (7 << I2C_ADDRLEN_OFFSET)
  122. +#define I2C_DEVADLEN_7 (6 << I2C_DEVADLEN_OFFSET)
  123. +#define I2C_CONF_DEFAULT (I2C_ADDRLEN_8 | I2C_DEVADLEN_7)
  124. +
  125. +/* REG_CLKDIV_REG */
  126. +#define I2C_CLKDIV_MASK 0xffff
  127. +
  128. +/* REG_DEVADDR_REG */
  129. +#define I2C_DEVADDR_MASK 0x7f
  130. +
  131. +/* REG_ADDR_REG */
  132. +#define I2C_ADDR_MASK 0xff
  133. +
  134. +/* REG_STATUS_REG */
  135. +#define I2C_STARTERR BIT(4)
  136. +#define I2C_ACKERR BIT(3)
  137. +#define I2C_DATARDY BIT(2)
  138. +#define I2C_SDOEMPTY BIT(1)
  139. +#define I2C_BUSY BIT(0)
  140. +
  141. +/* REG_STARTXFR_REG */
  142. +#define NOSTOP_CMD BIT(2)
  143. +#define NODATA_CMD BIT(1)
  144. +#define READ_CMD BIT(0)
  145. +
  146. +/* REG_BYTECNT_REG */
  147. +#define BYTECNT_MAX 64
  148. +#define SET_BYTECNT(x) (x - 1)
  149. +
  150. +/* timeout waiting for I2C devices to respond (clock streching) */
  151. +#define TIMEOUT_MS 1000
  152. +#define DELAY_INTERVAL_US 100
  153. +
  154. +struct rt_i2c {
  155. + void __iomem *base;
  156. + struct clk *clk;
  157. + struct device *dev;
  158. + struct i2c_adapter adap;
  159. + u32 cur_clk;
  160. + u32 clk_div;
  161. + u32 flags;
  162. +};
  163. +
  164. +static void rt_i2c_w32(struct rt_i2c *i2c, u32 val, unsigned reg)
  165. +{
  166. + iowrite32(val, i2c->base + reg);
  167. +}
  168. +
  169. +static u32 rt_i2c_r32(struct rt_i2c *i2c, unsigned reg)
  170. +{
  171. + return ioread32(i2c->base + reg);
  172. +}
  173. +
  174. +static int poll_down_timeout(void __iomem *addr, u32 mask)
  175. +{
  176. + unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
  177. +
  178. + do {
  179. + if (!(readl_relaxed(addr) & mask))
  180. + return 0;
  181. +
  182. + usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
  183. + } while (time_before(jiffies, timeout));
  184. +
  185. + return (readl_relaxed(addr) & mask) ? -EAGAIN : 0;
  186. +}
  187. +
  188. +static int rt_i2c_wait_idle(struct rt_i2c *i2c)
  189. +{
  190. + int ret;
  191. +
  192. + ret = poll_down_timeout(i2c->base + REG_STATUS_REG, I2C_BUSY);
  193. + if (ret < 0)
  194. + dev_dbg(i2c->dev, "idle err(%d)\n", ret);
  195. +
  196. + return ret;
  197. +}
  198. +
  199. +static int poll_up_timeout(void __iomem *addr, u32 mask)
  200. +{
  201. + unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
  202. + u32 status;
  203. +
  204. + do {
  205. + status = readl_relaxed(addr);
  206. +
  207. + /* check error status */
  208. + if (status & I2C_STARTERR)
  209. + return -EAGAIN;
  210. + else if (status & I2C_ACKERR)
  211. + return -ENXIO;
  212. + else if (status & mask)
  213. + return 0;
  214. +
  215. + usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
  216. + } while (time_before(jiffies, timeout));
  217. +
  218. + return -ETIMEDOUT;
  219. +}
  220. +
  221. +static int rt_i2c_wait_rx_done(struct rt_i2c *i2c)
  222. +{
  223. + int ret;
  224. +
  225. + ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_DATARDY);
  226. + if (ret < 0)
  227. + dev_dbg(i2c->dev, "rx err(%d)\n", ret);
  228. +
  229. + return ret;
  230. +}
  231. +
  232. +static int rt_i2c_wait_tx_done(struct rt_i2c *i2c)
  233. +{
  234. + int ret;
  235. +
  236. + ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_SDOEMPTY);
  237. + if (ret < 0)
  238. + dev_dbg(i2c->dev, "tx err(%d)\n", ret);
  239. +
  240. + return ret;
  241. +}
  242. +
  243. +static void rt_i2c_reset(struct rt_i2c *i2c)
  244. +{
  245. + device_reset(i2c->adap.dev.parent);
  246. + barrier();
  247. + rt_i2c_w32(i2c, i2c->clk_div, REG_CLKDIV_REG);
  248. +}
  249. +
  250. +static void rt_i2c_dump_reg(struct rt_i2c *i2c)
  251. +{
  252. + dev_dbg(i2c->dev, "conf %08x, clkdiv %08x, devaddr %08x, " \
  253. + "addr %08x, dataout %08x, datain %08x, " \
  254. + "status %08x, startxfr %08x, bytecnt %08x\n",
  255. + rt_i2c_r32(i2c, REG_CONFIG_REG),
  256. + rt_i2c_r32(i2c, REG_CLKDIV_REG),
  257. + rt_i2c_r32(i2c, REG_DEVADDR_REG),
  258. + rt_i2c_r32(i2c, REG_ADDR_REG),
  259. + rt_i2c_r32(i2c, REG_DATAOUT_REG),
  260. + rt_i2c_r32(i2c, REG_DATAIN_REG),
  261. + rt_i2c_r32(i2c, REG_STATUS_REG),
  262. + rt_i2c_r32(i2c, REG_STARTXFR_REG),
  263. + rt_i2c_r32(i2c, REG_BYTECNT_REG));
  264. +}
  265. +
  266. +static int rt_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
  267. + int num)
  268. +{
  269. + struct rt_i2c *i2c;
  270. + struct i2c_msg *pmsg;
  271. + unsigned char addr;
  272. + int i, j, ret;
  273. + u32 cmd;
  274. +
  275. + i2c = i2c_get_adapdata(adap);
  276. +
  277. + for (i = 0; i < num; i++) {
  278. + pmsg = &msgs[i];
  279. + if (i == (num - 1))
  280. + cmd = 0;
  281. + else
  282. + cmd = NOSTOP_CMD;
  283. +
  284. + dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x, stop: %d\n",
  285. + pmsg->addr, pmsg->len, pmsg->flags,
  286. + (cmd == 0)? 1 : 0);
  287. +
  288. + /* wait hardware idle */
  289. + if ((ret = rt_i2c_wait_idle(i2c)))
  290. + goto err_timeout;
  291. +
  292. + if (pmsg->flags & I2C_M_TEN) {
  293. + rt_i2c_w32(i2c, I2C_CONF_DEFAULT, REG_CONFIG_REG);
  294. + /* 10 bits address */
  295. + addr = 0x78 | ((pmsg->addr >> 8) & 0x03);
  296. + rt_i2c_w32(i2c, addr & I2C_DEVADDR_MASK,
  297. + REG_DEVADDR_REG);
  298. + rt_i2c_w32(i2c, pmsg->addr & I2C_ADDR_MASK,
  299. + REG_ADDR_REG);
  300. + } else {
  301. + rt_i2c_w32(i2c, I2C_CONF_DEFAULT | I2C_ADDR_DIS,
  302. + REG_CONFIG_REG);
  303. + /* 7 bits address */
  304. + rt_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK,
  305. + REG_DEVADDR_REG);
  306. + }
  307. +
  308. + /* buffer length */
  309. + if (pmsg->len == 0)
  310. + cmd |= NODATA_CMD;
  311. + else
  312. + rt_i2c_w32(i2c, SET_BYTECNT(pmsg->len),
  313. + REG_BYTECNT_REG);
  314. +
  315. + j = 0;
  316. + if (pmsg->flags & I2C_M_RD) {
  317. + cmd |= READ_CMD;
  318. + /* start transfer */
  319. + barrier();
  320. + rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
  321. + do {
  322. + /* wait */
  323. + if ((ret = rt_i2c_wait_rx_done(i2c)))
  324. + goto err_timeout;
  325. + /* read data */
  326. + if (pmsg->len)
  327. + pmsg->buf[j] = rt_i2c_r32(i2c,
  328. + REG_DATAIN_REG);
  329. + j++;
  330. + } while (j < pmsg->len);
  331. + } else {
  332. + do {
  333. + /* write data */
  334. + if (pmsg->len)
  335. + rt_i2c_w32(i2c, pmsg->buf[j],
  336. + REG_DATAOUT_REG);
  337. + /* start transfer */
  338. + if (j == 0) {
  339. + barrier();
  340. + rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
  341. + }
  342. + /* wait */
  343. + if ((ret = rt_i2c_wait_tx_done(i2c)))
  344. + goto err_timeout;
  345. + j++;
  346. + } while (j < pmsg->len);
  347. + }
  348. + }
  349. + /* the return value is number of executed messages */
  350. + ret = i;
  351. +
  352. + return ret;
  353. +
  354. +err_timeout:
  355. + rt_i2c_dump_reg(i2c);
  356. + rt_i2c_reset(i2c);
  357. + return ret;
  358. +}
  359. +
  360. +static u32 rt_i2c_func(struct i2c_adapter *a)
  361. +{
  362. + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  363. +}
  364. +
  365. +static const struct i2c_algorithm rt_i2c_algo = {
  366. + .master_xfer = rt_i2c_master_xfer,
  367. + .functionality = rt_i2c_func,
  368. +};
  369. +
  370. +static const struct of_device_id i2c_rt_dt_ids[] = {
  371. + { .compatible = "ralink,rt2880-i2c" },
  372. + { /* sentinel */ }
  373. +};
  374. +
  375. +MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
  376. +
  377. +static struct i2c_adapter_quirks rt_i2c_quirks = {
  378. + .max_write_len = BYTECNT_MAX,
  379. + .max_read_len = BYTECNT_MAX,
  380. +};
  381. +
  382. +static int rt_i2c_init(struct rt_i2c *i2c)
  383. +{
  384. + u32 reg;
  385. +
  386. + /* i2c_sclk = periph_clk / ((2 * clk_div) + 5) */
  387. + i2c->clk_div = (clk_get_rate(i2c->clk) - (5 * i2c->cur_clk)) /
  388. + (2 * i2c->cur_clk);
  389. + if (i2c->clk_div < 8)
  390. + i2c->clk_div = 8;
  391. + if (i2c->clk_div > I2C_CLKDIV_MASK)
  392. + i2c->clk_div = I2C_CLKDIV_MASK;
  393. +
  394. + /* check support combinde/repeated start message */
  395. + rt_i2c_w32(i2c, NOSTOP_CMD, REG_STARTXFR_REG);
  396. + reg = rt_i2c_r32(i2c, REG_STARTXFR_REG) & NOSTOP_CMD;
  397. +
  398. + rt_i2c_reset(i2c);
  399. +
  400. + return reg;
  401. +}
  402. +
  403. +static int rt_i2c_probe(struct platform_device *pdev)
  404. +{
  405. + struct resource *res;
  406. + struct rt_i2c *i2c;
  407. + struct i2c_adapter *adap;
  408. + const struct of_device_id *match;
  409. + int ret, restart;
  410. +
  411. + match = of_match_device(i2c_rt_dt_ids, &pdev->dev);
  412. +
  413. + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  414. + if (!res) {
  415. + dev_err(&pdev->dev, "no memory resource found\n");
  416. + return -ENODEV;
  417. + }
  418. +
  419. + i2c = devm_kzalloc(&pdev->dev, sizeof(struct rt_i2c), GFP_KERNEL);
  420. + if (!i2c) {
  421. + dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
  422. + return -ENOMEM;
  423. + }
  424. +
  425. + i2c->base = devm_ioremap_resource(&pdev->dev, res);
  426. + if (IS_ERR(i2c->base))
  427. + return PTR_ERR(i2c->base);
  428. +
  429. + i2c->clk = devm_clk_get(&pdev->dev, NULL);
  430. + if (IS_ERR(i2c->clk)) {
  431. + dev_err(&pdev->dev, "no clock defined\n");
  432. + return -ENODEV;
  433. + }
  434. + clk_prepare_enable(i2c->clk);
  435. + i2c->dev = &pdev->dev;
  436. +
  437. + if (of_property_read_u32(pdev->dev.of_node,
  438. + "clock-frequency", &i2c->cur_clk))
  439. + i2c->cur_clk = 100000;
  440. +
  441. + adap = &i2c->adap;
  442. + adap->owner = THIS_MODULE;
  443. + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
  444. + adap->algo = &rt_i2c_algo;
  445. + adap->retries = 3;
  446. + adap->dev.parent = &pdev->dev;
  447. + i2c_set_adapdata(adap, i2c);
  448. + adap->dev.of_node = pdev->dev.of_node;
  449. + strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
  450. + adap->quirks = &rt_i2c_quirks;
  451. +
  452. + platform_set_drvdata(pdev, i2c);
  453. +
  454. + restart = rt_i2c_init(i2c);
  455. +
  456. + ret = i2c_add_adapter(adap);
  457. + if (ret < 0) {
  458. + dev_err(&pdev->dev, "failed to add adapter\n");
  459. + clk_disable_unprepare(i2c->clk);
  460. + return ret;
  461. + }
  462. +
  463. + dev_info(&pdev->dev, "clock %uKHz, re-start %ssupport\n",
  464. + i2c->cur_clk/1000, restart ? "" : "not ");
  465. +
  466. + return ret;
  467. +}
  468. +
  469. +static int rt_i2c_remove(struct platform_device *pdev)
  470. +{
  471. + struct rt_i2c *i2c = platform_get_drvdata(pdev);
  472. +
  473. + i2c_del_adapter(&i2c->adap);
  474. + clk_disable_unprepare(i2c->clk);
  475. +
  476. + return 0;
  477. +}
  478. +
  479. +static struct platform_driver rt_i2c_driver = {
  480. + .probe = rt_i2c_probe,
  481. + .remove = rt_i2c_remove,
  482. + .driver = {
  483. + .owner = THIS_MODULE,
  484. + .name = "i2c-ralink",
  485. + .of_match_table = i2c_rt_dt_ids,
  486. + },
  487. +};
  488. +
  489. +static int __init i2c_rt_init (void)
  490. +{
  491. + return platform_driver_register(&rt_i2c_driver);
  492. +}
  493. +subsys_initcall(i2c_rt_init);
  494. +
  495. +static void __exit i2c_rt_exit (void)
  496. +{
  497. + platform_driver_unregister(&rt_i2c_driver);
  498. +}
  499. +module_exit(i2c_rt_exit);
  500. +
  501. +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
  502. +MODULE_DESCRIPTION("Ralink I2c host driver");
  503. +MODULE_LICENSE("GPL");
  504. +MODULE_ALIAS("platform:Ralink-I2C");