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0047-DMA-ralink-add-rt2880-dma-engine.patch 47 KB

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  1. From f1c4d9e622c800e1f38b3818f933ec7597d1ccfb Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Sun, 27 Jul 2014 09:29:51 +0100
  4. Subject: [PATCH 47/53] DMA: ralink: add rt2880 dma engine
  5. Signed-off-by: John Crispin <blogic@openwrt.org>
  6. ---
  7. drivers/dma/Kconfig | 6 +
  8. drivers/dma/Makefile | 1 +
  9. drivers/dma/ralink-gdma.c | 577 +++++++++++++++++++++++++++++++++++++++++++++
  10. include/linux/dmaengine.h | 1 +
  11. 4 files changed, 585 insertions(+)
  12. create mode 100644 drivers/dma/ralink-gdma.c
  13. --- a/drivers/dma/Kconfig
  14. +++ b/drivers/dma/Kconfig
  15. @@ -40,6 +40,18 @@ config ASYNC_TX_ENABLE_CHANNEL_SWITCH
  16. config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
  17. bool
  18. +config DMA_RALINK
  19. + tristate "RALINK DMA support"
  20. + depends on RALINK && !SOC_RT288X
  21. + select DMA_ENGINE
  22. + select DMA_VIRTUAL_CHANNELS
  23. +
  24. +config MTK_HSDMA
  25. + tristate "MTK HSDMA support"
  26. + depends on RALINK && SOC_MT7621
  27. + select DMA_ENGINE
  28. + select DMA_VIRTUAL_CHANNELS
  29. +
  30. config DMA_ENGINE
  31. bool
  32. --- a/drivers/dma/Makefile
  33. +++ b/drivers/dma/Makefile
  34. @@ -65,5 +65,7 @@ obj-$(CONFIG_TI_DMA_CROSSBAR) += ti-dma-
  35. obj-$(CONFIG_TI_EDMA) += edma.o
  36. obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
  37. obj-$(CONFIG_ZX_DMA) += zx296702_dma.o
  38. +obj-$(CONFIG_DMA_RALINK) += ralink-gdma.o
  39. +obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
  40. obj-y += xilinx/
  41. --- /dev/null
  42. +++ b/drivers/dma/ralink-gdma.c
  43. @@ -0,0 +1,928 @@
  44. +/*
  45. + * Copyright (C) 2013, Lars-Peter Clausen <lars@metafoo.de>
  46. + * GDMA4740 DMAC support
  47. + *
  48. + * This program is free software; you can redistribute it and/or modify it
  49. + * under the terms of the GNU General Public License as published by the
  50. + * Free Software Foundation; either version 2 of the License, or (at your
  51. + * option) any later version.
  52. + *
  53. + */
  54. +
  55. +#include <linux/dmaengine.h>
  56. +#include <linux/dma-mapping.h>
  57. +#include <linux/err.h>
  58. +#include <linux/init.h>
  59. +#include <linux/list.h>
  60. +#include <linux/module.h>
  61. +#include <linux/platform_device.h>
  62. +#include <linux/slab.h>
  63. +#include <linux/spinlock.h>
  64. +#include <linux/irq.h>
  65. +#include <linux/of_dma.h>
  66. +#include <linux/reset.h>
  67. +#include <linux/of_device.h>
  68. +
  69. +#include "virt-dma.h"
  70. +
  71. +#define GDMA_REG_SRC_ADDR(x) (0x00 + (x) * 0x10)
  72. +#define GDMA_REG_DST_ADDR(x) (0x04 + (x) * 0x10)
  73. +
  74. +#define GDMA_REG_CTRL0(x) (0x08 + (x) * 0x10)
  75. +#define GDMA_REG_CTRL0_TX_MASK 0xffff
  76. +#define GDMA_REG_CTRL0_TX_SHIFT 16
  77. +#define GDMA_REG_CTRL0_CURR_MASK 0xff
  78. +#define GDMA_REG_CTRL0_CURR_SHIFT 8
  79. +#define GDMA_REG_CTRL0_SRC_ADDR_FIXED BIT(7)
  80. +#define GDMA_REG_CTRL0_DST_ADDR_FIXED BIT(6)
  81. +#define GDMA_REG_CTRL0_BURST_MASK 0x7
  82. +#define GDMA_REG_CTRL0_BURST_SHIFT 3
  83. +#define GDMA_REG_CTRL0_DONE_INT BIT(2)
  84. +#define GDMA_REG_CTRL0_ENABLE BIT(1)
  85. +#define GDMA_REG_CTRL0_SW_MODE BIT(0)
  86. +
  87. +#define GDMA_REG_CTRL1(x) (0x0c + (x) * 0x10)
  88. +#define GDMA_REG_CTRL1_SEG_MASK 0xf
  89. +#define GDMA_REG_CTRL1_SEG_SHIFT 22
  90. +#define GDMA_REG_CTRL1_REQ_MASK 0x3f
  91. +#define GDMA_REG_CTRL1_SRC_REQ_SHIFT 16
  92. +#define GDMA_REG_CTRL1_DST_REQ_SHIFT 8
  93. +#define GDMA_REG_CTRL1_CONTINOUS BIT(14)
  94. +#define GDMA_REG_CTRL1_NEXT_MASK 0x1f
  95. +#define GDMA_REG_CTRL1_NEXT_SHIFT 3
  96. +#define GDMA_REG_CTRL1_COHERENT BIT(2)
  97. +#define GDMA_REG_CTRL1_FAIL BIT(1)
  98. +#define GDMA_REG_CTRL1_MASK BIT(0)
  99. +
  100. +#define GDMA_REG_UNMASK_INT 0x200
  101. +#define GDMA_REG_DONE_INT 0x204
  102. +
  103. +#define GDMA_REG_GCT 0x220
  104. +#define GDMA_REG_GCT_CHAN_MASK 0x3
  105. +#define GDMA_REG_GCT_CHAN_SHIFT 3
  106. +#define GDMA_REG_GCT_VER_MASK 0x3
  107. +#define GDMA_REG_GCT_VER_SHIFT 1
  108. +#define GDMA_REG_GCT_ARBIT_RR BIT(0)
  109. +
  110. +#define GDMA_REG_REQSTS 0x2a0
  111. +#define GDMA_REG_ACKSTS 0x2a4
  112. +#define GDMA_REG_FINSTS 0x2a8
  113. +
  114. +/* for RT305X gdma registers */
  115. +#define GDMA_RT305X_CTRL0_REQ_MASK 0xf
  116. +#define GDMA_RT305X_CTRL0_SRC_REQ_SHIFT 12
  117. +#define GDMA_RT305X_CTRL0_DST_REQ_SHIFT 8
  118. +
  119. +#define GDMA_RT305X_CTRL1_FAIL BIT(4)
  120. +#define GDMA_RT305X_CTRL1_NEXT_MASK 0x7
  121. +#define GDMA_RT305X_CTRL1_NEXT_SHIFT 1
  122. +
  123. +#define GDMA_RT305X_STATUS_INT 0x80
  124. +#define GDMA_RT305X_STATUS_SIGNAL 0x84
  125. +#define GDMA_RT305X_GCT 0x88
  126. +
  127. +/* for MT7621 gdma registers */
  128. +#define GDMA_REG_PERF_START(x) (0x230 + (x) * 0x8)
  129. +#define GDMA_REG_PERF_END(x) (0x234 + (x) * 0x8)
  130. +
  131. +enum gdma_dma_transfer_size {
  132. + GDMA_TRANSFER_SIZE_4BYTE = 0,
  133. + GDMA_TRANSFER_SIZE_8BYTE = 1,
  134. + GDMA_TRANSFER_SIZE_16BYTE = 2,
  135. + GDMA_TRANSFER_SIZE_32BYTE = 3,
  136. + GDMA_TRANSFER_SIZE_64BYTE = 4,
  137. +};
  138. +
  139. +struct gdma_dma_sg {
  140. + dma_addr_t src_addr;
  141. + dma_addr_t dst_addr;
  142. + u32 len;
  143. +};
  144. +
  145. +struct gdma_dma_desc {
  146. + struct virt_dma_desc vdesc;
  147. +
  148. + enum dma_transfer_direction direction;
  149. + bool cyclic;
  150. +
  151. + u32 residue;
  152. + unsigned int num_sgs;
  153. + struct gdma_dma_sg sg[];
  154. +};
  155. +
  156. +struct gdma_dmaengine_chan {
  157. + struct virt_dma_chan vchan;
  158. + unsigned int id;
  159. + unsigned int slave_id;
  160. +
  161. + dma_addr_t fifo_addr;
  162. + enum gdma_dma_transfer_size burst_size;
  163. +
  164. + struct gdma_dma_desc *desc;
  165. + unsigned int next_sg;
  166. +};
  167. +
  168. +struct gdma_dma_dev {
  169. + struct dma_device ddev;
  170. + struct device_dma_parameters dma_parms;
  171. + struct gdma_data *data;
  172. + void __iomem *base;
  173. + struct tasklet_struct task;
  174. + volatile unsigned long chan_issued;
  175. + atomic_t cnt;
  176. +
  177. + struct gdma_dmaengine_chan chan[];
  178. +};
  179. +
  180. +struct gdma_data
  181. +{
  182. + int chancnt;
  183. + u32 done_int_reg;
  184. + void (*init)(struct gdma_dma_dev *dma_dev);
  185. + int (*start_transfer)(struct gdma_dmaengine_chan *chan);
  186. +};
  187. +
  188. +static struct gdma_dma_dev *gdma_dma_chan_get_dev(
  189. + struct gdma_dmaengine_chan *chan)
  190. +{
  191. + return container_of(chan->vchan.chan.device, struct gdma_dma_dev,
  192. + ddev);
  193. +}
  194. +
  195. +static struct gdma_dmaengine_chan *to_gdma_dma_chan(struct dma_chan *c)
  196. +{
  197. + return container_of(c, struct gdma_dmaengine_chan, vchan.chan);
  198. +}
  199. +
  200. +static struct gdma_dma_desc *to_gdma_dma_desc(struct virt_dma_desc *vdesc)
  201. +{
  202. + return container_of(vdesc, struct gdma_dma_desc, vdesc);
  203. +}
  204. +
  205. +static inline uint32_t gdma_dma_read(struct gdma_dma_dev *dma_dev,
  206. + unsigned int reg)
  207. +{
  208. + return readl(dma_dev->base + reg);
  209. +}
  210. +
  211. +static inline void gdma_dma_write(struct gdma_dma_dev *dma_dev,
  212. + unsigned reg, uint32_t val)
  213. +{
  214. + writel(val, dma_dev->base + reg);
  215. +}
  216. +
  217. +static struct gdma_dma_desc *gdma_dma_alloc_desc(unsigned int num_sgs)
  218. +{
  219. + return kzalloc(sizeof(struct gdma_dma_desc) +
  220. + sizeof(struct gdma_dma_sg) * num_sgs, GFP_ATOMIC);
  221. +}
  222. +
  223. +static enum gdma_dma_transfer_size gdma_dma_maxburst(u32 maxburst)
  224. +{
  225. + if (maxburst < 2)
  226. + return GDMA_TRANSFER_SIZE_4BYTE;
  227. + else if (maxburst < 4)
  228. + return GDMA_TRANSFER_SIZE_8BYTE;
  229. + else if (maxburst < 8)
  230. + return GDMA_TRANSFER_SIZE_16BYTE;
  231. + else if (maxburst < 16)
  232. + return GDMA_TRANSFER_SIZE_32BYTE;
  233. + else
  234. + return GDMA_TRANSFER_SIZE_64BYTE;
  235. +}
  236. +
  237. +static int gdma_dma_config(struct dma_chan *c,
  238. + struct dma_slave_config *config)
  239. +{
  240. + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
  241. + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
  242. +
  243. + if (config->device_fc) {
  244. + dev_err(dma_dev->ddev.dev, "not support flow controller\n");
  245. + return -EINVAL;
  246. + }
  247. +
  248. + switch (config->direction) {
  249. + case DMA_MEM_TO_DEV:
  250. + if (config->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) {
  251. + dev_err(dma_dev->ddev.dev, "only support 4 byte buswidth\n");
  252. + return -EINVAL;
  253. + }
  254. + chan->slave_id = config->slave_id;
  255. + chan->fifo_addr = config->dst_addr;
  256. + chan->burst_size = gdma_dma_maxburst(config->dst_maxburst);
  257. + break;
  258. + case DMA_DEV_TO_MEM:
  259. + if (config->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) {
  260. + dev_err(dma_dev->ddev.dev, "only support 4 byte buswidth\n");
  261. + return -EINVAL;
  262. + }
  263. + chan->slave_id = config->slave_id;
  264. + chan->fifo_addr = config->src_addr;
  265. + chan->burst_size = gdma_dma_maxburst(config->src_maxburst);
  266. + break;
  267. + default:
  268. + dev_err(dma_dev->ddev.dev, "direction type %d error\n",
  269. + config->direction);
  270. + return -EINVAL;
  271. + }
  272. +
  273. + return 0;
  274. +}
  275. +
  276. +static int gdma_dma_terminate_all(struct dma_chan *c)
  277. +{
  278. + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
  279. + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
  280. + unsigned long flags, timeout;
  281. + LIST_HEAD(head);
  282. + int i = 0;
  283. +
  284. + spin_lock_irqsave(&chan->vchan.lock, flags);
  285. + chan->desc = NULL;
  286. + clear_bit(chan->id, &dma_dev->chan_issued);
  287. + vchan_get_all_descriptors(&chan->vchan, &head);
  288. + spin_unlock_irqrestore(&chan->vchan.lock, flags);
  289. +
  290. + vchan_dma_desc_free_list(&chan->vchan, &head);
  291. +
  292. + /* wait dma transfer complete */
  293. + timeout = jiffies + msecs_to_jiffies(5000);
  294. + while (gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id)) &
  295. + GDMA_REG_CTRL0_ENABLE) {
  296. + if (time_after_eq(jiffies, timeout)) {
  297. + dev_err(dma_dev->ddev.dev, "chan %d wait timeout\n",
  298. + chan->id);
  299. + /* restore to init value */
  300. + gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), 0);
  301. + break;
  302. + }
  303. + cpu_relax();
  304. + i++;
  305. + }
  306. +
  307. + if (i)
  308. + dev_dbg(dma_dev->ddev.dev, "terminate chan %d loops %d\n",
  309. + chan->id, i);
  310. +
  311. + return 0;
  312. +}
  313. +
  314. +static void rt305x_dump_reg(struct gdma_dma_dev *dma_dev, int id)
  315. +{
  316. + dev_dbg(dma_dev->ddev.dev, "chan %d, src %08x, dst %08x, ctr0 %08x, " \
  317. + "ctr1 %08x, intr %08x, signal %08x\n", id,
  318. + gdma_dma_read(dma_dev, GDMA_REG_SRC_ADDR(id)),
  319. + gdma_dma_read(dma_dev, GDMA_REG_DST_ADDR(id)),
  320. + gdma_dma_read(dma_dev, GDMA_REG_CTRL0(id)),
  321. + gdma_dma_read(dma_dev, GDMA_REG_CTRL1(id)),
  322. + gdma_dma_read(dma_dev, GDMA_RT305X_STATUS_INT),
  323. + gdma_dma_read(dma_dev, GDMA_RT305X_STATUS_SIGNAL));
  324. +}
  325. +
  326. +static int rt305x_gdma_start_transfer(struct gdma_dmaengine_chan *chan)
  327. +{
  328. + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
  329. + dma_addr_t src_addr, dst_addr;
  330. + struct gdma_dma_sg *sg;
  331. + uint32_t ctrl0, ctrl1;
  332. +
  333. + /* verify chan is already stopped */
  334. + ctrl0 = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
  335. + if (unlikely(ctrl0 & GDMA_REG_CTRL0_ENABLE)) {
  336. + dev_err(dma_dev->ddev.dev, "chan %d is start(%08x).\n",
  337. + chan->id, ctrl0);
  338. + rt305x_dump_reg(dma_dev, chan->id);
  339. + return -EINVAL;
  340. + }
  341. +
  342. + sg = &chan->desc->sg[chan->next_sg];
  343. + if (chan->desc->direction == DMA_MEM_TO_DEV) {
  344. + src_addr = sg->src_addr;
  345. + dst_addr = chan->fifo_addr;
  346. + ctrl0 = GDMA_REG_CTRL0_DST_ADDR_FIXED | \
  347. + (8 << GDMA_RT305X_CTRL0_SRC_REQ_SHIFT) | \
  348. + (chan->slave_id << GDMA_RT305X_CTRL0_DST_REQ_SHIFT);
  349. + } else if (chan->desc->direction == DMA_DEV_TO_MEM) {
  350. + src_addr = chan->fifo_addr;
  351. + dst_addr = sg->dst_addr;
  352. + ctrl0 = GDMA_REG_CTRL0_SRC_ADDR_FIXED | \
  353. + (chan->slave_id << GDMA_RT305X_CTRL0_SRC_REQ_SHIFT) | \
  354. + (8 << GDMA_RT305X_CTRL0_DST_REQ_SHIFT);
  355. + } else if (chan->desc->direction == DMA_MEM_TO_MEM) {
  356. + /*
  357. + * TODO: memcpy function have bugs. sometime it will copy
  358. + * more 8 bytes data when using dmatest verify.
  359. + */
  360. + src_addr = sg->src_addr;
  361. + dst_addr = sg->dst_addr;
  362. + ctrl0 = GDMA_REG_CTRL0_SW_MODE | \
  363. + (8 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) | \
  364. + (8 << GDMA_REG_CTRL1_DST_REQ_SHIFT);
  365. + } else {
  366. + dev_err(dma_dev->ddev.dev, "direction type %d error\n",
  367. + chan->desc->direction);
  368. + return -EINVAL;
  369. + }
  370. +
  371. + ctrl0 |= (sg->len << GDMA_REG_CTRL0_TX_SHIFT) | \
  372. + (chan->burst_size << GDMA_REG_CTRL0_BURST_SHIFT) | \
  373. + GDMA_REG_CTRL0_DONE_INT | GDMA_REG_CTRL0_ENABLE;
  374. + ctrl1 = chan->id << GDMA_REG_CTRL1_NEXT_SHIFT;
  375. +
  376. + chan->next_sg++;
  377. + gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr);
  378. + gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr);
  379. + gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1);
  380. +
  381. + /* make sure next_sg is update */
  382. + wmb();
  383. + gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0);
  384. +
  385. + return 0;
  386. +}
  387. +
  388. +static void rt3883_dump_reg(struct gdma_dma_dev *dma_dev, int id)
  389. +{
  390. + dev_dbg(dma_dev->ddev.dev, "chan %d, src %08x, dst %08x, ctr0 %08x, " \
  391. + "ctr1 %08x, unmask %08x, done %08x, " \
  392. + "req %08x, ack %08x, fin %08x\n", id,
  393. + gdma_dma_read(dma_dev, GDMA_REG_SRC_ADDR(id)),
  394. + gdma_dma_read(dma_dev, GDMA_REG_DST_ADDR(id)),
  395. + gdma_dma_read(dma_dev, GDMA_REG_CTRL0(id)),
  396. + gdma_dma_read(dma_dev, GDMA_REG_CTRL1(id)),
  397. + gdma_dma_read(dma_dev, GDMA_REG_UNMASK_INT),
  398. + gdma_dma_read(dma_dev, GDMA_REG_DONE_INT),
  399. + gdma_dma_read(dma_dev, GDMA_REG_REQSTS),
  400. + gdma_dma_read(dma_dev, GDMA_REG_ACKSTS),
  401. + gdma_dma_read(dma_dev, GDMA_REG_FINSTS));
  402. +}
  403. +
  404. +static int rt3883_gdma_start_transfer(struct gdma_dmaengine_chan *chan)
  405. +{
  406. + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
  407. + dma_addr_t src_addr, dst_addr;
  408. + struct gdma_dma_sg *sg;
  409. + uint32_t ctrl0, ctrl1;
  410. +
  411. + /* verify chan is already stopped */
  412. + ctrl0 = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
  413. + if (unlikely(ctrl0 & GDMA_REG_CTRL0_ENABLE)) {
  414. + dev_err(dma_dev->ddev.dev, "chan %d is start(%08x).\n",
  415. + chan->id, ctrl0);
  416. + rt3883_dump_reg(dma_dev, chan->id);
  417. + return -EINVAL;
  418. + }
  419. +
  420. + sg = &chan->desc->sg[chan->next_sg];
  421. + if (chan->desc->direction == DMA_MEM_TO_DEV) {
  422. + src_addr = sg->src_addr;
  423. + dst_addr = chan->fifo_addr;
  424. + ctrl0 = GDMA_REG_CTRL0_DST_ADDR_FIXED;
  425. + ctrl1 = (32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) | \
  426. + (chan->slave_id << GDMA_REG_CTRL1_DST_REQ_SHIFT);
  427. + } else if (chan->desc->direction == DMA_DEV_TO_MEM) {
  428. + src_addr = chan->fifo_addr;
  429. + dst_addr = sg->dst_addr;
  430. + ctrl0 = GDMA_REG_CTRL0_SRC_ADDR_FIXED;
  431. + ctrl1 = (chan->slave_id << GDMA_REG_CTRL1_SRC_REQ_SHIFT) | \
  432. + (32 << GDMA_REG_CTRL1_DST_REQ_SHIFT) | \
  433. + GDMA_REG_CTRL1_COHERENT;
  434. + } else if (chan->desc->direction == DMA_MEM_TO_MEM) {
  435. + src_addr = sg->src_addr;
  436. + dst_addr = sg->dst_addr;
  437. + ctrl0 = GDMA_REG_CTRL0_SW_MODE;
  438. + ctrl1 = (32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) | \
  439. + (32 << GDMA_REG_CTRL1_DST_REQ_SHIFT) | \
  440. + GDMA_REG_CTRL1_COHERENT;
  441. + } else {
  442. + dev_err(dma_dev->ddev.dev, "direction type %d error\n",
  443. + chan->desc->direction);
  444. + return -EINVAL;
  445. + }
  446. +
  447. + ctrl0 |= (sg->len << GDMA_REG_CTRL0_TX_SHIFT) | \
  448. + (chan->burst_size << GDMA_REG_CTRL0_BURST_SHIFT) | \
  449. + GDMA_REG_CTRL0_DONE_INT | GDMA_REG_CTRL0_ENABLE;
  450. + ctrl1 |= chan->id << GDMA_REG_CTRL1_NEXT_SHIFT;
  451. +
  452. + chan->next_sg++;
  453. + gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr);
  454. + gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr);
  455. + gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1);
  456. +
  457. + /* make sure next_sg is update */
  458. + wmb();
  459. + gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0);
  460. +
  461. + return 0;
  462. +}
  463. +
  464. +static inline int gdma_start_transfer(struct gdma_dma_dev *dma_dev,
  465. + struct gdma_dmaengine_chan *chan)
  466. +{
  467. + return dma_dev->data->start_transfer(chan);
  468. +}
  469. +
  470. +static int gdma_next_desc(struct gdma_dmaengine_chan *chan)
  471. +{
  472. + struct virt_dma_desc *vdesc;
  473. +
  474. + vdesc = vchan_next_desc(&chan->vchan);
  475. + if (!vdesc) {
  476. + chan->desc = NULL;
  477. + return 0;
  478. + }
  479. + chan->desc = to_gdma_dma_desc(vdesc);
  480. + chan->next_sg = 0;
  481. +
  482. + return 1;
  483. +}
  484. +
  485. +static void gdma_dma_chan_irq(struct gdma_dma_dev *dma_dev,
  486. + struct gdma_dmaengine_chan *chan)
  487. +{
  488. + struct gdma_dma_desc *desc;
  489. + unsigned long flags;
  490. + int chan_issued;
  491. +
  492. + chan_issued = 0;
  493. + spin_lock_irqsave(&chan->vchan.lock, flags);
  494. + desc = chan->desc;
  495. + if (desc) {
  496. + if (desc->cyclic) {
  497. + vchan_cyclic_callback(&desc->vdesc);
  498. + if (chan->next_sg == desc->num_sgs)
  499. + chan->next_sg = 0;
  500. + chan_issued = 1;
  501. + } else {
  502. + desc->residue -= desc->sg[chan->next_sg - 1].len;
  503. + if (chan->next_sg == desc->num_sgs) {
  504. + list_del(&desc->vdesc.node);
  505. + vchan_cookie_complete(&desc->vdesc);
  506. + chan_issued = gdma_next_desc(chan);
  507. + } else
  508. + chan_issued = 1;
  509. + }
  510. + } else
  511. + dev_dbg(dma_dev->ddev.dev, "chan %d no desc to complete\n",
  512. + chan->id);
  513. + if (chan_issued)
  514. + set_bit(chan->id, &dma_dev->chan_issued);
  515. + spin_unlock_irqrestore(&chan->vchan.lock, flags);
  516. +}
  517. +
  518. +static irqreturn_t gdma_dma_irq(int irq, void *devid)
  519. +{
  520. + struct gdma_dma_dev *dma_dev = devid;
  521. + u32 done, done_reg;
  522. + unsigned int i;
  523. +
  524. + done_reg = dma_dev->data->done_int_reg;
  525. + done = gdma_dma_read(dma_dev, done_reg);
  526. + if (unlikely(!done))
  527. + return IRQ_NONE;
  528. +
  529. + /* clean done bits */
  530. + gdma_dma_write(dma_dev, done_reg, done);
  531. +
  532. + i = 0;
  533. + while (done) {
  534. + if (done & 0x1) {
  535. + gdma_dma_chan_irq(dma_dev, &dma_dev->chan[i]);
  536. + atomic_dec(&dma_dev->cnt);
  537. + }
  538. + done >>= 1;
  539. + i++;
  540. + }
  541. +
  542. + /* start only have work to do */
  543. + if (dma_dev->chan_issued)
  544. + tasklet_schedule(&dma_dev->task);
  545. +
  546. + return IRQ_HANDLED;
  547. +}
  548. +
  549. +static void gdma_dma_issue_pending(struct dma_chan *c)
  550. +{
  551. + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
  552. + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
  553. + unsigned long flags;
  554. +
  555. + spin_lock_irqsave(&chan->vchan.lock, flags);
  556. + if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
  557. + if (gdma_next_desc(chan)) {
  558. + set_bit(chan->id, &dma_dev->chan_issued);
  559. + tasklet_schedule(&dma_dev->task);
  560. + } else
  561. + dev_dbg(dma_dev->ddev.dev, "chan %d no desc to issue\n",
  562. + chan->id);
  563. + }
  564. + spin_unlock_irqrestore(&chan->vchan.lock, flags);
  565. +}
  566. +
  567. +static struct dma_async_tx_descriptor *gdma_dma_prep_slave_sg(
  568. + struct dma_chan *c, struct scatterlist *sgl,
  569. + unsigned int sg_len, enum dma_transfer_direction direction,
  570. + unsigned long flags, void *context)
  571. +{
  572. + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
  573. + struct gdma_dma_desc *desc;
  574. + struct scatterlist *sg;
  575. + unsigned int i;
  576. +
  577. + desc = gdma_dma_alloc_desc(sg_len);
  578. + if (!desc) {
  579. + dev_err(c->device->dev, "alloc sg decs error\n");
  580. + return NULL;
  581. + }
  582. + desc->residue = 0;
  583. +
  584. + for_each_sg(sgl, sg, sg_len, i) {
  585. + if (direction == DMA_MEM_TO_DEV)
  586. + desc->sg[i].src_addr = sg_dma_address(sg);
  587. + else if (direction == DMA_DEV_TO_MEM)
  588. + desc->sg[i].dst_addr = sg_dma_address(sg);
  589. + else {
  590. + dev_err(c->device->dev, "direction type %d error\n",
  591. + direction);
  592. + goto free_desc;
  593. + }
  594. +
  595. + if (unlikely(sg_dma_len(sg) > GDMA_REG_CTRL0_TX_MASK)) {
  596. + dev_err(c->device->dev, "sg len too large %d\n",
  597. + sg_dma_len(sg));
  598. + goto free_desc;
  599. + }
  600. + desc->sg[i].len = sg_dma_len(sg);
  601. + desc->residue += sg_dma_len(sg);
  602. + }
  603. +
  604. + desc->num_sgs = sg_len;
  605. + desc->direction = direction;
  606. + desc->cyclic = false;
  607. +
  608. + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
  609. +
  610. +free_desc:
  611. + kfree(desc);
  612. + return NULL;
  613. +}
  614. +
  615. +static struct dma_async_tx_descriptor * gdma_dma_prep_dma_memcpy(
  616. + struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
  617. + size_t len, unsigned long flags)
  618. +{
  619. + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
  620. + struct gdma_dma_desc *desc;
  621. + unsigned int num_periods, i;
  622. + size_t xfer_count;
  623. +
  624. + if (len <= 0)
  625. + return NULL;
  626. +
  627. + chan->burst_size = gdma_dma_maxburst(len >> 2);
  628. +
  629. + xfer_count = GDMA_REG_CTRL0_TX_MASK;
  630. + num_periods = DIV_ROUND_UP(len, xfer_count);
  631. +
  632. + desc = gdma_dma_alloc_desc(num_periods);
  633. + if (!desc) {
  634. + dev_err(c->device->dev, "alloc memcpy decs error\n");
  635. + return NULL;
  636. + }
  637. + desc->residue = len;
  638. +
  639. + for (i = 0; i < num_periods; i++) {
  640. + desc->sg[i].src_addr = src;
  641. + desc->sg[i].dst_addr = dest;
  642. + if (len > xfer_count) {
  643. + desc->sg[i].len = xfer_count;
  644. + } else {
  645. + desc->sg[i].len = len;
  646. + }
  647. + src += desc->sg[i].len;
  648. + dest += desc->sg[i].len;
  649. + len -= desc->sg[i].len;
  650. + }
  651. +
  652. + desc->num_sgs = num_periods;
  653. + desc->direction = DMA_MEM_TO_MEM;
  654. + desc->cyclic = false;
  655. +
  656. + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
  657. +}
  658. +
  659. +static struct dma_async_tx_descriptor *gdma_dma_prep_dma_cyclic(
  660. + struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
  661. + size_t period_len, enum dma_transfer_direction direction,
  662. + unsigned long flags)
  663. +{
  664. + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
  665. + struct gdma_dma_desc *desc;
  666. + unsigned int num_periods, i;
  667. +
  668. + if (buf_len % period_len)
  669. + return NULL;
  670. +
  671. + if (period_len > GDMA_REG_CTRL0_TX_MASK) {
  672. + dev_err(c->device->dev, "cyclic len too large %d\n",
  673. + period_len);
  674. + return NULL;
  675. + }
  676. +
  677. + num_periods = buf_len / period_len;
  678. + desc = gdma_dma_alloc_desc(num_periods);
  679. + if (!desc) {
  680. + dev_err(c->device->dev, "alloc cyclic decs error\n");
  681. + return NULL;
  682. + }
  683. + desc->residue = buf_len;
  684. +
  685. + for (i = 0; i < num_periods; i++) {
  686. + if (direction == DMA_MEM_TO_DEV)
  687. + desc->sg[i].src_addr = buf_addr;
  688. + else if (direction == DMA_DEV_TO_MEM)
  689. + desc->sg[i].dst_addr = buf_addr;
  690. + else {
  691. + dev_err(c->device->dev, "direction type %d error\n",
  692. + direction);
  693. + goto free_desc;
  694. + }
  695. + desc->sg[i].len = period_len;
  696. + buf_addr += period_len;
  697. + }
  698. +
  699. + desc->num_sgs = num_periods;
  700. + desc->direction = direction;
  701. + desc->cyclic = true;
  702. +
  703. + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
  704. +
  705. +free_desc:
  706. + kfree(desc);
  707. + return NULL;
  708. +}
  709. +
  710. +static enum dma_status gdma_dma_tx_status(struct dma_chan *c,
  711. + dma_cookie_t cookie, struct dma_tx_state *state)
  712. +{
  713. + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
  714. + struct virt_dma_desc *vdesc;
  715. + enum dma_status status;
  716. + unsigned long flags;
  717. + struct gdma_dma_desc *desc;
  718. +
  719. + status = dma_cookie_status(c, cookie, state);
  720. + if (status == DMA_COMPLETE || !state)
  721. + return status;
  722. +
  723. + spin_lock_irqsave(&chan->vchan.lock, flags);
  724. + desc = chan->desc;
  725. + if (desc && (cookie == desc->vdesc.tx.cookie)) {
  726. + /*
  727. + * We never update edesc->residue in the cyclic case, so we
  728. + * can tell the remaining room to the end of the circular
  729. + * buffer.
  730. + */
  731. + if (desc->cyclic)
  732. + state->residue = desc->residue -
  733. + ((chan->next_sg - 1) * desc->sg[0].len);
  734. + else
  735. + state->residue = desc->residue;
  736. + } else if ((vdesc = vchan_find_desc(&chan->vchan, cookie)))
  737. + state->residue = to_gdma_dma_desc(vdesc)->residue;
  738. + spin_unlock_irqrestore(&chan->vchan.lock, flags);
  739. +
  740. + dev_dbg(c->device->dev, "tx residue %d bytes\n", state->residue);
  741. +
  742. + return status;
  743. +}
  744. +
  745. +static void gdma_dma_free_chan_resources(struct dma_chan *c)
  746. +{
  747. + vchan_free_chan_resources(to_virt_chan(c));
  748. +}
  749. +
  750. +static void gdma_dma_desc_free(struct virt_dma_desc *vdesc)
  751. +{
  752. + kfree(container_of(vdesc, struct gdma_dma_desc, vdesc));
  753. +}
  754. +
  755. +static void gdma_dma_tasklet(unsigned long arg)
  756. +{
  757. + struct gdma_dma_dev *dma_dev = (struct gdma_dma_dev *)arg;
  758. + struct gdma_dmaengine_chan *chan;
  759. + static unsigned int last_chan;
  760. + unsigned int i, chan_mask;
  761. +
  762. + /* record last chan to round robin all chans */
  763. + i = last_chan;
  764. + chan_mask = dma_dev->data->chancnt - 1;
  765. + do {
  766. + /*
  767. + * on mt7621. when verify with dmatest with all
  768. + * channel is enable. we need to limit only two
  769. + * channel is working at the same time. otherwise the
  770. + * data will have problem.
  771. + */
  772. + if (atomic_read(&dma_dev->cnt) >= 2) {
  773. + last_chan = i;
  774. + break;
  775. + }
  776. +
  777. + if (test_and_clear_bit(i, &dma_dev->chan_issued)) {
  778. + chan = &dma_dev->chan[i];
  779. + if (chan->desc) {
  780. + atomic_inc(&dma_dev->cnt);
  781. + gdma_start_transfer(dma_dev, chan);
  782. + } else
  783. + dev_dbg(dma_dev->ddev.dev, "chan %d no desc to issue\n", chan->id);
  784. +
  785. + if (!dma_dev->chan_issued)
  786. + break;
  787. + }
  788. +
  789. + i = (i + 1) & chan_mask;
  790. + } while (i != last_chan);
  791. +}
  792. +
  793. +static void rt305x_gdma_init(struct gdma_dma_dev *dma_dev)
  794. +{
  795. + uint32_t gct;
  796. +
  797. + /* all chans round robin */
  798. + gdma_dma_write(dma_dev, GDMA_RT305X_GCT, GDMA_REG_GCT_ARBIT_RR);
  799. +
  800. + gct = gdma_dma_read(dma_dev, GDMA_RT305X_GCT);
  801. + dev_info(dma_dev->ddev.dev, "revision: %d, channels: %d\n",
  802. + (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
  803. + 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) &
  804. + GDMA_REG_GCT_CHAN_MASK));
  805. +}
  806. +
  807. +static void rt3883_gdma_init(struct gdma_dma_dev *dma_dev)
  808. +{
  809. + uint32_t gct;
  810. +
  811. + /* all chans round robin */
  812. + gdma_dma_write(dma_dev, GDMA_REG_GCT, GDMA_REG_GCT_ARBIT_RR);
  813. +
  814. + gct = gdma_dma_read(dma_dev, GDMA_REG_GCT);
  815. + dev_info(dma_dev->ddev.dev, "revision: %d, channels: %d\n",
  816. + (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
  817. + 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) &
  818. + GDMA_REG_GCT_CHAN_MASK));
  819. +}
  820. +
  821. +static struct gdma_data rt305x_gdma_data = {
  822. + .chancnt = 8,
  823. + .done_int_reg = GDMA_RT305X_STATUS_INT,
  824. + .init = rt305x_gdma_init,
  825. + .start_transfer = rt305x_gdma_start_transfer,
  826. +};
  827. +
  828. +static struct gdma_data rt3883_gdma_data = {
  829. + .chancnt = 16,
  830. + .done_int_reg = GDMA_REG_DONE_INT,
  831. + .init = rt3883_gdma_init,
  832. + .start_transfer = rt3883_gdma_start_transfer,
  833. +};
  834. +
  835. +static const struct of_device_id gdma_of_match_table[] = {
  836. + { .compatible = "ralink,rt305x-gdma", .data = &rt305x_gdma_data },
  837. + { .compatible = "ralink,rt3883-gdma", .data = &rt3883_gdma_data },
  838. + { },
  839. +};
  840. +
  841. +static int gdma_dma_probe(struct platform_device *pdev)
  842. +{
  843. + const struct of_device_id *match;
  844. + struct gdma_dmaengine_chan *chan;
  845. + struct gdma_dma_dev *dma_dev;
  846. + struct dma_device *dd;
  847. + unsigned int i;
  848. + struct resource *res;
  849. + int ret;
  850. + int irq;
  851. + void __iomem *base;
  852. + struct gdma_data *data;
  853. +
  854. + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
  855. + if (ret)
  856. + return ret;
  857. +
  858. + match = of_match_device(gdma_of_match_table, &pdev->dev);
  859. + if (!match)
  860. + return -EINVAL;
  861. + data = (struct gdma_data *) match->data;
  862. +
  863. + dma_dev = devm_kzalloc(&pdev->dev, sizeof(*dma_dev) +
  864. + (sizeof(struct gdma_dmaengine_chan) * data->chancnt),
  865. + GFP_KERNEL);
  866. + if (!dma_dev) {
  867. + dev_err(&pdev->dev, "alloc dma device failed\n");
  868. + return -EINVAL;
  869. + }
  870. + dma_dev->data = data;
  871. +
  872. + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  873. + base = devm_ioremap_resource(&pdev->dev, res);
  874. + if (IS_ERR(base))
  875. + return PTR_ERR(base);
  876. + dma_dev->base = base;
  877. + tasklet_init(&dma_dev->task, gdma_dma_tasklet, (unsigned long)dma_dev);
  878. +
  879. + irq = platform_get_irq(pdev, 0);
  880. + if (irq < 0) {
  881. + dev_err(&pdev->dev, "failed to get irq\n");
  882. + return -EINVAL;
  883. + }
  884. + ret = devm_request_irq(&pdev->dev, irq, gdma_dma_irq,
  885. + 0, dev_name(&pdev->dev), dma_dev);
  886. + if (ret) {
  887. + dev_err(&pdev->dev, "failed to request irq\n");
  888. + return ret;
  889. + }
  890. +
  891. + device_reset(&pdev->dev);
  892. +
  893. + dd = &dma_dev->ddev;
  894. + dma_cap_set(DMA_MEMCPY, dd->cap_mask);
  895. + dma_cap_set(DMA_SLAVE, dd->cap_mask);
  896. + dma_cap_set(DMA_CYCLIC, dd->cap_mask);
  897. + dd->device_free_chan_resources = gdma_dma_free_chan_resources;
  898. + dd->device_prep_dma_memcpy = gdma_dma_prep_dma_memcpy;
  899. + dd->device_prep_slave_sg = gdma_dma_prep_slave_sg;
  900. + dd->device_prep_dma_cyclic = gdma_dma_prep_dma_cyclic;
  901. + dd->device_config = gdma_dma_config;
  902. + dd->device_terminate_all = gdma_dma_terminate_all;
  903. + dd->device_tx_status = gdma_dma_tx_status;
  904. + dd->device_issue_pending = gdma_dma_issue_pending;
  905. +
  906. + dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
  907. + dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
  908. + dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
  909. + dd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
  910. +
  911. + dd->dev = &pdev->dev;
  912. + dd->dev->dma_parms = &dma_dev->dma_parms;
  913. + dma_set_max_seg_size(dd->dev, GDMA_REG_CTRL0_TX_MASK);
  914. + INIT_LIST_HEAD(&dd->channels);
  915. +
  916. + for (i = 0; i < data->chancnt; i++) {
  917. + chan = &dma_dev->chan[i];
  918. + chan->id = i;
  919. + chan->vchan.desc_free = gdma_dma_desc_free;
  920. + vchan_init(&chan->vchan, dd);
  921. + }
  922. +
  923. + /* init hardware */
  924. + data->init(dma_dev);
  925. +
  926. + ret = dma_async_device_register(dd);
  927. + if (ret) {
  928. + dev_err(&pdev->dev, "failed to register dma device\n");
  929. + return ret;
  930. + }
  931. +
  932. + ret = of_dma_controller_register(pdev->dev.of_node,
  933. + of_dma_xlate_by_chan_id, dma_dev);
  934. + if (ret) {
  935. + dev_err(&pdev->dev, "failed to register of dma controller\n");
  936. + goto err_unregister;
  937. + }
  938. +
  939. + platform_set_drvdata(pdev, dma_dev);
  940. +
  941. + return 0;
  942. +
  943. +err_unregister:
  944. + dma_async_device_unregister(dd);
  945. + return ret;
  946. +}
  947. +
  948. +static int gdma_dma_remove(struct platform_device *pdev)
  949. +{
  950. + struct gdma_dma_dev *dma_dev = platform_get_drvdata(pdev);
  951. +
  952. + tasklet_kill(&dma_dev->task);
  953. + of_dma_controller_free(pdev->dev.of_node);
  954. + dma_async_device_unregister(&dma_dev->ddev);
  955. +
  956. + return 0;
  957. +}
  958. +
  959. +static struct platform_driver gdma_dma_driver = {
  960. + .probe = gdma_dma_probe,
  961. + .remove = gdma_dma_remove,
  962. + .driver = {
  963. + .name = "gdma-rt2880",
  964. + .of_match_table = gdma_of_match_table,
  965. + },
  966. +};
  967. +module_platform_driver(gdma_dma_driver);
  968. +
  969. +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  970. +MODULE_DESCRIPTION("Ralink/MTK DMA driver");
  971. +MODULE_LICENSE("GPL v2");
  972. --- a/include/linux/dmaengine.h
  973. +++ b/include/linux/dmaengine.h
  974. @@ -496,6 +496,7 @@ static inline void dma_set_unmap(struct
  975. struct dmaengine_unmap_data *
  976. dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
  977. void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
  978. +struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
  979. #else
  980. static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
  981. struct dmaengine_unmap_data *unmap)
  982. --- /dev/null
  983. +++ b/drivers/dma/mtk-hsdma.c
  984. @@ -0,0 +1,767 @@
  985. +/*
  986. + * Copyright (C) 2015, Michael Lee <igvtee@gmail.com>
  987. + * MTK HSDMA support
  988. + *
  989. + * This program is free software; you can redistribute it and/or modify it
  990. + * under the terms of the GNU General Public License as published by the
  991. + * Free Software Foundation; either version 2 of the License, or (at your
  992. + * option) any later version.
  993. + *
  994. + */
  995. +
  996. +#include <linux/dmaengine.h>
  997. +#include <linux/dma-mapping.h>
  998. +#include <linux/err.h>
  999. +#include <linux/init.h>
  1000. +#include <linux/list.h>
  1001. +#include <linux/module.h>
  1002. +#include <linux/platform_device.h>
  1003. +#include <linux/slab.h>
  1004. +#include <linux/spinlock.h>
  1005. +#include <linux/irq.h>
  1006. +#include <linux/of_dma.h>
  1007. +#include <linux/reset.h>
  1008. +#include <linux/of_device.h>
  1009. +
  1010. +#include "virt-dma.h"
  1011. +
  1012. +#define HSDMA_BASE_OFFSET 0x800
  1013. +
  1014. +#define HSDMA_REG_TX_BASE 0x00
  1015. +#define HSDMA_REG_TX_CNT 0x04
  1016. +#define HSDMA_REG_TX_CTX 0x08
  1017. +#define HSDMA_REG_TX_DTX 0x0c
  1018. +#define HSDMA_REG_RX_BASE 0x100
  1019. +#define HSDMA_REG_RX_CNT 0x104
  1020. +#define HSDMA_REG_RX_CRX 0x108
  1021. +#define HSDMA_REG_RX_DRX 0x10c
  1022. +#define HSDMA_REG_INFO 0x200
  1023. +#define HSDMA_REG_GLO_CFG 0x204
  1024. +#define HSDMA_REG_RST_CFG 0x208
  1025. +#define HSDMA_REG_DELAY_INT 0x20c
  1026. +#define HSDMA_REG_FREEQ_THRES 0x210
  1027. +#define HSDMA_REG_INT_STATUS 0x220
  1028. +#define HSDMA_REG_INT_MASK 0x228
  1029. +#define HSDMA_REG_SCH_Q01 0x280
  1030. +#define HSDMA_REG_SCH_Q23 0x284
  1031. +
  1032. +#define HSDMA_DESCS_MAX 0xfff
  1033. +#define HSDMA_DESCS_NUM 8
  1034. +#define HSDMA_DESCS_MASK (HSDMA_DESCS_NUM - 1)
  1035. +#define HSDMA_NEXT_DESC(x) (((x) + 1) & HSDMA_DESCS_MASK)
  1036. +
  1037. +/* HSDMA_REG_INFO */
  1038. +#define HSDMA_INFO_INDEX_MASK 0xf
  1039. +#define HSDMA_INFO_INDEX_SHIFT 24
  1040. +#define HSDMA_INFO_BASE_MASK 0xff
  1041. +#define HSDMA_INFO_BASE_SHIFT 16
  1042. +#define HSDMA_INFO_RX_MASK 0xff
  1043. +#define HSDMA_INFO_RX_SHIFT 8
  1044. +#define HSDMA_INFO_TX_MASK 0xff
  1045. +#define HSDMA_INFO_TX_SHIFT 0
  1046. +
  1047. +/* HSDMA_REG_GLO_CFG */
  1048. +#define HSDMA_GLO_TX_2B_OFFSET BIT(31)
  1049. +#define HSDMA_GLO_CLK_GATE BIT(30)
  1050. +#define HSDMA_GLO_BYTE_SWAP BIT(29)
  1051. +#define HSDMA_GLO_MULTI_DMA BIT(10)
  1052. +#define HSDMA_GLO_TWO_BUF BIT(9)
  1053. +#define HSDMA_GLO_32B_DESC BIT(8)
  1054. +#define HSDMA_GLO_BIG_ENDIAN BIT(7)
  1055. +#define HSDMA_GLO_TX_DONE BIT(6)
  1056. +#define HSDMA_GLO_BT_MASK 0x3
  1057. +#define HSDMA_GLO_BT_SHIFT 4
  1058. +#define HSDMA_GLO_RX_BUSY BIT(3)
  1059. +#define HSDMA_GLO_RX_DMA BIT(2)
  1060. +#define HSDMA_GLO_TX_BUSY BIT(1)
  1061. +#define HSDMA_GLO_TX_DMA BIT(0)
  1062. +
  1063. +#define HSDMA_BT_SIZE_16BYTES (0 << HSDMA_GLO_BT_SHIFT)
  1064. +#define HSDMA_BT_SIZE_32BYTES (1 << HSDMA_GLO_BT_SHIFT)
  1065. +#define HSDMA_BT_SIZE_64BYTES (2 << HSDMA_GLO_BT_SHIFT)
  1066. +#define HSDMA_BT_SIZE_128BYTES (3 << HSDMA_GLO_BT_SHIFT)
  1067. +
  1068. +#define HSDMA_GLO_DEFAULT (HSDMA_GLO_MULTI_DMA | \
  1069. + HSDMA_GLO_RX_DMA | HSDMA_GLO_TX_DMA | HSDMA_BT_SIZE_32BYTES)
  1070. +
  1071. +/* HSDMA_REG_RST_CFG */
  1072. +#define HSDMA_RST_RX_SHIFT 16
  1073. +#define HSDMA_RST_TX_SHIFT 0
  1074. +
  1075. +/* HSDMA_REG_DELAY_INT */
  1076. +#define HSDMA_DELAY_INT_EN BIT(15)
  1077. +#define HSDMA_DELAY_PEND_OFFSET 8
  1078. +#define HSDMA_DELAY_TIME_OFFSET 0
  1079. +#define HSDMA_DELAY_TX_OFFSET 16
  1080. +#define HSDMA_DELAY_RX_OFFSET 0
  1081. +
  1082. +#define HSDMA_DELAY_INIT(x) (HSDMA_DELAY_INT_EN | \
  1083. + ((x) << HSDMA_DELAY_PEND_OFFSET))
  1084. +#define HSDMA_DELAY(x) ((HSDMA_DELAY_INIT(x) << \
  1085. + HSDMA_DELAY_TX_OFFSET) | HSDMA_DELAY_INIT(x))
  1086. +
  1087. +/* HSDMA_REG_INT_STATUS */
  1088. +#define HSDMA_INT_DELAY_RX_COH BIT(31)
  1089. +#define HSDMA_INT_DELAY_RX_INT BIT(30)
  1090. +#define HSDMA_INT_DELAY_TX_COH BIT(29)
  1091. +#define HSDMA_INT_DELAY_TX_INT BIT(28)
  1092. +#define HSDMA_INT_RX_MASK 0x3
  1093. +#define HSDMA_INT_RX_SHIFT 16
  1094. +#define HSDMA_INT_RX_Q0 BIT(16)
  1095. +#define HSDMA_INT_TX_MASK 0xf
  1096. +#define HSDMA_INT_TX_SHIFT 0
  1097. +#define HSDMA_INT_TX_Q0 BIT(0)
  1098. +
  1099. +/* tx/rx dma desc flags */
  1100. +#define HSDMA_PLEN_MASK 0x3fff
  1101. +#define HSDMA_DESC_DONE BIT(31)
  1102. +#define HSDMA_DESC_LS0 BIT(30)
  1103. +#define HSDMA_DESC_PLEN0(_x) (((_x) & HSDMA_PLEN_MASK) << 16)
  1104. +#define HSDMA_DESC_TAG BIT(15)
  1105. +#define HSDMA_DESC_LS1 BIT(14)
  1106. +#define HSDMA_DESC_PLEN1(_x) ((_x) & HSDMA_PLEN_MASK)
  1107. +
  1108. +/* align 4 bytes */
  1109. +#define HSDMA_ALIGN_SIZE 3
  1110. +/* align size 128bytes */
  1111. +#define HSDMA_MAX_PLEN 0x3f80
  1112. +
  1113. +struct hsdma_desc {
  1114. + u32 addr0;
  1115. + u32 flags;
  1116. + u32 addr1;
  1117. + u32 unused;
  1118. +};
  1119. +
  1120. +struct mtk_hsdma_sg {
  1121. + dma_addr_t src_addr;
  1122. + dma_addr_t dst_addr;
  1123. + u32 len;
  1124. +};
  1125. +
  1126. +struct mtk_hsdma_desc {
  1127. + struct virt_dma_desc vdesc;
  1128. + unsigned int num_sgs;
  1129. + struct mtk_hsdma_sg sg[1];
  1130. +};
  1131. +
  1132. +struct mtk_hsdma_chan {
  1133. + struct virt_dma_chan vchan;
  1134. + unsigned int id;
  1135. + dma_addr_t desc_addr;
  1136. + int tx_idx;
  1137. + int rx_idx;
  1138. + struct hsdma_desc *tx_ring;
  1139. + struct hsdma_desc *rx_ring;
  1140. + struct mtk_hsdma_desc *desc;
  1141. + unsigned int next_sg;
  1142. +};
  1143. +
  1144. +struct mtk_hsdam_engine {
  1145. + struct dma_device ddev;
  1146. + struct device_dma_parameters dma_parms;
  1147. + void __iomem *base;
  1148. + struct tasklet_struct task;
  1149. + volatile unsigned long chan_issued;
  1150. +
  1151. + struct mtk_hsdma_chan chan[1];
  1152. +};
  1153. +
  1154. +static inline struct mtk_hsdam_engine *mtk_hsdma_chan_get_dev(
  1155. + struct mtk_hsdma_chan *chan)
  1156. +{
  1157. + return container_of(chan->vchan.chan.device, struct mtk_hsdam_engine,
  1158. + ddev);
  1159. +}
  1160. +
  1161. +static inline struct mtk_hsdma_chan *to_mtk_hsdma_chan(struct dma_chan *c)
  1162. +{
  1163. + return container_of(c, struct mtk_hsdma_chan, vchan.chan);
  1164. +}
  1165. +
  1166. +static inline struct mtk_hsdma_desc *to_mtk_hsdma_desc(
  1167. + struct virt_dma_desc *vdesc)
  1168. +{
  1169. + return container_of(vdesc, struct mtk_hsdma_desc, vdesc);
  1170. +}
  1171. +
  1172. +static inline u32 mtk_hsdma_read(struct mtk_hsdam_engine *hsdma, u32 reg)
  1173. +{
  1174. + return readl(hsdma->base + reg);
  1175. +}
  1176. +
  1177. +static inline void mtk_hsdma_write(struct mtk_hsdam_engine *hsdma,
  1178. + unsigned reg, u32 val)
  1179. +{
  1180. + writel(val, hsdma->base + reg);
  1181. +}
  1182. +
  1183. +static void mtk_hsdma_reset_chan(struct mtk_hsdam_engine *hsdma,
  1184. + struct mtk_hsdma_chan *chan)
  1185. +{
  1186. + chan->tx_idx = 0;
  1187. + chan->rx_idx = HSDMA_DESCS_NUM - 1;
  1188. +
  1189. + mtk_hsdma_write(hsdma, HSDMA_REG_TX_CTX, chan->tx_idx);
  1190. + mtk_hsdma_write(hsdma, HSDMA_REG_RX_CRX, chan->rx_idx);
  1191. +
  1192. + mtk_hsdma_write(hsdma, HSDMA_REG_RST_CFG,
  1193. + 0x1 << (chan->id + HSDMA_RST_TX_SHIFT));
  1194. + mtk_hsdma_write(hsdma, HSDMA_REG_RST_CFG,
  1195. + 0x1 << (chan->id + HSDMA_RST_RX_SHIFT));
  1196. +}
  1197. +
  1198. +static void hsdma_dump_reg(struct mtk_hsdam_engine *hsdma)
  1199. +{
  1200. + dev_dbg(hsdma->ddev.dev, "tbase %08x, tcnt %08x, " \
  1201. + "tctx %08x, tdtx: %08x, rbase %08x, " \
  1202. + "rcnt %08x, rctx %08x, rdtx %08x\n",
  1203. + mtk_hsdma_read(hsdma, HSDMA_REG_TX_BASE),
  1204. + mtk_hsdma_read(hsdma, HSDMA_REG_TX_CNT),
  1205. + mtk_hsdma_read(hsdma, HSDMA_REG_TX_CTX),
  1206. + mtk_hsdma_read(hsdma, HSDMA_REG_TX_DTX),
  1207. + mtk_hsdma_read(hsdma, HSDMA_REG_RX_BASE),
  1208. + mtk_hsdma_read(hsdma, HSDMA_REG_RX_CNT),
  1209. + mtk_hsdma_read(hsdma, HSDMA_REG_RX_CRX),
  1210. + mtk_hsdma_read(hsdma, HSDMA_REG_RX_DRX));
  1211. +
  1212. + dev_dbg(hsdma->ddev.dev, "info %08x, glo %08x, delay %08x, " \
  1213. + "intr_stat %08x, intr_mask %08x\n",
  1214. + mtk_hsdma_read(hsdma, HSDMA_REG_INFO),
  1215. + mtk_hsdma_read(hsdma, HSDMA_REG_GLO_CFG),
  1216. + mtk_hsdma_read(hsdma, HSDMA_REG_DELAY_INT),
  1217. + mtk_hsdma_read(hsdma, HSDMA_REG_INT_STATUS),
  1218. + mtk_hsdma_read(hsdma, HSDMA_REG_INT_MASK));
  1219. +}
  1220. +
  1221. +static void hsdma_dump_desc(struct mtk_hsdam_engine *hsdma,
  1222. + struct mtk_hsdma_chan *chan)
  1223. +{
  1224. + struct hsdma_desc *tx_desc;
  1225. + struct hsdma_desc *rx_desc;
  1226. + int i;
  1227. +
  1228. + dev_dbg(hsdma->ddev.dev, "tx idx: %d, rx idx: %d\n",
  1229. + chan->tx_idx, chan->rx_idx);
  1230. +
  1231. + for (i = 0; i < HSDMA_DESCS_NUM; i++) {
  1232. + tx_desc = &chan->tx_ring[i];
  1233. + rx_desc = &chan->rx_ring[i];
  1234. +
  1235. + dev_dbg(hsdma->ddev.dev, "%d tx addr0: %08x, flags %08x, " \
  1236. + "tx addr1: %08x, rx addr0 %08x, flags %08x\n",
  1237. + i, tx_desc->addr0, tx_desc->flags, \
  1238. + tx_desc->addr1, rx_desc->addr0, rx_desc->flags);
  1239. + }
  1240. +}
  1241. +
  1242. +static void mtk_hsdma_reset(struct mtk_hsdam_engine *hsdma,
  1243. + struct mtk_hsdma_chan *chan)
  1244. +{
  1245. + int i;
  1246. +
  1247. + /* disable dma */
  1248. + mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, 0);
  1249. +
  1250. + /* disable intr */
  1251. + mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, 0);
  1252. +
  1253. + /* init desc value */
  1254. + for (i = 0; i < HSDMA_DESCS_NUM; i++) {
  1255. + chan->tx_ring[i].addr0 = 0;
  1256. + chan->tx_ring[i].flags = HSDMA_DESC_LS0 |
  1257. + HSDMA_DESC_DONE;
  1258. + }
  1259. + for (i = 0; i < HSDMA_DESCS_NUM; i++) {
  1260. + chan->rx_ring[i].addr0 = 0;
  1261. + chan->rx_ring[i].flags = 0;
  1262. + }
  1263. +
  1264. + /* reset */
  1265. + mtk_hsdma_reset_chan(hsdma, chan);
  1266. +
  1267. + /* enable intr */
  1268. + mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, HSDMA_INT_RX_Q0);
  1269. +
  1270. + /* enable dma */
  1271. + mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, HSDMA_GLO_DEFAULT);
  1272. +}
  1273. +
  1274. +static int mtk_hsdma_terminate_all(struct dma_chan *c)
  1275. +{
  1276. + struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
  1277. + struct mtk_hsdam_engine *hsdma = mtk_hsdma_chan_get_dev(chan);
  1278. + unsigned long timeout;
  1279. + LIST_HEAD(head);
  1280. +
  1281. + spin_lock_bh(&chan->vchan.lock);
  1282. + chan->desc = NULL;
  1283. + clear_bit(chan->id, &hsdma->chan_issued);
  1284. + vchan_get_all_descriptors(&chan->vchan, &head);
  1285. + spin_unlock_bh(&chan->vchan.lock);
  1286. +
  1287. + vchan_dma_desc_free_list(&chan->vchan, &head);
  1288. +
  1289. + /* wait dma transfer complete */
  1290. + timeout = jiffies + msecs_to_jiffies(2000);
  1291. + while (mtk_hsdma_read(hsdma, HSDMA_REG_GLO_CFG) &
  1292. + (HSDMA_GLO_RX_BUSY | HSDMA_GLO_TX_BUSY)) {
  1293. + if (time_after_eq(jiffies, timeout)) {
  1294. + hsdma_dump_desc(hsdma, chan);
  1295. + mtk_hsdma_reset(hsdma, chan);
  1296. + dev_err(hsdma->ddev.dev, "timeout, reset it\n");
  1297. + break;
  1298. + }
  1299. + cpu_relax();
  1300. + }
  1301. +
  1302. + return 0;
  1303. +}
  1304. +
  1305. +static int mtk_hsdma_start_transfer(struct mtk_hsdam_engine *hsdma,
  1306. + struct mtk_hsdma_chan *chan)
  1307. +{
  1308. + dma_addr_t src, dst;
  1309. + size_t len, tlen;
  1310. + struct hsdma_desc *tx_desc, *rx_desc;
  1311. + struct mtk_hsdma_sg *sg;
  1312. + unsigned int i;
  1313. + int rx_idx;
  1314. +
  1315. + sg = &chan->desc->sg[0];
  1316. + len = sg->len;
  1317. + chan->desc->num_sgs = DIV_ROUND_UP(len, HSDMA_MAX_PLEN);
  1318. +
  1319. + /* tx desc */
  1320. + src = sg->src_addr;
  1321. + for (i = 0; i < chan->desc->num_sgs; i++) {
  1322. + if (len > HSDMA_MAX_PLEN)
  1323. + tlen = HSDMA_MAX_PLEN;
  1324. + else
  1325. + tlen = len;
  1326. +
  1327. + if (i & 0x1) {
  1328. + tx_desc->addr1 = src;
  1329. + tx_desc->flags |= HSDMA_DESC_PLEN1(tlen);
  1330. + } else {
  1331. + tx_desc = &chan->tx_ring[chan->tx_idx];
  1332. + tx_desc->addr0 = src;
  1333. + tx_desc->flags = HSDMA_DESC_PLEN0(tlen);
  1334. +
  1335. + /* update index */
  1336. + chan->tx_idx = HSDMA_NEXT_DESC(chan->tx_idx);
  1337. + }
  1338. +
  1339. + src += tlen;
  1340. + len -= tlen;
  1341. + }
  1342. + if (i & 0x1)
  1343. + tx_desc->flags |= HSDMA_DESC_LS0;
  1344. + else
  1345. + tx_desc->flags |= HSDMA_DESC_LS1;
  1346. +
  1347. + /* rx desc */
  1348. + rx_idx = HSDMA_NEXT_DESC(chan->rx_idx);
  1349. + len = sg->len;
  1350. + dst = sg->dst_addr;
  1351. + for (i = 0; i < chan->desc->num_sgs; i++) {
  1352. + rx_desc = &chan->rx_ring[rx_idx];
  1353. + if (len > HSDMA_MAX_PLEN)
  1354. + tlen = HSDMA_MAX_PLEN;
  1355. + else
  1356. + tlen = len;
  1357. +
  1358. + rx_desc->addr0 = dst;
  1359. + rx_desc->flags = HSDMA_DESC_PLEN0(tlen);
  1360. +
  1361. + dst += tlen;
  1362. + len -= tlen;
  1363. +
  1364. + /* update index */
  1365. + rx_idx = HSDMA_NEXT_DESC(rx_idx);
  1366. + }
  1367. +
  1368. + /* make sure desc and index all up to date */
  1369. + wmb();
  1370. + mtk_hsdma_write(hsdma, HSDMA_REG_TX_CTX, chan->tx_idx);
  1371. +
  1372. + return 0;
  1373. +}
  1374. +
  1375. +static int gdma_next_desc(struct mtk_hsdma_chan *chan)
  1376. +{
  1377. + struct virt_dma_desc *vdesc;
  1378. +
  1379. + vdesc = vchan_next_desc(&chan->vchan);
  1380. + if (!vdesc) {
  1381. + chan->desc = NULL;
  1382. + return 0;
  1383. + }
  1384. + chan->desc = to_mtk_hsdma_desc(vdesc);
  1385. + chan->next_sg = 0;
  1386. +
  1387. + return 1;
  1388. +}
  1389. +
  1390. +static void mtk_hsdma_chan_done(struct mtk_hsdam_engine *hsdma,
  1391. + struct mtk_hsdma_chan *chan)
  1392. +{
  1393. + struct mtk_hsdma_desc *desc;
  1394. + int chan_issued;
  1395. +
  1396. + chan_issued = 0;
  1397. + spin_lock_bh(&chan->vchan.lock);
  1398. + desc = chan->desc;
  1399. + if (likely(desc)) {
  1400. + if (chan->next_sg == desc->num_sgs) {
  1401. + list_del(&desc->vdesc.node);
  1402. + vchan_cookie_complete(&desc->vdesc);
  1403. + chan_issued = gdma_next_desc(chan);
  1404. + }
  1405. + } else
  1406. + dev_dbg(hsdma->ddev.dev, "no desc to complete\n");
  1407. +
  1408. + if (chan_issued)
  1409. + set_bit(chan->id, &hsdma->chan_issued);
  1410. + spin_unlock_bh(&chan->vchan.lock);
  1411. +}
  1412. +
  1413. +static irqreturn_t mtk_hsdma_irq(int irq, void *devid)
  1414. +{
  1415. + struct mtk_hsdam_engine *hsdma = devid;
  1416. + u32 status;
  1417. +
  1418. + status = mtk_hsdma_read(hsdma, HSDMA_REG_INT_STATUS);
  1419. + if (unlikely(!status))
  1420. + return IRQ_NONE;
  1421. +
  1422. + if (likely(status & HSDMA_INT_RX_Q0))
  1423. + tasklet_schedule(&hsdma->task);
  1424. + else
  1425. + dev_dbg(hsdma->ddev.dev, "unhandle irq status %08x\n",
  1426. + status);
  1427. + /* clean intr bits */
  1428. + mtk_hsdma_write(hsdma, HSDMA_REG_INT_STATUS, status);
  1429. +
  1430. + return IRQ_HANDLED;
  1431. +}
  1432. +
  1433. +static void mtk_hsdma_issue_pending(struct dma_chan *c)
  1434. +{
  1435. + struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
  1436. + struct mtk_hsdam_engine *hsdma = mtk_hsdma_chan_get_dev(chan);
  1437. +
  1438. + spin_lock_bh(&chan->vchan.lock);
  1439. + if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
  1440. + if (gdma_next_desc(chan)) {
  1441. + set_bit(chan->id, &hsdma->chan_issued);
  1442. + tasklet_schedule(&hsdma->task);
  1443. + } else
  1444. + dev_dbg(hsdma->ddev.dev, "no desc to issue\n");
  1445. + }
  1446. + spin_unlock_bh(&chan->vchan.lock);
  1447. +}
  1448. +
  1449. +static struct dma_async_tx_descriptor * mtk_hsdma_prep_dma_memcpy(
  1450. + struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
  1451. + size_t len, unsigned long flags)
  1452. +{
  1453. + struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
  1454. + struct mtk_hsdma_desc *desc;
  1455. +
  1456. + if (len <= 0)
  1457. + return NULL;
  1458. +
  1459. + desc = kzalloc(sizeof(struct mtk_hsdma_desc), GFP_ATOMIC);
  1460. + if (!desc) {
  1461. + dev_err(c->device->dev, "alloc memcpy decs error\n");
  1462. + return NULL;
  1463. + }
  1464. +
  1465. + desc->sg[0].src_addr = src;
  1466. + desc->sg[0].dst_addr = dest;
  1467. + desc->sg[0].len = len;
  1468. +
  1469. + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
  1470. +}
  1471. +
  1472. +static enum dma_status mtk_hsdma_tx_status(struct dma_chan *c,
  1473. + dma_cookie_t cookie, struct dma_tx_state *state)
  1474. +{
  1475. + return dma_cookie_status(c, cookie, state);
  1476. +}
  1477. +
  1478. +static void mtk_hsdma_free_chan_resources(struct dma_chan *c)
  1479. +{
  1480. + vchan_free_chan_resources(to_virt_chan(c));
  1481. +}
  1482. +
  1483. +static void mtk_hsdma_desc_free(struct virt_dma_desc *vdesc)
  1484. +{
  1485. + kfree(container_of(vdesc, struct mtk_hsdma_desc, vdesc));
  1486. +}
  1487. +
  1488. +static void mtk_hsdma_tx(struct mtk_hsdam_engine *hsdma)
  1489. +{
  1490. + struct mtk_hsdma_chan *chan;
  1491. +
  1492. + if (test_and_clear_bit(0, &hsdma->chan_issued)) {
  1493. + chan = &hsdma->chan[0];
  1494. + if (chan->desc) {
  1495. + mtk_hsdma_start_transfer(hsdma, chan);
  1496. + } else
  1497. + dev_dbg(hsdma->ddev.dev,"chan 0 no desc to issue\n");
  1498. + }
  1499. +}
  1500. +
  1501. +static void mtk_hsdma_rx(struct mtk_hsdam_engine *hsdma)
  1502. +{
  1503. + struct mtk_hsdma_chan *chan;
  1504. + int next_idx, drx_idx, cnt;
  1505. +
  1506. + chan = &hsdma->chan[0];
  1507. + next_idx = HSDMA_NEXT_DESC(chan->rx_idx);
  1508. + drx_idx = mtk_hsdma_read(hsdma, HSDMA_REG_RX_DRX);
  1509. +
  1510. + cnt = (drx_idx - next_idx) & HSDMA_DESCS_MASK;
  1511. + if (!cnt)
  1512. + return;
  1513. +
  1514. + chan->next_sg += cnt;
  1515. + chan->rx_idx = (chan->rx_idx + cnt) & HSDMA_DESCS_MASK;
  1516. +
  1517. + /* update rx crx */
  1518. + wmb();
  1519. + mtk_hsdma_write(hsdma, HSDMA_REG_RX_CRX, chan->rx_idx);
  1520. +
  1521. + mtk_hsdma_chan_done(hsdma, chan);
  1522. +}
  1523. +
  1524. +static void mtk_hsdma_tasklet(unsigned long arg)
  1525. +{
  1526. + struct mtk_hsdam_engine *hsdma = (struct mtk_hsdam_engine *)arg;
  1527. +
  1528. + mtk_hsdma_rx(hsdma);
  1529. + mtk_hsdma_tx(hsdma);
  1530. +}
  1531. +
  1532. +static int mtk_hsdam_alloc_desc(struct mtk_hsdam_engine *hsdma,
  1533. + struct mtk_hsdma_chan *chan)
  1534. +{
  1535. + int i;
  1536. +
  1537. + chan->tx_ring = dma_alloc_coherent(hsdma->ddev.dev,
  1538. + 2 * HSDMA_DESCS_NUM * sizeof(*chan->tx_ring),
  1539. + &chan->desc_addr, GFP_ATOMIC | __GFP_ZERO);
  1540. + if (!chan->tx_ring)
  1541. + goto no_mem;
  1542. +
  1543. + chan->rx_ring = &chan->tx_ring[HSDMA_DESCS_NUM];
  1544. +
  1545. + /* init tx ring value */
  1546. + for (i = 0; i < HSDMA_DESCS_NUM; i++)
  1547. + chan->tx_ring[i].flags = HSDMA_DESC_LS0 | HSDMA_DESC_DONE;
  1548. +
  1549. + return 0;
  1550. +no_mem:
  1551. + return -ENOMEM;
  1552. +}
  1553. +
  1554. +static void mtk_hsdam_free_desc(struct mtk_hsdam_engine *hsdma,
  1555. + struct mtk_hsdma_chan *chan)
  1556. +{
  1557. + if (chan->tx_ring) {
  1558. + dma_free_coherent(hsdma->ddev.dev,
  1559. + 2 * HSDMA_DESCS_NUM * sizeof(*chan->tx_ring),
  1560. + chan->tx_ring, chan->desc_addr);
  1561. + chan->tx_ring = NULL;
  1562. + chan->rx_ring = NULL;
  1563. + }
  1564. +}
  1565. +
  1566. +static int mtk_hsdma_init(struct mtk_hsdam_engine *hsdma)
  1567. +{
  1568. + struct mtk_hsdma_chan *chan;
  1569. + int ret;
  1570. + u32 reg;
  1571. +
  1572. + /* init desc */
  1573. + chan = &hsdma->chan[0];
  1574. + ret = mtk_hsdam_alloc_desc(hsdma, chan);
  1575. + if (ret)
  1576. + return ret;
  1577. +
  1578. + /* tx */
  1579. + mtk_hsdma_write(hsdma, HSDMA_REG_TX_BASE, chan->desc_addr);
  1580. + mtk_hsdma_write(hsdma, HSDMA_REG_TX_CNT, HSDMA_DESCS_NUM);
  1581. + /* rx */
  1582. + mtk_hsdma_write(hsdma, HSDMA_REG_RX_BASE, chan->desc_addr +
  1583. + (sizeof(struct hsdma_desc) * HSDMA_DESCS_NUM));
  1584. + mtk_hsdma_write(hsdma, HSDMA_REG_RX_CNT, HSDMA_DESCS_NUM);
  1585. + /* reset */
  1586. + mtk_hsdma_reset_chan(hsdma, chan);
  1587. +
  1588. + /* enable rx intr */
  1589. + mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, HSDMA_INT_RX_Q0);
  1590. +
  1591. + /* enable dma */
  1592. + mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, HSDMA_GLO_DEFAULT);
  1593. +
  1594. + /* hardware info */
  1595. + reg = mtk_hsdma_read(hsdma, HSDMA_REG_INFO);
  1596. + dev_info(hsdma->ddev.dev, "rx: %d, tx: %d\n",
  1597. + (reg >> HSDMA_INFO_RX_SHIFT) & HSDMA_INFO_RX_MASK,
  1598. + (reg >> HSDMA_INFO_TX_SHIFT) & HSDMA_INFO_TX_MASK);
  1599. +
  1600. + hsdma_dump_reg(hsdma);
  1601. +
  1602. + return ret;
  1603. +}
  1604. +
  1605. +static void mtk_hsdma_uninit(struct mtk_hsdam_engine *hsdma)
  1606. +{
  1607. + struct mtk_hsdma_chan *chan;
  1608. +
  1609. + /* disable dma */
  1610. + mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, 0);
  1611. +
  1612. + /* disable intr */
  1613. + mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, 0);
  1614. +
  1615. + /* free desc */
  1616. + chan = &hsdma->chan[0];
  1617. + mtk_hsdam_free_desc(hsdma, chan);
  1618. +
  1619. + /* tx */
  1620. + mtk_hsdma_write(hsdma, HSDMA_REG_TX_BASE, 0);
  1621. + mtk_hsdma_write(hsdma, HSDMA_REG_TX_CNT, 0);
  1622. + /* rx */
  1623. + mtk_hsdma_write(hsdma, HSDMA_REG_RX_BASE, 0);
  1624. + mtk_hsdma_write(hsdma, HSDMA_REG_RX_CNT, 0);
  1625. + /* reset */
  1626. + mtk_hsdma_reset_chan(hsdma, chan);
  1627. +}
  1628. +
  1629. +static const struct of_device_id mtk_hsdma_of_match[] = {
  1630. + { .compatible = "mediatek,mt7621-hsdma" },
  1631. + { },
  1632. +};
  1633. +
  1634. +static int mtk_hsdma_probe(struct platform_device *pdev)
  1635. +{
  1636. + const struct of_device_id *match;
  1637. + struct mtk_hsdma_chan *chan;
  1638. + struct mtk_hsdam_engine *hsdma;
  1639. + struct dma_device *dd;
  1640. + struct resource *res;
  1641. + int ret;
  1642. + int irq;
  1643. + void __iomem *base;
  1644. +
  1645. + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
  1646. + if (ret)
  1647. + return ret;
  1648. +
  1649. + match = of_match_device(mtk_hsdma_of_match, &pdev->dev);
  1650. + if (!match)
  1651. + return -EINVAL;
  1652. +
  1653. + hsdma = devm_kzalloc(&pdev->dev, sizeof(*hsdma), GFP_KERNEL);
  1654. + if (!hsdma) {
  1655. + dev_err(&pdev->dev, "alloc dma device failed\n");
  1656. + return -EINVAL;
  1657. + }
  1658. +
  1659. + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1660. + base = devm_ioremap_resource(&pdev->dev, res);
  1661. + if (IS_ERR(base))
  1662. + return PTR_ERR(base);
  1663. + hsdma->base = base + HSDMA_BASE_OFFSET;
  1664. + tasklet_init(&hsdma->task, mtk_hsdma_tasklet, (unsigned long)hsdma);
  1665. +
  1666. + irq = platform_get_irq(pdev, 0);
  1667. + if (irq < 0) {
  1668. + dev_err(&pdev->dev, "failed to get irq\n");
  1669. + return -EINVAL;
  1670. + }
  1671. + ret = devm_request_irq(&pdev->dev, irq, mtk_hsdma_irq,
  1672. + 0, dev_name(&pdev->dev), hsdma);
  1673. + if (ret) {
  1674. + dev_err(&pdev->dev, "failed to request irq\n");
  1675. + return ret;
  1676. + }
  1677. +
  1678. + device_reset(&pdev->dev);
  1679. +
  1680. + dd = &hsdma->ddev;
  1681. + dma_cap_set(DMA_MEMCPY, dd->cap_mask);
  1682. + dd->copy_align = HSDMA_ALIGN_SIZE;
  1683. + dd->device_free_chan_resources = mtk_hsdma_free_chan_resources;
  1684. + dd->device_prep_dma_memcpy = mtk_hsdma_prep_dma_memcpy;
  1685. + dd->device_terminate_all = mtk_hsdma_terminate_all;
  1686. + dd->device_tx_status = mtk_hsdma_tx_status;
  1687. + dd->device_issue_pending = mtk_hsdma_issue_pending;
  1688. + dd->dev = &pdev->dev;
  1689. + dd->dev->dma_parms = &hsdma->dma_parms;
  1690. + dma_set_max_seg_size(dd->dev, HSDMA_MAX_PLEN);
  1691. + INIT_LIST_HEAD(&dd->channels);
  1692. +
  1693. + chan = &hsdma->chan[0];
  1694. + chan->id = 0;
  1695. + chan->vchan.desc_free = mtk_hsdma_desc_free;
  1696. + vchan_init(&chan->vchan, dd);
  1697. +
  1698. + /* init hardware */
  1699. + ret = mtk_hsdma_init(hsdma);
  1700. + if (ret) {
  1701. + dev_err(&pdev->dev, "failed to alloc ring descs\n");
  1702. + return ret;
  1703. + }
  1704. +
  1705. + ret = dma_async_device_register(dd);
  1706. + if (ret) {
  1707. + dev_err(&pdev->dev, "failed to register dma device\n");
  1708. + return ret;
  1709. + }
  1710. +
  1711. + ret = of_dma_controller_register(pdev->dev.of_node,
  1712. + of_dma_xlate_by_chan_id, hsdma);
  1713. + if (ret) {
  1714. + dev_err(&pdev->dev, "failed to register of dma controller\n");
  1715. + goto err_unregister;
  1716. + }
  1717. +
  1718. + platform_set_drvdata(pdev, hsdma);
  1719. +
  1720. + return 0;
  1721. +
  1722. +err_unregister:
  1723. + dma_async_device_unregister(dd);
  1724. + return ret;
  1725. +}
  1726. +
  1727. +static int mtk_hsdma_remove(struct platform_device *pdev)
  1728. +{
  1729. + struct mtk_hsdam_engine *hsdma = platform_get_drvdata(pdev);
  1730. +
  1731. + mtk_hsdma_uninit(hsdma);
  1732. +
  1733. + of_dma_controller_free(pdev->dev.of_node);
  1734. + dma_async_device_unregister(&hsdma->ddev);
  1735. +
  1736. + return 0;
  1737. +}
  1738. +
  1739. +static struct platform_driver mtk_hsdma_driver = {
  1740. + .probe = mtk_hsdma_probe,
  1741. + .remove = mtk_hsdma_remove,
  1742. + .driver = {
  1743. + .name = "hsdma-mt7621",
  1744. + .of_match_table = mtk_hsdma_of_match,
  1745. + },
  1746. +};
  1747. +module_platform_driver(mtk_hsdma_driver);
  1748. +
  1749. +MODULE_AUTHOR("Michael Lee <igvtee@gmail.com>");
  1750. +MODULE_DESCRIPTION("MTK HSDMA driver");
  1751. +MODULE_LICENSE("GPL v2");