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0048-asoc-add-mt7620-support.patch 27 KB

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  1. From 7f29222b1731e8182ba94a331531dec18865a1e4 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Sun, 27 Jul 2014 09:31:47 +0100
  4. Subject: [PATCH 48/53] asoc: add mt7620 support
  5. Signed-off-by: John Crispin <blogic@openwrt.org>
  6. ---
  7. arch/mips/ralink/of.c | 2 +
  8. sound/soc/Kconfig | 1 +
  9. sound/soc/Makefile | 1 +
  10. sound/soc/ralink/Kconfig | 15 ++
  11. sound/soc/ralink/Makefile | 11 +
  12. sound/soc/ralink/mt7620-i2s.c | 436 ++++++++++++++++++++++++++++++++++++++
  13. sound/soc/ralink/mt7620-wm8960.c | 233 ++++++++++++++++++++
  14. 7 files changed, 699 insertions(+)
  15. create mode 100644 sound/soc/ralink/Kconfig
  16. create mode 100644 sound/soc/ralink/Makefile
  17. create mode 100644 sound/soc/ralink/mt7620-i2s.c
  18. create mode 100644 sound/soc/ralink/mt7620-wm8960.c
  19. --- a/arch/mips/ralink/of.c
  20. +++ b/arch/mips/ralink/of.c
  21. @@ -15,6 +15,7 @@
  22. #include <linux/of_fdt.h>
  23. #include <linux/kernel.h>
  24. #include <linux/bootmem.h>
  25. +#include <linux/module.h>
  26. #include <linux/of_platform.h>
  27. #include <linux/of_address.h>
  28. @@ -26,6 +27,7 @@
  29. #include "common.h"
  30. __iomem void *rt_sysc_membase;
  31. +EXPORT_SYMBOL(rt_sysc_membase);
  32. __iomem void *rt_memc_membase;
  33. __iomem void *plat_of_remap_node(const char *node)
  34. --- a/sound/soc/Kconfig
  35. +++ b/sound/soc/Kconfig
  36. @@ -56,6 +56,7 @@ source "sound/soc/mxs/Kconfig"
  37. source "sound/soc/pxa/Kconfig"
  38. source "sound/soc/qcom/Kconfig"
  39. source "sound/soc/rockchip/Kconfig"
  40. +source "sound/soc/ralink/Kconfig"
  41. source "sound/soc/samsung/Kconfig"
  42. source "sound/soc/sh/Kconfig"
  43. source "sound/soc/sirf/Kconfig"
  44. --- a/sound/soc/Makefile
  45. +++ b/sound/soc/Makefile
  46. @@ -36,6 +36,7 @@ obj-$(CONFIG_SND_SOC) += kirkwood/
  47. obj-$(CONFIG_SND_SOC) += pxa/
  48. obj-$(CONFIG_SND_SOC) += qcom/
  49. obj-$(CONFIG_SND_SOC) += rockchip/
  50. +obj-$(CONFIG_SND_SOC) += ralink/
  51. obj-$(CONFIG_SND_SOC) += samsung/
  52. obj-$(CONFIG_SND_SOC) += sh/
  53. obj-$(CONFIG_SND_SOC) += sirf/
  54. --- /dev/null
  55. +++ b/sound/soc/ralink/Kconfig
  56. @@ -0,0 +1,8 @@
  57. +config SND_RALINK_SOC_I2S
  58. + depends on RALINK && SND_SOC && !SOC_RT288X
  59. + select SND_SOC_GENERIC_DMAENGINE_PCM
  60. + select REGMAP_MMIO
  61. + tristate "SoC Audio (I2S protocol) for Ralink SoC"
  62. + help
  63. + Say Y if you want to use I2S protocol and I2S codec on Ralink/MediaTek
  64. + based boards.
  65. --- /dev/null
  66. +++ b/sound/soc/ralink/Makefile
  67. @@ -0,0 +1,6 @@
  68. +#
  69. +# Ralink/MediaTek Platform Support
  70. +#
  71. +snd-soc-ralink-i2s-objs := ralink-i2s.o
  72. +
  73. +obj-$(CONFIG_SND_RALINK_SOC_I2S) += snd-soc-ralink-i2s.o
  74. --- /dev/null
  75. +++ b/sound/soc/ralink/ralink-i2s.c
  76. @@ -0,0 +1,965 @@
  77. +/*
  78. + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  79. + * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
  80. + *
  81. + * This program is free software; you can redistribute it and/or modify it
  82. + * under the terms of the GNU General Public License as published by the
  83. + * Free Software Foundation; either version 2 of the License, or (at your
  84. + * option) any later version.
  85. + *
  86. + * You should have received a copy of the GNU General Public License along
  87. + * with this program; if not, write to the Free Software Foundation, Inc.,
  88. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  89. + *
  90. + */
  91. +
  92. +#include <linux/module.h>
  93. +#include <linux/platform_device.h>
  94. +#include <linux/clk.h>
  95. +#include <linux/regmap.h>
  96. +#include <linux/reset.h>
  97. +#include <linux/debugfs.h>
  98. +#include <linux/of_device.h>
  99. +#include <sound/pcm_params.h>
  100. +#include <sound/dmaengine_pcm.h>
  101. +
  102. +#include <asm/mach-ralink/ralink_regs.h>
  103. +
  104. +#define DRV_NAME "ralink-i2s"
  105. +
  106. +#define I2S_REG_CFG0 0x00
  107. +#define I2S_REG_INT_STATUS 0x04
  108. +#define I2S_REG_INT_EN 0x08
  109. +#define I2S_REG_FF_STATUS 0x0c
  110. +#define I2S_REG_WREG 0x10
  111. +#define I2S_REG_RREG 0x14
  112. +#define I2S_REG_CFG1 0x18
  113. +#define I2S_REG_DIVCMP 0x20
  114. +#define I2S_REG_DIVINT 0x24
  115. +
  116. +/* I2S_REG_CFG0 */
  117. +#define I2S_REG_CFG0_EN BIT(31)
  118. +#define I2S_REG_CFG0_DMA_EN BIT(30)
  119. +#define I2S_REG_CFG0_BYTE_SWAP BIT(28)
  120. +#define I2S_REG_CFG0_TX_EN BIT(24)
  121. +#define I2S_REG_CFG0_RX_EN BIT(20)
  122. +#define I2S_REG_CFG0_SLAVE BIT(16)
  123. +#define I2S_REG_CFG0_RX_THRES 12
  124. +#define I2S_REG_CFG0_TX_THRES 4
  125. +#define I2S_REG_CFG0_THRES_MASK (0xf << I2S_REG_CFG0_RX_THRES) | \
  126. + (4 << I2S_REG_CFG0_TX_THRES)
  127. +#define I2S_REG_CFG0_DFT_THRES (4 << I2S_REG_CFG0_RX_THRES) | \
  128. + (4 << I2S_REG_CFG0_TX_THRES)
  129. +/* RT305x */
  130. +#define I2S_REG_CFG0_CLK_DIS BIT(8)
  131. +#define I2S_REG_CFG0_TXCH_SWAP BIT(3)
  132. +#define I2S_REG_CFG0_TXCH1_OFF BIT(2)
  133. +#define I2S_REG_CFG0_TXCH0_OFF BIT(1)
  134. +#define I2S_REG_CFG0_SLAVE_EN BIT(0)
  135. +/* RT3883 */
  136. +#define I2S_REG_CFG0_RXCH_SWAP BIT(11)
  137. +#define I2S_REG_CFG0_RXCH1_OFF BIT(10)
  138. +#define I2S_REG_CFG0_RXCH0_OFF BIT(9)
  139. +#define I2S_REG_CFG0_WS_INV BIT(0)
  140. +/* MT7628 */
  141. +#define I2S_REG_CFG0_FMT_LE BIT(29)
  142. +#define I2S_REG_CFG0_SYS_BE BIT(28)
  143. +#define I2S_REG_CFG0_NORM_24 BIT(18)
  144. +#define I2S_REG_CFG0_DATA_24 BIT(17)
  145. +
  146. +/* I2S_REG_INT_STATUS */
  147. +#define I2S_REG_INT_RX_FAULT BIT(7)
  148. +#define I2S_REG_INT_RX_OVRUN BIT(6)
  149. +#define I2S_REG_INT_RX_UNRUN BIT(5)
  150. +#define I2S_REG_INT_RX_THRES BIT(4)
  151. +#define I2S_REG_INT_TX_FAULT BIT(3)
  152. +#define I2S_REG_INT_TX_OVRUN BIT(2)
  153. +#define I2S_REG_INT_TX_UNRUN BIT(1)
  154. +#define I2S_REG_INT_TX_THRES BIT(0)
  155. +#define I2S_REG_INT_TX_MASK 0xf
  156. +#define I2S_REG_INT_RX_MASK 0xf0
  157. +
  158. +/* I2S_REG_INT_STATUS */
  159. +#define I2S_RX_AVCNT(x) ((x >> 4) & 0xf)
  160. +#define I2S_TX_AVCNT(x) (x & 0xf)
  161. +/* MT7628 */
  162. +#define MT7628_I2S_RX_AVCNT(x) ((x >> 8) & 0x1f)
  163. +#define MT7628_I2S_TX_AVCNT(x) (x & 0x1f)
  164. +
  165. +/* I2S_REG_CFG1 */
  166. +#define I2S_REG_CFG1_LBK BIT(31)
  167. +#define I2S_REG_CFG1_EXTLBK BIT(30)
  168. +/* RT3883 */
  169. +#define I2S_REG_CFG1_LEFT_J BIT(0)
  170. +#define I2S_REG_CFG1_RIGHT_J BIT(1)
  171. +#define I2S_REG_CFG1_FMT_MASK 0x3
  172. +
  173. +/* I2S_REG_DIVCMP */
  174. +#define I2S_REG_DIVCMP_CLKEN BIT(31)
  175. +#define I2S_REG_DIVCMP_DIVCOMP_MASK 0x1ff
  176. +
  177. +/* I2S_REG_DIVINT */
  178. +#define I2S_REG_DIVINT_MASK 0x3ff
  179. +
  180. +/* BCLK dividers */
  181. +#define RALINK_I2S_DIVCMP 0
  182. +#define RALINK_I2S_DIVINT 1
  183. +
  184. +/* FIFO */
  185. +#define RALINK_I2S_FIFO_SIZE 32
  186. +
  187. +/* feature flags */
  188. +#define RALINK_FLAGS_TXONLY BIT(0)
  189. +#define RALINK_FLAGS_LEFT_J BIT(1)
  190. +#define RALINK_FLAGS_RIGHT_J BIT(2)
  191. +#define RALINK_FLAGS_ENDIAN BIT(3)
  192. +#define RALINK_FLAGS_24BIT BIT(4)
  193. +
  194. +#define RALINK_I2S_INT_EN 0
  195. +
  196. +struct ralink_i2s_stats {
  197. + u32 dmafault;
  198. + u32 overrun;
  199. + u32 underrun;
  200. + u32 belowthres;
  201. +};
  202. +
  203. +struct ralink_i2s {
  204. + struct device *dev;
  205. + void __iomem *regs;
  206. + struct clk *clk;
  207. + struct regmap *regmap;
  208. + u32 flags;
  209. + unsigned int fmt;
  210. + u16 txdma_req;
  211. + u16 rxdma_req;
  212. +
  213. + struct snd_dmaengine_dai_dma_data playback_dma_data;
  214. + struct snd_dmaengine_dai_dma_data capture_dma_data;
  215. +
  216. + struct dentry *dbg_dir;
  217. + struct dentry *dbg_stats;
  218. + struct ralink_i2s_stats txstats;
  219. + struct ralink_i2s_stats rxstats;
  220. +};
  221. +
  222. +static void ralink_i2s_dump_regs(struct ralink_i2s *i2s)
  223. +{
  224. + u32 buf[10];
  225. + int ret;
  226. +
  227. + ret = regmap_bulk_read(i2s->regmap, I2S_REG_CFG0,
  228. + buf, ARRAY_SIZE(buf));
  229. +
  230. + dev_dbg(i2s->dev, "CFG0: %08x, INTSTAT: %08x, INTEN: %08x, " \
  231. + "FFSTAT: %08x, WREG: %08x, RREG: %08x, " \
  232. + "CFG1: %08x, DIVCMP: %08x, DIVINT: %08x\n",
  233. + buf[0], buf[1], buf[2], buf[3], buf[4],
  234. + buf[5], buf[6], buf[8], buf[9]);
  235. +}
  236. +
  237. +static int ralink_i2s_set_sysclk(struct snd_soc_dai *dai,
  238. + int clk_id, unsigned int freq, int dir)
  239. +{
  240. + return 0;
  241. +}
  242. +
  243. +static int ralink_i2s_set_sys_bclk(struct snd_soc_dai *dai, int width, int rate)
  244. +{
  245. + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  246. + unsigned long clk = clk_get_rate(i2s->clk);
  247. + int div;
  248. + uint32_t data;
  249. +
  250. + /* disable clock at slave mode */
  251. + if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
  252. + SND_SOC_DAIFMT_CBM_CFM) {
  253. + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
  254. + I2S_REG_CFG0_CLK_DIS,
  255. + I2S_REG_CFG0_CLK_DIS);
  256. + return 0;
  257. + }
  258. +
  259. + /* FREQOUT = FREQIN / (I2S_CLK_DIV + 1) */
  260. + div = (clk / rate ) - 1;
  261. +
  262. + data = rt_sysc_r32(0x30);
  263. + data &= (0xff << 8);
  264. + data |= (0x1 << 15) | (div << 8);
  265. + rt_sysc_w32(data, 0x30);
  266. +
  267. + /* enable clock */
  268. + regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_CLK_DIS, 0);
  269. +
  270. + dev_dbg(i2s->dev, "clk: %lu, rate: %u, div: %d\n",
  271. + clk, rate, div);
  272. +
  273. + return 0;
  274. +}
  275. +
  276. +static int ralink_i2s_set_bclk(struct snd_soc_dai *dai, int width, int rate)
  277. +{
  278. + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  279. + unsigned long clk = clk_get_rate(i2s->clk);
  280. + int divint, divcomp;
  281. +
  282. + /* disable clock at slave mode */
  283. + if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
  284. + SND_SOC_DAIFMT_CBM_CFM) {
  285. + regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,
  286. + I2S_REG_DIVCMP_CLKEN, 0);
  287. + return 0;
  288. + }
  289. +
  290. + /* FREQOUT = FREQIN * (1/2) * (1/(DIVINT + DIVCOMP/512)) */
  291. + clk = clk / (2 * 2 * width);
  292. + divint = clk / rate;
  293. + divcomp = ((clk % rate) * 512) / rate;
  294. +
  295. + if ((divint > I2S_REG_DIVINT_MASK) ||
  296. + (divcomp > I2S_REG_DIVCMP_DIVCOMP_MASK))
  297. + return -EINVAL;
  298. +
  299. + regmap_update_bits(i2s->regmap, I2S_REG_DIVINT,
  300. + I2S_REG_DIVINT_MASK, divint);
  301. + regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,
  302. + I2S_REG_DIVCMP_DIVCOMP_MASK, divcomp);
  303. +
  304. + /* enable clock */
  305. + regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, I2S_REG_DIVCMP_CLKEN,
  306. + I2S_REG_DIVCMP_CLKEN);
  307. +
  308. + dev_dbg(i2s->dev, "clk: %lu, rate: %u, int: %d, comp: %d\n",
  309. + clk_get_rate(i2s->clk), rate, divint, divcomp);
  310. +
  311. + return 0;
  312. +}
  313. +
  314. +static int ralink_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  315. +{
  316. + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  317. + unsigned int cfg0 = 0, cfg1 = 0;
  318. +
  319. + /* set master/slave audio interface */
  320. + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  321. + case SND_SOC_DAIFMT_CBM_CFM:
  322. + if (i2s->flags & RALINK_FLAGS_TXONLY)
  323. + cfg0 |= I2S_REG_CFG0_SLAVE_EN;
  324. + else
  325. + cfg0 |= I2S_REG_CFG0_SLAVE;
  326. + break;
  327. + case SND_SOC_DAIFMT_CBS_CFS:
  328. + break;
  329. + default:
  330. + return -EINVAL;
  331. + }
  332. +
  333. + /* interface format */
  334. + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  335. + case SND_SOC_DAIFMT_I2S:
  336. + break;
  337. + case SND_SOC_DAIFMT_RIGHT_J:
  338. + if (i2s->flags & RALINK_FLAGS_RIGHT_J) {
  339. + cfg1 |= I2S_REG_CFG1_RIGHT_J;
  340. + break;
  341. + }
  342. + return -EINVAL;
  343. + case SND_SOC_DAIFMT_LEFT_J:
  344. + if (i2s->flags & RALINK_FLAGS_LEFT_J) {
  345. + cfg1 |= I2S_REG_CFG1_LEFT_J;
  346. + break;
  347. + }
  348. + return -EINVAL;
  349. + default:
  350. + return -EINVAL;
  351. + }
  352. +
  353. + /* clock inversion */
  354. + switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  355. + case SND_SOC_DAIFMT_NB_NF:
  356. + break;
  357. + default:
  358. + return -EINVAL;
  359. + }
  360. +
  361. + if (i2s->flags & RALINK_FLAGS_TXONLY) {
  362. + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
  363. + I2S_REG_CFG0_SLAVE_EN, cfg0);
  364. + } else {
  365. + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
  366. + I2S_REG_CFG0_SLAVE, cfg0);
  367. + }
  368. + regmap_update_bits(i2s->regmap, I2S_REG_CFG1,
  369. + I2S_REG_CFG1_FMT_MASK, cfg1);
  370. + i2s->fmt = fmt;
  371. +
  372. + return 0;
  373. +}
  374. +
  375. +static int ralink_i2s_startup(struct snd_pcm_substream *substream,
  376. + struct snd_soc_dai *dai)
  377. +{
  378. + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  379. +
  380. + if (dai->active)
  381. + return 0;
  382. +
  383. + /* setup status interrupt */
  384. +#if (RALINK_I2S_INT_EN)
  385. + regmap_write(i2s->regmap, I2S_REG_INT_EN, 0xff);
  386. +#else
  387. + regmap_write(i2s->regmap, I2S_REG_INT_EN, 0x0);
  388. +#endif
  389. +
  390. + /* enable */
  391. + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
  392. + I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |
  393. + I2S_REG_CFG0_THRES_MASK,
  394. + I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |
  395. + I2S_REG_CFG0_DFT_THRES);
  396. +
  397. + return 0;
  398. +}
  399. +
  400. +static void ralink_i2s_shutdown(struct snd_pcm_substream *substream,
  401. + struct snd_soc_dai *dai)
  402. +{
  403. + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  404. +
  405. + /* If both streams are stopped, disable module and clock */
  406. + if (dai->active)
  407. + return;
  408. +
  409. + /*
  410. + * datasheet mention when disable all control regs are cleared
  411. + * to initial values. need reinit at startup.
  412. + */
  413. + regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_EN, 0);
  414. +}
  415. +
  416. +static int ralink_i2s_hw_params(struct snd_pcm_substream *substream,
  417. + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  418. +{
  419. + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  420. + int width;
  421. + int ret;
  422. +
  423. + width = params_width(params);
  424. + switch (width) {
  425. + case 16:
  426. + if (i2s->flags & RALINK_FLAGS_24BIT)
  427. + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
  428. + I2S_REG_CFG0_DATA_24, 0);
  429. + break;
  430. + case 24:
  431. + if (i2s->flags & RALINK_FLAGS_24BIT) {
  432. + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
  433. + I2S_REG_CFG0_DATA_24,
  434. + I2S_REG_CFG0_DATA_24);
  435. + break;
  436. + }
  437. + return -EINVAL;
  438. + default:
  439. + return -EINVAL;
  440. + }
  441. +
  442. + switch (params_channels(params)) {
  443. + case 2:
  444. + break;
  445. + default:
  446. + return -EINVAL;
  447. + }
  448. +
  449. + if (i2s->flags & RALINK_FLAGS_ENDIAN) {
  450. + /* system endian */
  451. +#ifdef SNDRV_LITTLE_ENDIAN
  452. + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
  453. + I2S_REG_CFG0_SYS_BE, 0);
  454. +#else
  455. + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
  456. + I2S_REG_CFG0_SYS_BE,
  457. + I2S_REG_CFG0_SYS_BE);
  458. +#endif
  459. +
  460. + /* data endian */
  461. + switch (params_format(params)) {
  462. + case SNDRV_PCM_FORMAT_S16_LE:
  463. + case SNDRV_PCM_FORMAT_S24_LE:
  464. + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
  465. + I2S_REG_CFG0_FMT_LE,
  466. + I2S_REG_CFG0_FMT_LE);
  467. + break;
  468. + case SNDRV_PCM_FORMAT_S16_BE:
  469. + case SNDRV_PCM_FORMAT_S24_BE:
  470. + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
  471. + I2S_REG_CFG0_FMT_LE, 0);
  472. + break;
  473. + default:
  474. + return -EINVAL;
  475. + }
  476. + }
  477. +
  478. + /* setup bclk rate */
  479. + if (i2s->flags & RALINK_FLAGS_TXONLY)
  480. + ret = ralink_i2s_set_sys_bclk(dai, width, params_rate(params));
  481. + else
  482. + ret = ralink_i2s_set_bclk(dai, width, params_rate(params));
  483. +
  484. + return ret;
  485. +}
  486. +
  487. +static int ralink_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
  488. + struct snd_soc_dai *dai)
  489. +{
  490. + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  491. + unsigned int mask, val;
  492. +
  493. + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  494. + mask = I2S_REG_CFG0_TX_EN;
  495. + else
  496. + mask = I2S_REG_CFG0_RX_EN;
  497. +
  498. + switch (cmd) {
  499. + case SNDRV_PCM_TRIGGER_START:
  500. + case SNDRV_PCM_TRIGGER_RESUME:
  501. + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  502. + val = mask;
  503. + break;
  504. + case SNDRV_PCM_TRIGGER_STOP:
  505. + case SNDRV_PCM_TRIGGER_SUSPEND:
  506. + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  507. + val = 0;
  508. + break;
  509. + default:
  510. + return -EINVAL;
  511. + }
  512. +
  513. + regmap_update_bits(i2s->regmap, I2S_REG_CFG0, mask, val);
  514. +
  515. + return 0;
  516. +}
  517. +
  518. +static void ralink_i2s_init_dma_data(struct ralink_i2s *i2s,
  519. + struct resource *res)
  520. +{
  521. + struct snd_dmaengine_dai_dma_data *dma_data;
  522. +
  523. + /* Playback */
  524. + dma_data = &i2s->playback_dma_data;
  525. + dma_data->addr = res->start + I2S_REG_WREG;
  526. + dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  527. + dma_data->maxburst = 1;
  528. + dma_data->slave_id = i2s->txdma_req;
  529. +
  530. + if (i2s->flags & RALINK_FLAGS_TXONLY)
  531. + return;
  532. +
  533. + /* Capture */
  534. + dma_data = &i2s->capture_dma_data;
  535. + dma_data->addr = res->start + I2S_REG_RREG;
  536. + dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  537. + dma_data->maxburst = 1;
  538. + dma_data->slave_id = i2s->rxdma_req;
  539. +}
  540. +
  541. +static int ralink_i2s_dai_probe(struct snd_soc_dai *dai)
  542. +{
  543. + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  544. +
  545. + snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
  546. + &i2s->capture_dma_data);
  547. +
  548. + return 0;
  549. +}
  550. +
  551. +static int ralink_i2s_dai_remove(struct snd_soc_dai *dai)
  552. +{
  553. + return 0;
  554. +}
  555. +
  556. +static const struct snd_soc_dai_ops ralink_i2s_dai_ops = {
  557. + .set_sysclk = ralink_i2s_set_sysclk,
  558. + .set_fmt = ralink_i2s_set_fmt,
  559. + .startup = ralink_i2s_startup,
  560. + .shutdown = ralink_i2s_shutdown,
  561. + .hw_params = ralink_i2s_hw_params,
  562. + .trigger = ralink_i2s_trigger,
  563. +};
  564. +
  565. +static struct snd_soc_dai_driver ralink_i2s_dai = {
  566. + .name = DRV_NAME,
  567. + .probe = ralink_i2s_dai_probe,
  568. + .remove = ralink_i2s_dai_remove,
  569. + .ops = &ralink_i2s_dai_ops,
  570. + .capture = {
  571. + .stream_name = "I2S Capture",
  572. + .channels_min = 2,
  573. + .channels_max = 2,
  574. + .rate_min = 5512,
  575. + .rate_max = 192000,
  576. + .rates = SNDRV_PCM_RATE_CONTINUOUS,
  577. + .formats = SNDRV_PCM_FMTBIT_S16_LE,
  578. + },
  579. + .playback = {
  580. + .stream_name = "I2S Playback",
  581. + .channels_min = 2,
  582. + .channels_max = 2,
  583. + .rate_min = 5512,
  584. + .rate_max = 192000,
  585. + .rates = SNDRV_PCM_RATE_CONTINUOUS,
  586. + .formats = SNDRV_PCM_FMTBIT_S16_LE,
  587. + },
  588. + .symmetric_rates = 1,
  589. +};
  590. +
  591. +static struct snd_pcm_hardware ralink_pcm_hardware = {
  592. + .info = SNDRV_PCM_INFO_MMAP |
  593. + SNDRV_PCM_INFO_MMAP_VALID |
  594. + SNDRV_PCM_INFO_INTERLEAVED |
  595. + SNDRV_PCM_INFO_BLOCK_TRANSFER,
  596. + .formats = SNDRV_PCM_FMTBIT_S16_LE,
  597. + .channels_min = 2,
  598. + .channels_max = 2,
  599. + .period_bytes_min = PAGE_SIZE,
  600. + .period_bytes_max = PAGE_SIZE * 2,
  601. + .periods_min = 2,
  602. + .periods_max = 128,
  603. + .buffer_bytes_max = 128 * 1024,
  604. + .fifo_size = RALINK_I2S_FIFO_SIZE,
  605. +};
  606. +
  607. +static const struct snd_dmaengine_pcm_config ralink_dmaengine_pcm_config = {
  608. + .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
  609. + .pcm_hardware = &ralink_pcm_hardware,
  610. + .prealloc_buffer_size = 256 * PAGE_SIZE,
  611. +};
  612. +
  613. +static const struct snd_soc_component_driver ralink_i2s_component = {
  614. + .name = DRV_NAME,
  615. +};
  616. +
  617. +static bool ralink_i2s_readable_reg(struct device *dev, unsigned int reg)
  618. +{
  619. + return true;
  620. +}
  621. +
  622. +static bool ralink_i2s_volatile_reg(struct device *dev, unsigned int reg)
  623. +{
  624. + switch (reg) {
  625. + case I2S_REG_INT_STATUS:
  626. + case I2S_REG_FF_STATUS:
  627. + return true;
  628. + }
  629. + return false;
  630. +}
  631. +
  632. +static bool ralink_i2s_writeable_reg(struct device *dev, unsigned int reg)
  633. +{
  634. + switch (reg) {
  635. + case I2S_REG_FF_STATUS:
  636. + case I2S_REG_RREG:
  637. + return false;
  638. + }
  639. + return true;
  640. +}
  641. +
  642. +static const struct regmap_config ralink_i2s_regmap_config = {
  643. + .reg_bits = 32,
  644. + .reg_stride = 4,
  645. + .val_bits = 32,
  646. + .writeable_reg = ralink_i2s_writeable_reg,
  647. + .readable_reg = ralink_i2s_readable_reg,
  648. + .volatile_reg = ralink_i2s_volatile_reg,
  649. + .max_register = I2S_REG_DIVINT,
  650. +};
  651. +
  652. +#if (RALINK_I2S_INT_EN)
  653. +static irqreturn_t ralink_i2s_irq(int irq, void *devid)
  654. +{
  655. + struct ralink_i2s *i2s = devid;
  656. + u32 status;
  657. +
  658. + regmap_read(i2s->regmap, I2S_REG_INT_STATUS, &status);
  659. + if (unlikely(!status))
  660. + return IRQ_NONE;
  661. +
  662. + /* tx stats */
  663. + if (status & I2S_REG_INT_TX_MASK) {
  664. + if (status & I2S_REG_INT_TX_THRES)
  665. + i2s->txstats.belowthres++;
  666. + if (status & I2S_REG_INT_TX_UNRUN)
  667. + i2s->txstats.underrun++;
  668. + if (status & I2S_REG_INT_TX_OVRUN)
  669. + i2s->txstats.overrun++;
  670. + if (status & I2S_REG_INT_TX_FAULT)
  671. + i2s->txstats.dmafault++;
  672. + }
  673. +
  674. + /* rx stats */
  675. + if (status & I2S_REG_INT_RX_MASK) {
  676. + if (status & I2S_REG_INT_RX_THRES)
  677. + i2s->rxstats.belowthres++;
  678. + if (status & I2S_REG_INT_RX_UNRUN)
  679. + i2s->rxstats.underrun++;
  680. + if (status & I2S_REG_INT_RX_OVRUN)
  681. + i2s->rxstats.overrun++;
  682. + if (status & I2S_REG_INT_RX_FAULT)
  683. + i2s->rxstats.dmafault++;
  684. + }
  685. +
  686. + /* clean status bits */
  687. + regmap_write(i2s->regmap, I2S_REG_INT_STATUS, status);
  688. +
  689. + return IRQ_HANDLED;
  690. +}
  691. +#endif
  692. +
  693. +#if IS_ENABLED(CONFIG_DEBUG_FS)
  694. +static int ralink_i2s_stats_show(struct seq_file *s, void *unused)
  695. +{
  696. + struct ralink_i2s *i2s = s->private;
  697. +
  698. + seq_printf(s, "tx stats\n");
  699. + seq_printf(s, "\tbelow threshold\t%u\n", i2s->txstats.belowthres);
  700. + seq_printf(s, "\tunder run\t%u\n", i2s->txstats.underrun);
  701. + seq_printf(s, "\tover run\t%u\n", i2s->txstats.overrun);
  702. + seq_printf(s, "\tdma fault\t%u\n", i2s->txstats.dmafault);
  703. +
  704. + seq_printf(s, "rx stats\n");
  705. + seq_printf(s, "\tbelow threshold\t%u\n", i2s->rxstats.belowthres);
  706. + seq_printf(s, "\tunder run\t%u\n", i2s->rxstats.underrun);
  707. + seq_printf(s, "\tover run\t%u\n", i2s->rxstats.overrun);
  708. + seq_printf(s, "\tdma fault\t%u\n", i2s->rxstats.dmafault);
  709. +
  710. + ralink_i2s_dump_regs(i2s);
  711. +
  712. + return 0;
  713. +}
  714. +
  715. +static int ralink_i2s_stats_open(struct inode *inode, struct file *file)
  716. +{
  717. + return single_open(file, ralink_i2s_stats_show, inode->i_private);
  718. +}
  719. +
  720. +static const struct file_operations ralink_i2s_stats_ops = {
  721. + .open = ralink_i2s_stats_open,
  722. + .read = seq_read,
  723. + .llseek = seq_lseek,
  724. + .release = single_release,
  725. +};
  726. +
  727. +static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)
  728. +{
  729. + i2s->dbg_dir = debugfs_create_dir(dev_name(i2s->dev), NULL);
  730. + if (!i2s->dbg_dir)
  731. + return -ENOMEM;
  732. +
  733. + i2s->dbg_stats = debugfs_create_file("stats", S_IRUGO,
  734. + i2s->dbg_dir, i2s, &ralink_i2s_stats_ops);
  735. + if (!i2s->dbg_stats) {
  736. + debugfs_remove(i2s->dbg_dir);
  737. + return -ENOMEM;
  738. + }
  739. +
  740. + return 0;
  741. +}
  742. +
  743. +static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)
  744. +{
  745. + debugfs_remove(i2s->dbg_stats);
  746. + debugfs_remove(i2s->dbg_dir);
  747. +}
  748. +#else
  749. +static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)
  750. +{
  751. + return 0;
  752. +}
  753. +
  754. +static inline void ralink_i2s_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg)
  755. +{
  756. +}
  757. +#endif
  758. +
  759. +/*
  760. + * TODO: these refclk setup functions should use
  761. + * clock framework instead. hardcode it now.
  762. + */
  763. +static void rt3350_refclk_setup(void)
  764. +{
  765. + uint32_t data;
  766. +
  767. + /* set refclk output 12Mhz clock */
  768. + data = rt_sysc_r32(0x2c);
  769. + data |= (0x1 << 8);
  770. + rt_sysc_w32(data, 0x2c);
  771. +}
  772. +
  773. +static void rt3883_refclk_setup(void)
  774. +{
  775. + uint32_t data;
  776. +
  777. + /* set refclk output 12Mhz clock */
  778. + data = rt_sysc_r32(0x2c);
  779. + data &= ~(0x3 << 13);
  780. + data |= (0x1 << 13);
  781. + rt_sysc_w32(data, 0x2c);
  782. +}
  783. +
  784. +static void rt3552_refclk_setup(void)
  785. +{
  786. + uint32_t data;
  787. +
  788. + /* set refclk output 12Mhz clock */
  789. + data = rt_sysc_r32(0x2c);
  790. + data &= ~(0xf << 8);
  791. + data |= (0x3 << 8);
  792. + rt_sysc_w32(data, 0x2c);
  793. +}
  794. +
  795. +static void mt7620_refclk_setup(void)
  796. +{
  797. + uint32_t data;
  798. +
  799. + /* set refclk output 12Mhz clock */
  800. + data = rt_sysc_r32(0x2c);
  801. + data &= ~(0x7 << 9);
  802. + data |= 0x1 << 9;
  803. + rt_sysc_w32(data, 0x2c);
  804. +}
  805. +
  806. +static void mt7621_refclk_setup(void)
  807. +{
  808. + uint32_t data;
  809. +
  810. + /* set refclk output 12Mhz clock */
  811. + data = rt_sysc_r32(0x2c);
  812. + data &= ~(0x1f << 18);
  813. + data |= (0x19 << 18);
  814. + data &= ~(0x1f << 12);
  815. + data |= (0x1 << 12);
  816. + data &= ~(0x7 << 9);
  817. + data |= (0x5 << 9);
  818. + rt_sysc_w32(data, 0x2c);
  819. +}
  820. +
  821. +static void mt7628_refclk_setup(void)
  822. +{
  823. + uint32_t data;
  824. +
  825. + /* set i2s and refclk digital pad */
  826. + data = rt_sysc_r32(0x3c);
  827. + data |= 0x1f;
  828. + rt_sysc_w32(data, 0x3c);
  829. +
  830. + /* Adjust REFCLK0's driving strength */
  831. + data = rt_sysc_r32(0x1354);
  832. + data &= ~(0x1 << 5);
  833. + rt_sysc_w32(data, 0x1354);
  834. + data = rt_sysc_r32(0x1364);
  835. + data |= ~(0x1 << 5);
  836. + rt_sysc_w32(data, 0x1364);
  837. +
  838. + /* set refclk output 12Mhz clock */
  839. + data = rt_sysc_r32(0x2c);
  840. + data &= ~(0x7 << 9);
  841. + data |= 0x1 << 9;
  842. + rt_sysc_w32(data, 0x2c);
  843. +}
  844. +
  845. +struct rt_i2s_data {
  846. + u32 flags;
  847. + void (*refclk_setup)(void);
  848. +};
  849. +
  850. +struct rt_i2s_data rt3050_i2s_data = { .flags = RALINK_FLAGS_TXONLY };
  851. +struct rt_i2s_data rt3350_i2s_data = { .flags = RALINK_FLAGS_TXONLY,
  852. + .refclk_setup = rt3350_refclk_setup };
  853. +struct rt_i2s_data rt3883_i2s_data = {
  854. + .flags = (RALINK_FLAGS_LEFT_J | RALINK_FLAGS_RIGHT_J),
  855. + .refclk_setup = rt3883_refclk_setup };
  856. +struct rt_i2s_data rt3352_i2s_data = { .refclk_setup = rt3552_refclk_setup};
  857. +struct rt_i2s_data mt7620_i2s_data = { .refclk_setup = mt7620_refclk_setup};
  858. +struct rt_i2s_data mt7621_i2s_data = { .refclk_setup = mt7621_refclk_setup};
  859. +struct rt_i2s_data mt7628_i2s_data = {
  860. + .flags = (RALINK_FLAGS_ENDIAN | RALINK_FLAGS_24BIT |
  861. + RALINK_FLAGS_LEFT_J),
  862. + .refclk_setup = mt7628_refclk_setup};
  863. +
  864. +static const struct of_device_id ralink_i2s_match_table[] = {
  865. + { .compatible = "ralink,rt3050-i2s",
  866. + .data = (void *)&rt3050_i2s_data },
  867. + { .compatible = "ralink,rt3350-i2s",
  868. + .data = (void *)&rt3350_i2s_data },
  869. + { .compatible = "ralink,rt3883-i2s",
  870. + .data = (void *)&rt3883_i2s_data },
  871. + { .compatible = "ralink,rt3352-i2s",
  872. + .data = (void *)&rt3352_i2s_data },
  873. + { .compatible = "mediatek,mt7620-i2s",
  874. + .data = (void *)&mt7620_i2s_data },
  875. + { .compatible = "mediatek,mt7621-i2s",
  876. + .data = (void *)&mt7621_i2s_data },
  877. + { .compatible = "mediatek,mt7628-i2s",
  878. + .data = (void *)&mt7628_i2s_data },
  879. +};
  880. +MODULE_DEVICE_TABLE(of, ralink_i2s_match_table);
  881. +
  882. +static int ralink_i2s_probe(struct platform_device *pdev)
  883. +{
  884. + const struct of_device_id *match;
  885. + struct device_node *np = pdev->dev.of_node;
  886. + struct ralink_i2s *i2s;
  887. + struct resource *res;
  888. + int irq, ret;
  889. + u32 dma_req;
  890. + struct rt_i2s_data *data;
  891. +
  892. + i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
  893. + if (!i2s)
  894. + return -ENOMEM;
  895. +
  896. + platform_set_drvdata(pdev, i2s);
  897. + i2s->dev = &pdev->dev;
  898. +
  899. + match = of_match_device(ralink_i2s_match_table, &pdev->dev);
  900. + if (!match)
  901. + return -EINVAL;
  902. + data = (struct rt_i2s_data *)match->data;
  903. + i2s->flags = data->flags;
  904. + /* setup out 12Mhz refclk to codec as mclk */
  905. + if (data->refclk_setup)
  906. + data->refclk_setup();
  907. +
  908. + if (of_property_read_u32(np, "txdma-req", &dma_req)) {
  909. + dev_err(&pdev->dev, "no txdma-req define\n");
  910. + return -EINVAL;
  911. + }
  912. + i2s->txdma_req = (u16)dma_req;
  913. + if (!(i2s->flags & RALINK_FLAGS_TXONLY)) {
  914. + if (of_property_read_u32(np, "rxdma-req", &dma_req)) {
  915. + dev_err(&pdev->dev, "no rxdma-req define\n");
  916. + return -EINVAL;
  917. + }
  918. + i2s->rxdma_req = (u16)dma_req;
  919. + }
  920. +
  921. + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  922. + i2s->regs = devm_ioremap_resource(&pdev->dev, res);
  923. + if (IS_ERR(i2s->regs))
  924. + return PTR_ERR(i2s->regs);
  925. +
  926. + i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,
  927. + &ralink_i2s_regmap_config);
  928. + if (IS_ERR(i2s->regmap)) {
  929. + dev_err(&pdev->dev, "regmap init failed\n");
  930. + return PTR_ERR(i2s->regmap);
  931. + }
  932. +
  933. + irq = platform_get_irq(pdev, 0);
  934. + if (irq < 0) {
  935. + dev_err(&pdev->dev, "failed to get irq\n");
  936. + return -EINVAL;
  937. + }
  938. +
  939. +#if (RALINK_I2S_INT_EN)
  940. + ret = devm_request_irq(&pdev->dev, irq, ralink_i2s_irq,
  941. + 0, dev_name(&pdev->dev), i2s);
  942. + if (ret) {
  943. + dev_err(&pdev->dev, "failed to request irq\n");
  944. + return ret;
  945. + }
  946. +#endif
  947. +
  948. + i2s->clk = devm_clk_get(&pdev->dev, NULL);
  949. + if (IS_ERR(i2s->clk)) {
  950. + dev_err(&pdev->dev, "no clock defined\n");
  951. + return PTR_ERR(i2s->clk);
  952. + }
  953. +
  954. + ret = clk_prepare_enable(i2s->clk);
  955. + if (ret)
  956. + return ret;
  957. +
  958. + ralink_i2s_init_dma_data(i2s, res);
  959. +
  960. + device_reset(&pdev->dev);
  961. +
  962. + ret = ralink_i2s_debugfs_create(i2s);
  963. + if (ret) {
  964. + dev_err(&pdev->dev, "create debugfs failed\n");
  965. + goto err_clk_disable;
  966. + }
  967. +
  968. + /* enable 24bits support */
  969. + if (i2s->flags & RALINK_FLAGS_24BIT) {
  970. + ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S24_LE;
  971. + ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S24_LE;
  972. + }
  973. +
  974. + /* enable big endian support */
  975. + if (i2s->flags & RALINK_FLAGS_ENDIAN) {
  976. + ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S16_BE;
  977. + ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S16_BE;
  978. + ralink_pcm_hardware.formats |= SNDRV_PCM_FMTBIT_S16_BE;
  979. + if (i2s->flags & RALINK_FLAGS_24BIT) {
  980. + ralink_i2s_dai.capture.formats |=
  981. + SNDRV_PCM_FMTBIT_S24_BE;
  982. + ralink_i2s_dai.playback.formats |=
  983. + SNDRV_PCM_FMTBIT_S24_BE;
  984. + ralink_pcm_hardware.formats |=
  985. + SNDRV_PCM_FMTBIT_S24_BE;
  986. + }
  987. + }
  988. +
  989. + /* disable capture support */
  990. + if (i2s->flags & RALINK_FLAGS_TXONLY)
  991. + memset(&ralink_i2s_dai.capture, sizeof(ralink_i2s_dai.capture),
  992. + 0);
  993. +
  994. + ret = devm_snd_soc_register_component(&pdev->dev, &ralink_i2s_component,
  995. + &ralink_i2s_dai, 1);
  996. + if (ret)
  997. + goto err_debugfs;
  998. +
  999. + ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
  1000. + &ralink_dmaengine_pcm_config,
  1001. + SND_DMAENGINE_PCM_FLAG_COMPAT);
  1002. + if (ret)
  1003. + goto err_debugfs;
  1004. +
  1005. + dev_info(i2s->dev, "mclk %luKHz\n", clk_get_rate(i2s->clk) / 1000000);
  1006. +
  1007. + return 0;
  1008. +
  1009. +err_debugfs:
  1010. + ralink_i2s_debugfs_remove(i2s);
  1011. +
  1012. +err_clk_disable:
  1013. + clk_disable_unprepare(i2s->clk);
  1014. +
  1015. + return ret;
  1016. +}
  1017. +
  1018. +static int ralink_i2s_remove(struct platform_device *pdev)
  1019. +{
  1020. + struct ralink_i2s *i2s = platform_get_drvdata(pdev);
  1021. +
  1022. + ralink_i2s_debugfs_remove(i2s);
  1023. + clk_disable_unprepare(i2s->clk);
  1024. +
  1025. + return 0;
  1026. +}
  1027. +
  1028. +static struct platform_driver ralink_i2s_driver = {
  1029. + .probe = ralink_i2s_probe,
  1030. + .remove = ralink_i2s_remove,
  1031. + .driver = {
  1032. + .name = DRV_NAME,
  1033. + .of_match_table = ralink_i2s_match_table,
  1034. + },
  1035. +};
  1036. +module_platform_driver(ralink_i2s_driver);
  1037. +
  1038. +MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
  1039. +MODULE_DESCRIPTION("Ralink/MediaTek I2S driver");
  1040. +MODULE_LICENSE("GPL");
  1041. +MODULE_ALIAS("platform:" DRV_NAME);