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0506-net-next-mediatek-add-support-for-rt3050.patch 7.1 KB

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  1. From a3555658ce5dd97df3dc225289b92800da9d38ba Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Mon, 14 Dec 2015 21:28:51 +0100
  4. Subject: [PATCH 506/513] net-next: mediatek: add support for rt3050
  5. Add support for SoCs from the rt3050 family. This include rt3050, rt3052,
  6. rt3352 and rt5350. These all have a builtin 5 port 100mbit switch. This patch
  7. includes rudimentary code to power up the switch. There are a lot of magic
  8. values that get written to the switch and the internal phys. These values
  9. come straight from the SDK driver and we do not know the meaning of most of
  10. them.
  11. Signed-off-by: John Crispin <blogic@openwrt.org>
  12. Signed-off-by: Felix Fietkau <nbd@nbd.name>
  13. Signed-off-by: Michael Lee <igvtee@gmail.com>
  14. ---
  15. drivers/net/ethernet/mediatek/esw_rt3050.c | 18 +---
  16. drivers/net/ethernet/mediatek/soc_rt3050.c | 158 ++++++++++++++++++++++++++++
  17. 2 files changed, 159 insertions(+), 17 deletions(-)
  18. create mode 100644 drivers/net/ethernet/mediatek/soc_rt3050.c
  19. --- a/drivers/net/ethernet/mediatek/esw_rt3050.c
  20. +++ b/drivers/net/ethernet/mediatek/esw_rt3050.c
  21. @@ -14,27 +14,11 @@
  22. #include <linux/module.h>
  23. #include <linux/kernel.h>
  24. -#include <linux/types.h>
  25. -#include <linux/dma-mapping.h>
  26. -#include <linux/init.h>
  27. -#include <linux/skbuff.h>
  28. -#include <linux/etherdevice.h>
  29. -#include <linux/ethtool.h>
  30. #include <linux/platform_device.h>
  31. -#include <linux/of_device.h>
  32. -#include <linux/clk.h>
  33. -#include <linux/of_net.h>
  34. -#include <linux/of_mdio.h>
  35. -
  36. #include <asm/mach-ralink/ralink_regs.h>
  37. #include "mtk_eth_soc.h"
  38. -#include <linux/ioport.h>
  39. -#include <linux/mii.h>
  40. -
  41. -#include <ralink_regs.h>
  42. -
  43. /* HW limitations for this switch:
  44. * - No large frame support (PKT_MAX_LEN at most 1536)
  45. * - Can't have untagged vlan and tagged vlan on one port at the same time,
  46. @@ -559,7 +543,7 @@ static irqreturn_t esw_interrupt(int irq
  47. static int esw_probe(struct platform_device *pdev)
  48. {
  49. - struct resource *res = platform_get_resource(p, IORESOURCE_MEM, 0);
  50. + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  51. struct device_node *np = pdev->dev.of_node;
  52. const __be32 *port_map, *reg_init;
  53. struct rt305x_esw *esw;
  54. @@ -629,12 +613,9 @@ static struct platform_driver esw_driver
  55. },
  56. };
  57. -int __init mtk_switch_init(void)
  58. -{
  59. - return platform_driver_register(&esw_driver);
  60. -}
  61. +module_platform_driver(esw_driver);
  62. -void mtk_switch_exit(void)
  63. -{
  64. - platform_driver_unregister(&esw_driver);
  65. -}
  66. +MODULE_LICENSE("GPL");
  67. +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
  68. +MODULE_DESCRIPTION("Switch driver for RT305X SoC");
  69. +MODULE_VERSION(MTK_FE_DRV_VERSION);
  70. --- /dev/null
  71. +++ b/drivers/net/ethernet/mediatek/soc_rt3050.c
  72. @@ -0,0 +1,158 @@
  73. +/* This program is free software; you can redistribute it and/or modify
  74. + * it under the terms of the GNU General Public License as published by
  75. + * the Free Software Foundation; version 2 of the License
  76. + *
  77. + * This program is distributed in the hope that it will be useful,
  78. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  79. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  80. + * GNU General Public License for more details.
  81. + *
  82. + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  83. + * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  84. + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  85. + */
  86. +
  87. +#include <linux/module.h>
  88. +
  89. +#include <asm/mach-ralink/ralink_regs.h>
  90. +
  91. +#include "mtk_eth_soc.h"
  92. +#include "mdio_rt2880.h"
  93. +
  94. +#define RT305X_RESET_FE BIT(21)
  95. +#define RT305X_RESET_ESW BIT(23)
  96. +
  97. +static const u16 rt5350_reg_table[FE_REG_COUNT] = {
  98. + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
  99. + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
  100. + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
  101. + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
  102. + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
  103. + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
  104. + [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
  105. + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
  106. + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
  107. + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
  108. + [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
  109. + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
  110. + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
  111. + [FE_REG_FE_RST_GL] = 0,
  112. + [FE_REG_FE_DMA_VID_BASE] = 0,
  113. +};
  114. +
  115. +static void rt305x_init_data(struct fe_soc_data *data,
  116. + struct net_device *netdev)
  117. +{
  118. + struct fe_priv *priv = netdev_priv(netdev);
  119. +
  120. + priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
  121. + FE_FLAG_CALIBRATE_CLK | FE_FLAG_HAS_SWITCH;
  122. + netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
  123. + NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
  124. +}
  125. +
  126. +static int rt3050_fwd_config(struct fe_priv *priv)
  127. +{
  128. + int ret;
  129. +
  130. + if (ralink_soc != RT305X_SOC_RT3052) {
  131. + ret = fe_set_clock_cycle(priv);
  132. + if (ret)
  133. + return ret;
  134. + }
  135. +
  136. + fe_fwd_config(priv);
  137. + if (ralink_soc != RT305X_SOC_RT3352)
  138. + fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
  139. + fe_csum_config(priv);
  140. +
  141. + return 0;
  142. +}
  143. +
  144. +static void rt305x_fe_reset(void)
  145. +{
  146. + fe_reset(RT305X_RESET_FE);
  147. +}
  148. +
  149. +static void rt5350_init_data(struct fe_soc_data *data,
  150. + struct net_device *netdev)
  151. +{
  152. + struct fe_priv *priv = netdev_priv(netdev);
  153. +
  154. + priv->flags = FE_FLAG_HAS_SWITCH;
  155. + netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM;
  156. +}
  157. +
  158. +static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
  159. +{
  160. + unsigned long flags;
  161. +
  162. + spin_lock_irqsave(&priv->page_lock, flags);
  163. + fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
  164. + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
  165. + RT5350_SDM_MAC_ADRL);
  166. + spin_unlock_irqrestore(&priv->page_lock, flags);
  167. +}
  168. +
  169. +static void rt5350_rxcsum_config(bool enable)
  170. +{
  171. + if (enable)
  172. + fe_w32(fe_r32(RT5350_SDM_CFG) | (RT5350_SDM_ICS_EN |
  173. + RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
  174. + RT5350_SDM_CFG);
  175. + else
  176. + fe_w32(fe_r32(RT5350_SDM_CFG) & ~(RT5350_SDM_ICS_EN |
  177. + RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
  178. + RT5350_SDM_CFG);
  179. +}
  180. +
  181. +static int rt5350_fwd_config(struct fe_priv *priv)
  182. +{
  183. + struct net_device *dev = priv_netdev(priv);
  184. +
  185. + rt5350_rxcsum_config((dev->features & NETIF_F_RXCSUM));
  186. +
  187. + return 0;
  188. +}
  189. +
  190. +static void rt5350_tx_dma(struct fe_tx_dma *txd)
  191. +{
  192. + txd->txd4 = 0;
  193. +}
  194. +
  195. +static void rt5350_fe_reset(void)
  196. +{
  197. + fe_reset(RT305X_RESET_FE | RT305X_RESET_ESW);
  198. +}
  199. +
  200. +static struct fe_soc_data rt3050_data = {
  201. + .init_data = rt305x_init_data,
  202. + .reset_fe = rt305x_fe_reset,
  203. + .fwd_config = rt3050_fwd_config,
  204. + .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
  205. + .checksum_bit = RX_DMA_L4VALID,
  206. + .rx_int = FE_RX_DONE_INT,
  207. + .tx_int = FE_TX_DONE_INT,
  208. + .status_int = FE_CNT_GDM_AF,
  209. +};
  210. +
  211. +static struct fe_soc_data rt5350_data = {
  212. + .init_data = rt5350_init_data,
  213. + .reg_table = rt5350_reg_table,
  214. + .reset_fe = rt5350_fe_reset,
  215. + .set_mac = rt5350_set_mac,
  216. + .fwd_config = rt5350_fwd_config,
  217. + .tx_dma = rt5350_tx_dma,
  218. + .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
  219. + .checksum_bit = RX_DMA_L4VALID,
  220. + .rx_int = RT5350_RX_DONE_INT,
  221. + .tx_int = RT5350_TX_DONE_INT,
  222. +};
  223. +
  224. +const struct of_device_id of_fe_match[] = {
  225. + { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
  226. + { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
  227. + {},
  228. +};
  229. +
  230. +MODULE_DEVICE_TABLE(of, of_fe_match);