0508-net-next-mediatek-add-support-for-mt7620.patch 15 KB

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  1. From 1efca7b539a91c49ab1d6484ec3a69c48fa6062b Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Mon, 14 Dec 2015 21:25:35 +0100
  4. Subject: [PATCH 508/513] net-next: mediatek: add support for mt7620
  5. Add support for SoCs from the mt7620 family. This include mt7620 and mt7621.
  6. These all have one dedicated external gbit port and a builtin 5 port 100mbit
  7. switch. Additionally one of the 5 switch ports can be changed to become an
  8. additional gbit port that we can attach a phy to. This patch includes
  9. rudimentary code to power up the switch. There are a lot of magic values
  10. that get written to the switch and the internal phys. These values come
  11. straight from the SDK driver.
  12. Signed-off-by: John Crispin <blogic@openwrt.org>
  13. Signed-off-by: Felix Fietkau <nbd@nbd.name>
  14. Signed-off-by: Michael Lee <igvtee@gmail.com>
  15. ---
  16. drivers/net/ethernet/mediatek/mdio_mt7620.c | 156 +++++++++++++
  17. drivers/net/ethernet/mediatek/soc_mt7620.c | 334 +++++++++++++++++++++++++++
  18. 2 files changed, 490 insertions(+)
  19. create mode 100644 drivers/net/ethernet/mediatek/mdio_mt7620.c
  20. create mode 100644 drivers/net/ethernet/mediatek/soc_mt7620.c
  21. --- /dev/null
  22. +++ b/drivers/net/ethernet/mediatek/mdio_mt7620.c
  23. @@ -0,0 +1,156 @@
  24. +/* This program is free software; you can redistribute it and/or modify
  25. + * it under the terms of the GNU General Public License as published by
  26. + * the Free Software Foundation; version 2 of the License
  27. + *
  28. + * This program is distributed in the hope that it will be useful,
  29. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  30. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  31. + * GNU General Public License for more details.
  32. + *
  33. + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  34. + * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  35. + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  36. + */
  37. +
  38. +#include <linux/module.h>
  39. +#include <linux/kernel.h>
  40. +#include <linux/types.h>
  41. +
  42. +#include "mtk_eth_soc.h"
  43. +#include "gsw_mt7620.h"
  44. +#include "mdio.h"
  45. +
  46. +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
  47. +{
  48. + unsigned long t_start = jiffies;
  49. +
  50. + while (1) {
  51. + if (!(mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
  52. + return 0;
  53. + if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT))
  54. + break;
  55. + }
  56. +
  57. + dev_err(gsw->dev, "mdio: MDIO timeout\n");
  58. + return -1;
  59. +}
  60. +
  61. +u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
  62. + u32 phy_register, u32 write_data)
  63. +{
  64. + if (mt7620_mii_busy_wait(gsw))
  65. + return -1;
  66. +
  67. + write_data &= 0xffff;
  68. +
  69. + mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
  70. + (phy_register << GSW_MDIO_REG_SHIFT) |
  71. + (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
  72. + MT7620A_GSW_REG_PIAC);
  73. +
  74. + if (mt7620_mii_busy_wait(gsw))
  75. + return -1;
  76. +
  77. + return 0;
  78. +}
  79. +
  80. +u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
  81. +{
  82. + u32 d;
  83. +
  84. + if (mt7620_mii_busy_wait(gsw))
  85. + return 0xffff;
  86. +
  87. + mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
  88. + (phy_reg << GSW_MDIO_REG_SHIFT) |
  89. + (phy_addr << GSW_MDIO_ADDR_SHIFT),
  90. + MT7620A_GSW_REG_PIAC);
  91. +
  92. + if (mt7620_mii_busy_wait(gsw))
  93. + return 0xffff;
  94. +
  95. + d = mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
  96. +
  97. + return d;
  98. +}
  99. +
  100. +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
  101. +{
  102. + struct fe_priv *priv = bus->priv;
  103. + struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
  104. +
  105. + return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
  106. +}
  107. +
  108. +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
  109. +{
  110. + struct fe_priv *priv = bus->priv;
  111. + struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
  112. +
  113. + return _mt7620_mii_read(gsw, phy_addr, phy_reg);
  114. +}
  115. +
  116. +void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)
  117. +{
  118. + _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
  119. + _mt7620_mii_write(gsw, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
  120. + _mt7620_mii_write(gsw, 0x1f, 0x10, val >> 16);
  121. +}
  122. +
  123. +u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)
  124. +{
  125. + u16 high, low;
  126. +
  127. + _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
  128. + low = _mt7620_mii_read(gsw, 0x1f, (reg >> 2) & 0xf);
  129. + high = _mt7620_mii_read(gsw, 0x1f, 0x10);
  130. +
  131. + return (high << 16) | (low & 0xffff);
  132. +}
  133. +
  134. +static unsigned char *fe_speed_str(int speed)
  135. +{
  136. + switch (speed) {
  137. + case 2:
  138. + case SPEED_1000:
  139. + return "1000";
  140. + case 1:
  141. + case SPEED_100:
  142. + return "100";
  143. + case 0:
  144. + case SPEED_10:
  145. + return "10";
  146. + }
  147. +
  148. + return "? ";
  149. +}
  150. +
  151. +int mt7620_has_carrier(struct fe_priv *priv)
  152. +{
  153. + struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
  154. + int i;
  155. +
  156. + for (i = 0; i < GSW_PORT6; i++)
  157. + if (mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
  158. + return 1;
  159. + return 0;
  160. +}
  161. +
  162. +
  163. +void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
  164. + int speed, int duplex)
  165. +{
  166. + if (link)
  167. + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
  168. + port, fe_speed_str(speed),
  169. + (duplex) ? "Full" : "Half");
  170. + else
  171. + netdev_info(priv->netdev, "port %d link down\n", port);
  172. +}
  173. +
  174. +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
  175. +{
  176. + mt7620_print_link_state(priv, port, priv->link[port],
  177. + priv->phy->speed[port],
  178. + (priv->phy->duplex[port] == DUPLEX_FULL));
  179. +}
  180. --- /dev/null
  181. +++ b/drivers/net/ethernet/mediatek/soc_mt7620.c
  182. @@ -0,0 +1,334 @@
  183. +/* This program is free software; you can redistribute it and/or modify
  184. + * it under the terms of the GNU General Public License as published by
  185. + * the Free Software Foundation; version 2 of the License
  186. + *
  187. + * This program is distributed in the hope that it will be useful,
  188. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  189. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  190. + * GNU General Public License for more details.
  191. + *
  192. + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  193. + * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  194. + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  195. + */
  196. +
  197. +#include <linux/module.h>
  198. +#include <linux/platform_device.h>
  199. +#include <linux/if_vlan.h>
  200. +#include <linux/of_net.h>
  201. +
  202. +#include <asm/mach-ralink/ralink_regs.h>
  203. +
  204. +#include <mt7620.h>
  205. +#include "mtk_eth_soc.h"
  206. +#include "gsw_mt7620.h"
  207. +#include "mt7530.h"
  208. +#include "mdio.h"
  209. +
  210. +#define MT7620A_CDMA_CSG_CFG 0x400
  211. +#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
  212. +#define MT7621_CDMP_IG_CTRL (MT7620A_CDMA_CSG_CFG + 0x00)
  213. +#define MT7621_CDMP_EG_CTRL (MT7620A_CDMA_CSG_CFG + 0x04)
  214. +#define MT7620A_RESET_FE BIT(21)
  215. +#define MT7621_RESET_FE BIT(6)
  216. +#define MT7620A_RESET_ESW BIT(23)
  217. +#define MT7620_L4_VALID BIT(23)
  218. +#define MT7621_L4_VALID BIT(24)
  219. +
  220. +#define MT7620_TX_DMA_UDF BIT(15)
  221. +#define MT7621_TX_DMA_UDF BIT(19)
  222. +#define TX_DMA_FP_BMAP ((0xff) << 19)
  223. +
  224. +#define CDMA_ICS_EN BIT(2)
  225. +#define CDMA_UCS_EN BIT(1)
  226. +#define CDMA_TCS_EN BIT(0)
  227. +
  228. +#define GDMA_ICS_EN BIT(22)
  229. +#define GDMA_TCS_EN BIT(21)
  230. +#define GDMA_UCS_EN BIT(20)
  231. +
  232. +/* frame engine counters */
  233. +#define MT7620_REG_MIB_OFFSET 0x1000
  234. +#define MT7620_PPE_AC_BCNT0 (MT7620_REG_MIB_OFFSET + 0x00)
  235. +#define MT7620_GDM1_TX_GBCNT (MT7620_REG_MIB_OFFSET + 0x300)
  236. +#define MT7620_GDM2_TX_GBCNT (MT7620_GDM1_TX_GBCNT + 0x40)
  237. +
  238. +#define MT7621_REG_MIB_OFFSET 0x2000
  239. +#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
  240. +#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
  241. +#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
  242. +
  243. +#define GSW_REG_GDMA1_MAC_ADRL 0x508
  244. +#define GSW_REG_GDMA1_MAC_ADRH 0x50C
  245. +
  246. +#define MT7621_FE_RST_GL (FE_FE_OFFSET + 0x04)
  247. +#define MT7620_FE_INT_STATUS2 (FE_FE_OFFSET + 0x08)
  248. +
  249. +/* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
  250. + * but after test it should be BIT(13).
  251. + */
  252. +#define MT7620_FE_GDM1_AF BIT(13)
  253. +#define MT7621_FE_GDM1_AF BIT(28)
  254. +#define MT7621_FE_GDM2_AF BIT(29)
  255. +
  256. +static const u16 mt7620_reg_table[FE_REG_COUNT] = {
  257. + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
  258. + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
  259. + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
  260. + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
  261. + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
  262. + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
  263. + [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
  264. + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
  265. + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
  266. + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
  267. + [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
  268. + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
  269. + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
  270. + [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
  271. + [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
  272. + [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
  273. + [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
  274. +};
  275. +
  276. +static int mt7620_gsw_config(struct fe_priv *priv)
  277. +{
  278. + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
  279. +
  280. + /* is the mt7530 internal or external */
  281. + if (priv->mii_bus && priv->mii_bus->phy_map[0x1f]) {
  282. + mt7530_probe(priv->device, gsw->base, NULL, 0);
  283. + mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
  284. + } else {
  285. + mt7530_probe(priv->device, gsw->base, NULL, 1);
  286. + }
  287. +
  288. + return 0;
  289. +}
  290. +
  291. +static void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
  292. +{
  293. + struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
  294. + unsigned long flags;
  295. +
  296. + spin_lock_irqsave(&priv->page_lock, flags);
  297. + mtk_switch_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
  298. + mtk_switch_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
  299. + GSW_REG_SMACCR0);
  300. + spin_unlock_irqrestore(&priv->page_lock, flags);
  301. +}
  302. +
  303. +static void mt7620_auto_poll(struct mt7620_gsw *gsw)
  304. +{
  305. + int phy;
  306. + int lsb = -1, msb = 0;
  307. +
  308. + for_each_set_bit(phy, &gsw->autopoll, 32) {
  309. + if (lsb < 0)
  310. + lsb = phy;
  311. + msb = phy;
  312. + }
  313. +
  314. + if (lsb == msb)
  315. + lsb--;
  316. +
  317. + mtk_switch_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) |
  318. + (msb << 8) | lsb, ESW_PHY_POLLING);
  319. +}
  320. +
  321. +static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
  322. +{
  323. + struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
  324. + const __be32 *_id = of_get_property(np, "reg", NULL);
  325. + int phy_mode, size, id;
  326. + int shift = 12;
  327. + u32 val, mask = 0;
  328. + int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
  329. +
  330. + if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
  331. + if (_id)
  332. + pr_err("%s: invalid port id %d\n", np->name,
  333. + be32_to_cpu(*_id));
  334. + else
  335. + pr_err("%s: invalid port id\n", np->name);
  336. + return;
  337. + }
  338. +
  339. + id = be32_to_cpu(*_id);
  340. +
  341. + if (id == 4)
  342. + shift = 14;
  343. +
  344. + priv->phy->phy_fixed[id] = of_get_property(np, "mediatek,fixed-link",
  345. + &size);
  346. + if (priv->phy->phy_fixed[id] &&
  347. + (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
  348. + pr_err("%s: invalid fixed link property\n", np->name);
  349. + priv->phy->phy_fixed[id] = NULL;
  350. + return;
  351. + }
  352. +
  353. + phy_mode = of_get_phy_mode(np);
  354. + switch (phy_mode) {
  355. + case PHY_INTERFACE_MODE_RGMII:
  356. + mask = 0;
  357. + break;
  358. + case PHY_INTERFACE_MODE_MII:
  359. + mask = 1;
  360. + break;
  361. + case PHY_INTERFACE_MODE_RMII:
  362. + mask = 2;
  363. + break;
  364. + default:
  365. + dev_err(priv->device, "port %d - invalid phy mode\n", id);
  366. + return;
  367. + }
  368. +
  369. + priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
  370. + if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
  371. + return;
  372. +
  373. + val = rt_sysc_r32(SYSC_REG_CFG1);
  374. + val &= ~(3 << shift);
  375. + val |= mask << shift;
  376. + rt_sysc_w32(val, SYSC_REG_CFG1);
  377. +
  378. + if (priv->phy->phy_fixed[id]) {
  379. + const __be32 *link = priv->phy->phy_fixed[id];
  380. + int tx_fc, rx_fc;
  381. + u32 val = 0;
  382. +
  383. + priv->phy->speed[id] = be32_to_cpup(link++);
  384. + tx_fc = be32_to_cpup(link++);
  385. + rx_fc = be32_to_cpup(link++);
  386. + priv->phy->duplex[id] = be32_to_cpup(link++);
  387. + priv->link[id] = 1;
  388. +
  389. + switch (priv->phy->speed[id]) {
  390. + case SPEED_10:
  391. + val = 0;
  392. + break;
  393. + case SPEED_100:
  394. + val = 1;
  395. + break;
  396. + case SPEED_1000:
  397. + val = 2;
  398. + break;
  399. + default:
  400. + dev_err(priv->device, "invalid link speed: %d\n",
  401. + priv->phy->speed[id]);
  402. + priv->phy->phy_fixed[id] = 0;
  403. + return;
  404. + }
  405. + val = PMCR_SPEED(val);
  406. + val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
  407. + PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
  408. + if (tx_fc)
  409. + val |= PMCR_TX_FC;
  410. + if (rx_fc)
  411. + val |= PMCR_RX_FC;
  412. + if (priv->phy->duplex[id])
  413. + val |= PMCR_DUPLEX;
  414. + mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
  415. + dev_info(priv->device, "using fixed link parameters\n");
  416. + return;
  417. + }
  418. +
  419. + if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
  420. + u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
  421. + PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
  422. +
  423. + mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
  424. + fe_connect_phy_node(priv, priv->phy->phy_node[id]);
  425. + gsw->autopoll |= BIT(id);
  426. + mt7620_auto_poll(gsw);
  427. + return;
  428. + }
  429. +}
  430. +
  431. +static void mt7620_fe_reset(void)
  432. +{
  433. + fe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW);
  434. +}
  435. +
  436. +static void mt7620_rxcsum_config(bool enable)
  437. +{
  438. + if (enable)
  439. + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
  440. + GDMA_TCS_EN | GDMA_UCS_EN),
  441. + MT7620A_GDMA1_FWD_CFG);
  442. + else
  443. + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
  444. + GDMA_TCS_EN | GDMA_UCS_EN),
  445. + MT7620A_GDMA1_FWD_CFG);
  446. +}
  447. +
  448. +static void mt7620_txcsum_config(bool enable)
  449. +{
  450. + if (enable)
  451. + fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
  452. + CDMA_UCS_EN | CDMA_TCS_EN),
  453. + MT7620A_CDMA_CSG_CFG);
  454. + else
  455. + fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
  456. + CDMA_UCS_EN | CDMA_TCS_EN),
  457. + MT7620A_CDMA_CSG_CFG);
  458. +}
  459. +
  460. +static int mt7620_fwd_config(struct fe_priv *priv)
  461. +{
  462. + struct net_device *dev = priv_netdev(priv);
  463. +
  464. + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
  465. +
  466. + mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
  467. + mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
  468. +
  469. + return 0;
  470. +}
  471. +
  472. +static void mt7620_tx_dma(struct fe_tx_dma *txd)
  473. +{
  474. +}
  475. +
  476. +static void mt7620_init_data(struct fe_soc_data *data,
  477. + struct net_device *netdev)
  478. +{
  479. + struct fe_priv *priv = netdev_priv(netdev);
  480. +
  481. + priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
  482. + FE_FLAG_RX_SG_DMA | FE_FLAG_HAS_SWITCH;
  483. +
  484. + netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
  485. + NETIF_F_HW_VLAN_CTAG_TX;
  486. + if (mt7620_get_eco() >= 5)
  487. + netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
  488. + NETIF_F_IPV6_CSUM;
  489. +}
  490. +
  491. +static struct fe_soc_data mt7620_data = {
  492. + .init_data = mt7620_init_data,
  493. + .reset_fe = mt7620_fe_reset,
  494. + .set_mac = mt7620_set_mac,
  495. + .fwd_config = mt7620_fwd_config,
  496. + .tx_dma = mt7620_tx_dma,
  497. + .switch_init = mtk_gsw_init,
  498. + .port_init = mt7620_port_init,
  499. + .reg_table = mt7620_reg_table,
  500. + .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
  501. + .rx_int = RT5350_RX_DONE_INT,
  502. + .tx_int = RT5350_TX_DONE_INT,
  503. + .status_int = MT7620_FE_GDM1_AF,
  504. + .checksum_bit = MT7620_L4_VALID,
  505. + .has_carrier = mt7620_has_carrier,
  506. + .mdio_read = mt7620_mdio_read,
  507. + .mdio_write = mt7620_mdio_write,
  508. + .mdio_adjust_link = mt7620_mdio_link_adjust,
  509. +};
  510. +
  511. +const struct of_device_id of_fe_match[] = {
  512. + { .compatible = "mediatek,mt7620-eth", .data = &mt7620_data },
  513. + {},
  514. +};
  515. +
  516. +MODULE_DEVICE_TABLE(of, of_fe_match);