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MT7620a_MT7530.dts 1.6 KB

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  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. / {
  4. compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
  5. model = "Ralink MT7620a + MT7530 evaluation board";
  6. };
  7. &spi0 {
  8. status = "okay";
  9. m25p80@0 {
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. compatible = "jedec,spi-nor";
  13. reg = <0>;
  14. spi-max-frequency = <10000000>;
  15. partition@0 {
  16. label = "u-boot";
  17. reg = <0x0 0x30000>;
  18. read-only;
  19. };
  20. partition@30000 {
  21. label = "u-boot-env";
  22. reg = <0x30000 0x10000>;
  23. read-only;
  24. };
  25. factory: partition@40000 {
  26. label = "factory";
  27. reg = <0x40000 0x10000>;
  28. read-only;
  29. };
  30. partition@50000 {
  31. label = "firmware";
  32. reg = <0x50000 0x7b0000>;
  33. };
  34. };
  35. };
  36. &pinctrl {
  37. state_default: pinctrl0 {
  38. gpio {
  39. ralink,group = "i2c", "uartf";
  40. ralink,function = "gpio";
  41. };
  42. };
  43. };
  44. &ethernet {
  45. status = "okay";
  46. pinctrl-names = "default";
  47. pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
  48. mediatek,portmap = "llllw";
  49. port@5 {
  50. status = "okay";
  51. mediatek,fixed-link = <1000 1 1 1>;
  52. phy-mode = "rgmii";
  53. };
  54. mdio-bus {
  55. status = "okay";
  56. phy0: ethernet-phy@0 {
  57. reg = <0>;
  58. phy-mode = "rgmii";
  59. };
  60. phy1: ethernet-phy@1 {
  61. reg = <1>;
  62. phy-mode = "rgmii";
  63. };
  64. phy2: ethernet-phy@2 {
  65. reg = <2>;
  66. phy-mode = "rgmii";
  67. };
  68. phy3: ethernet-phy@3 {
  69. reg = <3>;
  70. phy-mode = "rgmii";
  71. };
  72. phy4: ethernet-phy@4 {
  73. reg = <4>;
  74. phy-mode = "rgmii";
  75. };
  76. phy1f: ethernet-phy@1f {
  77. reg = <0x1f>;
  78. phy-mode = "rgmii";
  79. };
  80. };
  81. };
  82. &gsw {
  83. mediatek,port4 = "gmac";
  84. mediatek,mt7530 = <1>;
  85. };
  86. &pcie {
  87. status = "okay";
  88. };
  89. &ehci {
  90. status = "okay";
  91. };
  92. &ohci {
  93. status = "okay";
  94. };