WIZFI630A.dts 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185
  1. /dts-v1/;
  2. #include "rt5350.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. / {
  5. compatible = "wizfi630a", "ralink,rt5350-soc";
  6. model = "WIZnet WizFi630A";
  7. chosen {
  8. bootargs = "console=ttyS1,115200";
  9. };
  10. gpio-export {
  11. compatible = "gpio-export";
  12. #size-cells = <0>;
  13. };
  14. gpio-leds {
  15. compatible = "gpio-leds";
  16. run {
  17. label = "wizfi630a::run";
  18. gpios = <&gpio0 1 1>;
  19. };
  20. wps {
  21. label = "wizfi630a::wps";
  22. gpios = <&gpio0 20 1>;
  23. };
  24. uart1 {
  25. label = "wizfi630a::uart1";
  26. gpios = <&gpio0 18 1>;
  27. };
  28. uart2 {
  29. label = "wizfi630a::uart2";
  30. gpios = <&gpio0 21 1>;
  31. };
  32. };
  33. gpio-keys-polled {
  34. compatible = "gpio-keys-polled";
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. poll-interval = <20>;
  38. reset {
  39. label = "reset";
  40. gpios = <&gpio0 17 1>;
  41. linux,code = <KEY_RESTART>;
  42. };
  43. wps {
  44. label = "wps";
  45. gpios = <&gpio0 0 1>;
  46. linux,code = <KEY_WPS_BUTTON>;
  47. };
  48. scm1 {
  49. label = "SCM1";
  50. gpios = <&gpio0 19 1>;
  51. linux,code = <BTN_0>;
  52. };
  53. scm2 {
  54. label = "SCM2";
  55. gpios = <&gpio0 2 1>;
  56. linux,code = <BTN_1>;
  57. };
  58. };
  59. };
  60. &gpio1 {
  61. status = "okay";
  62. };
  63. &spi0 {
  64. status = "okay";
  65. m25p80@0 {
  66. #address-cells = <1>;
  67. #size-cells = <1>;
  68. compatible = "jedec,spi-nor";
  69. reg = <0>;
  70. spi-max-frequency = <10000000>;
  71. partition@0 {
  72. #size-cells = <1>;
  73. label = "uboot";
  74. reg = <0x0 0x30000>;
  75. read-only;
  76. };
  77. partition@30000 {
  78. #size-cells = <1>;
  79. label = "uboot-env";
  80. reg = <0x30000 0x10000>;
  81. read-only;
  82. };
  83. factory: partition@40000 {
  84. #size-cells = <1>;
  85. label = "factory";
  86. reg = <0x40000 0x10000>;
  87. read-only;
  88. };
  89. partition@50000 {
  90. #size-cells = <1>;
  91. label = "firmware";
  92. reg = <0x50000 0xfb0000>;
  93. };
  94. };
  95. };
  96. &uart {
  97. compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
  98. reg = <0x500 0x100>;
  99. resets = <&rstctrl 12>;
  100. reset-names = "uart";
  101. interrupt-parent = <&intc>;
  102. interrupts = <5>;
  103. reg-shift = <2>;
  104. pinctrl-names = "default";
  105. pinctrl-0 = <&uartf_pins>;
  106. status = "okay";
  107. };
  108. &uartlite {
  109. compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
  110. reg = <0xc00 0x100>;
  111. resets = <&rstctrl 19>;
  112. reset-names = "uartl";
  113. interrupt-parent = <&intc>;
  114. interrupts = <12>;
  115. reg-shift = <2>;
  116. pinctrl-names = "default";
  117. pinctrl-0 = <&uartlite_pins>;
  118. };
  119. &pinctrl {
  120. state_default: pinctrl0 {
  121. gpio {
  122. ralink,group = "i2c", "jtag" ;
  123. ralink,function = "gpio";
  124. };
  125. };
  126. uartf_gpio_pins: uartf_gpio {
  127. uartf_gpio {
  128. ralink,group = "uartf";
  129. ralink,function = "uartf";
  130. };
  131. };
  132. uartlite_pins: uartlite {
  133. uart {
  134. ralink,group = "uartlite";
  135. ralink,function = "uartlite";
  136. };
  137. };
  138. };
  139. &ethernet {
  140. mtd-mac-address = <&factory 0x4>;
  141. };
  142. &esw {
  143. mediatek,portmap = <0x17>;
  144. };
  145. &wmac {
  146. ralink,mtd-eeprom = <&factory 0>;
  147. };
  148. &ehci {
  149. status = "okay";
  150. };
  151. &ohci {
  152. status = "okay";
  153. };