MZK-750DHP.dts 1.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129
  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. / {
  5. compatible = "ralink,mt7620a-soc";
  6. model = "Planex MZK-750DHP";
  7. gpio-leds {
  8. compatible = "gpio-leds";
  9. wps {
  10. label = "mzk-750dhp:green:wps";
  11. gpios = <&gpio2 15 1>;
  12. };
  13. power {
  14. label = "mzk-750dhp:green:power";
  15. gpios = <&gpio1 15 1>;
  16. };
  17. wlan5g {
  18. label = "mzk-750dhp:green:wlan5g";
  19. gpios = <&gpio1 14 1>;
  20. };
  21. };
  22. gpio-keys-polled {
  23. compatible = "gpio-keys-polled";
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. poll-interval = <20>;
  27. s1 {
  28. label = "reset";
  29. gpios = <&gpio0 1 1>;
  30. linux,code = <KEY_RESTART>;
  31. };
  32. s2 {
  33. label = "wps";
  34. gpios = <&gpio2 19 1>;
  35. linux,code = <KEY_WPS_BUTTON>;
  36. };
  37. };
  38. };
  39. &gpio1 {
  40. status = "okay";
  41. };
  42. &gpio2 {
  43. status = "okay";
  44. };
  45. &spi0 {
  46. status = "okay";
  47. m25p80@0 {
  48. #address-cells = <1>;
  49. #size-cells = <1>;
  50. compatible = "jedec,spi-nor";
  51. reg = <0>;
  52. linux,modalias = "m25p80", "mx25l6405d";
  53. spi-max-frequency = <10000000>;
  54. partition@0 {
  55. label = "u-boot";
  56. reg = <0x0 0x30000>;
  57. read-only;
  58. };
  59. partition@30000 {
  60. label = "u-boot-env";
  61. reg = <0x30000 0x10000>;
  62. read-only;
  63. };
  64. factory: partition@40000 {
  65. label = "factory";
  66. reg = <0x40000 0x10000>;
  67. read-only;
  68. };
  69. partition@50000 {
  70. label = "firmware";
  71. reg = <0x50000 0x7b0000>;
  72. };
  73. };
  74. };
  75. &pinctrl {
  76. state_default: pinctrl0 {
  77. gpio {
  78. ralink,group = "i2c", "spi refclk", "rgmii1", "nd_sd";
  79. ralink,function = "gpio";
  80. };
  81. };
  82. };
  83. &ethernet {
  84. pinctrl-names = "default";
  85. pinctrl-0 = <&ephy_pins>;
  86. mtd-mac-address = <&factory 0x4>;
  87. mediatek,portmap = "llllw";
  88. };
  89. &gsw {
  90. mediatek,port4 = "ephy";
  91. };
  92. &wmac {
  93. ralink,mtd-eeprom = <&factory 0>;
  94. };
  95. &pcie {
  96. status = "okay";
  97. pcie-bridge {
  98. mt76@0,0 {
  99. reg = <0x0000 0 0 0 0>;
  100. device_type = "pci";
  101. mediatek,mtd-eeprom = <&factory 0x8000>;
  102. mediatek,2ghz = <0>;
  103. };
  104. };
  105. };