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020-19-rt2x00-add-support-for-MT7620.patch 73 KB

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  1. From 41977e86c984fcdddb454a3d7887de5d47b5f530 Mon Sep 17 00:00:00 2001
  2. From: Roman Yeryomin <roman@advem.lv>
  3. Date: Tue, 21 Mar 2017 00:43:00 +0100
  4. Subject: [PATCH 19/19] rt2x00: add support for MT7620
  5. Basic support for MT7620 built-in wireless radio was added to
  6. OpenWrt in r41441. It has seen some heavy cleaning and refactoring
  7. since in order to match the Kernel's code quality standards.
  8. Signed-off-by: Roman Yeryomin <roman@advem.lv>
  9. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  10. Acked-by: Stanislaw Gruszka <sgruszka@redhat.com>
  11. Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
  12. ---
  13. drivers/net/wireless/ralink/rt2x00/Kconfig | 2 +-
  14. drivers/net/wireless/ralink/rt2x00/rt2800.h | 177 +++
  15. drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 1421 +++++++++++++++++++++++-
  16. drivers/net/wireless/ralink/rt2x00/rt2800lib.h | 4 +
  17. drivers/net/wireless/ralink/rt2x00/rt2x00.h | 1 +
  18. 5 files changed, 1578 insertions(+), 27 deletions(-)
  19. diff --git a/drivers/net/wireless/ralink/rt2x00/Kconfig b/drivers/net/wireless/ralink/rt2x00/Kconfig
  20. index de62f5dcb62f..a1d1cfe214d2 100644
  21. --- a/drivers/net/wireless/ralink/rt2x00/Kconfig
  22. +++ b/drivers/net/wireless/ralink/rt2x00/Kconfig
  23. @@ -210,7 +210,7 @@ endif
  24. config RT2800SOC
  25. tristate "Ralink WiSoC support"
  26. depends on m
  27. - depends on SOC_RT288X || SOC_RT305X
  28. + depends on SOC_RT288X || SOC_RT305X || SOC_MT7620
  29. select RT2X00_LIB_SOC
  30. select RT2X00_LIB_MMIO
  31. select RT2X00_LIB_CRYPTO
  32. diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800.h b/drivers/net/wireless/ralink/rt2x00/rt2800.h
  33. index fd1dbd956bad..6a8c93fb6a43 100644
  34. --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
  35. +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
  36. @@ -79,6 +79,7 @@
  37. #define RF5372 0x5372
  38. #define RF5390 0x5390
  39. #define RF5392 0x5392
  40. +#define RF7620 0x7620
  41. /*
  42. * Chipset revisions.
  43. @@ -639,6 +640,24 @@
  44. #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
  45. /*
  46. + * MT7620 RF registers (reversed order)
  47. + */
  48. +#define RF_CSR_CFG_DATA_MT7620 FIELD32(0x0000ff00)
  49. +#define RF_CSR_CFG_REGNUM_MT7620 FIELD32(0x03ff0000)
  50. +#define RF_CSR_CFG_WRITE_MT7620 FIELD32(0x00000010)
  51. +#define RF_CSR_CFG_BUSY_MT7620 FIELD32(0x00000001)
  52. +
  53. +/* undocumented registers for calibration of new MAC */
  54. +#define RF_CONTROL0 0x0518
  55. +#define RF_BYPASS0 0x051c
  56. +#define RF_CONTROL1 0x0520
  57. +#define RF_BYPASS1 0x0524
  58. +#define RF_CONTROL2 0x0528
  59. +#define RF_BYPASS2 0x052c
  60. +#define RF_CONTROL3 0x0530
  61. +#define RF_BYPASS3 0x0534
  62. +
  63. +/*
  64. * EFUSE_CSR: RT30x0 EEPROM
  65. */
  66. #define EFUSE_CTRL 0x0580
  67. @@ -1022,6 +1041,16 @@
  68. #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
  69. /*
  70. + * MIMO_PS_CFG: MIMO Power-save Configuration
  71. + */
  72. +#define MIMO_PS_CFG 0x1210
  73. +#define MIMO_PS_CFG_MMPS_BB_EN FIELD32(0x00000001)
  74. +#define MIMO_PS_CFG_MMPS_RX_ANT_NUM FIELD32(0x00000006)
  75. +#define MIMO_PS_CFG_MMPS_RF_EN FIELD32(0x00000008)
  76. +#define MIMO_PS_CFG_RX_STBY_POL FIELD32(0x00000010)
  77. +#define MIMO_PS_CFG_RX_RX_STBY0 FIELD32(0x00000020)
  78. +
  79. +/*
  80. * EDCA_AC0_CFG:
  81. */
  82. #define EDCA_AC0_CFG 0x1300
  83. @@ -1095,6 +1124,12 @@
  84. #define TX_PWR_CFG_0_OFDM6_CH1 FIELD32(0x00f00000)
  85. #define TX_PWR_CFG_0_OFDM12_CH0 FIELD32(0x0f000000)
  86. #define TX_PWR_CFG_0_OFDM12_CH1 FIELD32(0xf0000000)
  87. +/* bits for new 2T devices */
  88. +#define TX_PWR_CFG_0B_1MBS_2MBS FIELD32(0x000000ff)
  89. +#define TX_PWR_CFG_0B_5MBS_11MBS FIELD32(0x0000ff00)
  90. +#define TX_PWR_CFG_0B_6MBS_9MBS FIELD32(0x00ff0000)
  91. +#define TX_PWR_CFG_0B_12MBS_18MBS FIELD32(0xff000000)
  92. +
  93. /*
  94. * TX_PWR_CFG_1:
  95. @@ -1117,6 +1152,11 @@
  96. #define TX_PWR_CFG_1_MCS0_CH1 FIELD32(0x00f00000)
  97. #define TX_PWR_CFG_1_MCS2_CH0 FIELD32(0x0f000000)
  98. #define TX_PWR_CFG_1_MCS2_CH1 FIELD32(0xf0000000)
  99. +/* bits for new 2T devices */
  100. +#define TX_PWR_CFG_1B_24MBS_36MBS FIELD32(0x000000ff)
  101. +#define TX_PWR_CFG_1B_48MBS FIELD32(0x0000ff00)
  102. +#define TX_PWR_CFG_1B_MCS0_MCS1 FIELD32(0x00ff0000)
  103. +#define TX_PWR_CFG_1B_MCS2_MCS3 FIELD32(0xff000000)
  104. /*
  105. * TX_PWR_CFG_2:
  106. @@ -1139,6 +1179,11 @@
  107. #define TX_PWR_CFG_2_MCS8_CH1 FIELD32(0x00f00000)
  108. #define TX_PWR_CFG_2_MCS10_CH0 FIELD32(0x0f000000)
  109. #define TX_PWR_CFG_2_MCS10_CH1 FIELD32(0xf0000000)
  110. +/* bits for new 2T devices */
  111. +#define TX_PWR_CFG_2B_MCS4_MCS5 FIELD32(0x000000ff)
  112. +#define TX_PWR_CFG_2B_MCS6_MCS7 FIELD32(0x0000ff00)
  113. +#define TX_PWR_CFG_2B_MCS8_MCS9 FIELD32(0x00ff0000)
  114. +#define TX_PWR_CFG_2B_MCS10_MCS11 FIELD32(0xff000000)
  115. /*
  116. * TX_PWR_CFG_3:
  117. @@ -1161,6 +1206,11 @@
  118. #define TX_PWR_CFG_3_STBC0_CH1 FIELD32(0x00f00000)
  119. #define TX_PWR_CFG_3_STBC2_CH0 FIELD32(0x0f000000)
  120. #define TX_PWR_CFG_3_STBC2_CH1 FIELD32(0xf0000000)
  121. +/* bits for new 2T devices */
  122. +#define TX_PWR_CFG_3B_MCS12_MCS13 FIELD32(0x000000ff)
  123. +#define TX_PWR_CFG_3B_MCS14 FIELD32(0x0000ff00)
  124. +#define TX_PWR_CFG_3B_STBC_MCS0_MCS1 FIELD32(0x00ff0000)
  125. +#define TX_PWR_CFG_3B_STBC_MCS2_MSC3 FIELD32(0xff000000)
  126. /*
  127. * TX_PWR_CFG_4:
  128. @@ -1175,6 +1225,9 @@
  129. #define TX_PWR_CFG_4_STBC4_CH1 FIELD32(0x000000f0)
  130. #define TX_PWR_CFG_4_STBC6_CH0 FIELD32(0x00000f00)
  131. #define TX_PWR_CFG_4_STBC6_CH1 FIELD32(0x0000f000)
  132. +/* bits for new 2T devices */
  133. +#define TX_PWR_CFG_4B_STBC_MCS4_MCS5 FIELD32(0x000000ff)
  134. +#define TX_PWR_CFG_4B_STBC_MCS6 FIELD32(0x0000ff00)
  135. /*
  136. * TX_PIN_CFG:
  137. @@ -1201,6 +1254,8 @@
  138. #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
  139. #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
  140. #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
  141. +#define TX_PIN_CFG_RFRX_EN FIELD32(0x00100000)
  142. +#define TX_PIN_CFG_RFRX_POL FIELD32(0x00200000)
  143. #define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
  144. #define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
  145. #define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
  146. @@ -1547,6 +1602,95 @@
  147. #define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f)
  148. #define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00)
  149. +/* TXn_RF_GAIN_CORRECT: RF Gain Correction for each RF_ALC[3:2]
  150. + * Unit: 0.1 dB, Range: -3.2 dB to 3.1 dB
  151. + */
  152. +#define TX0_RF_GAIN_CORRECT 0x13a0
  153. +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f)
  154. +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00)
  155. +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000)
  156. +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000)
  157. +
  158. +#define TX1_RF_GAIN_CORRECT 0x13a4
  159. +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f)
  160. +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00)
  161. +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000)
  162. +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000)
  163. +
  164. +/* TXn_RF_GAIN_ATTEN: TXn RF Gain Attenuation Level
  165. + * Format: 7-bit, signed value
  166. + * Unit: 0.5 dB, Range: -20 dB to -5 dB
  167. + */
  168. +#define TX0_RF_GAIN_ATTEN 0x13a8
  169. +#define TX0_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f)
  170. +#define TX0_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00)
  171. +#define TX0_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000)
  172. +#define TX0_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000)
  173. +#define TX1_RF_GAIN_ATTEN 0x13ac
  174. +#define TX1_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f)
  175. +#define TX1_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00)
  176. +#define TX1_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000)
  177. +#define TX1_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000)
  178. +
  179. +/* TX_ALC_CFG_0: TX Automatic Level Control Configuration 0
  180. + * TX_ALC_LIMIT_n: TXn upper limit
  181. + * TX_ALC_CH_INIT_n: TXn channel initial transmission gain
  182. + * Unit: 0.5 dB, Range: 0 to 23.5 dB
  183. + */
  184. +#define TX_ALC_CFG_0 0x13b0
  185. +#define TX_ALC_CFG_0_CH_INIT_0 FIELD32(0x0000003f)
  186. +#define TX_ALC_CFG_0_CH_INIT_1 FIELD32(0x00003f00)
  187. +#define TX_ALC_CFG_0_LIMIT_0 FIELD32(0x003f0000)
  188. +#define TX_ALC_CFG_0_LIMIT_1 FIELD32(0x3f000000)
  189. +
  190. +/* TX_ALC_CFG_1: TX Automatic Level Control Configuration 1
  191. + * TX_TEMP_COMP: TX Power Temperature Compensation
  192. + * Unit: 0.5 dB, Range: -10 dB to 10 dB
  193. + * TXn_GAIN_FINE: TXn Gain Fine Adjustment
  194. + * Unit: 0.1 dB, Range: -0.8 dB to 0.7 dB
  195. + * RF_TOS_DLY: Sets the RF_TOS_EN assertion delay after
  196. + * deassertion of PA_PE.
  197. + * Unit: 0.25 usec
  198. + * TXn_RF_GAIN_ATTEN: TXn RF gain attentuation selector
  199. + * RF_TOS_TIMEOUT: time-out value for RF_TOS_ENABLE
  200. + * deassertion if RF_TOS_DONE is missing.
  201. + * Unit: 0.25 usec
  202. + * RF_TOS_ENABLE: TX offset calibration enable
  203. + * ROS_BUSY_EN: RX offset calibration busy enable
  204. + */
  205. +#define TX_ALC_CFG_1 0x13b4
  206. +#define TX_ALC_CFG_1_TX_TEMP_COMP FIELD32(0x0000003f)
  207. +#define TX_ALC_CFG_1_TX0_GAIN_FINE FIELD32(0x00000f00)
  208. +#define TX_ALC_CFG_1_TX1_GAIN_FINE FIELD32(0x0000f000)
  209. +#define TX_ALC_CFG_1_RF_TOS_DLY FIELD32(0x00070000)
  210. +#define TX_ALC_CFG_1_TX0_RF_GAIN_ATTEN FIELD32(0x00300000)
  211. +#define TX_ALC_CFG_1_TX1_RF_GAIN_ATTEN FIELD32(0x00c00000)
  212. +#define TX_ALC_CFG_1_RF_TOS_TIMEOUT FIELD32(0x3f000000)
  213. +#define TX_ALC_CFG_1_RF_TOS_ENABLE FIELD32(0x40000000)
  214. +#define TX_ALC_CFG_1_ROS_BUSY_EN FIELD32(0x80000000)
  215. +
  216. +/* TXn_BB_GAIN_ATTEN: TXn RF Gain Attenuation Level
  217. + * Format: 5-bit signed values
  218. + * Unit: 0.5 dB, Range: -8 dB to 7 dB
  219. + */
  220. +#define TX0_BB_GAIN_ATTEN 0x13c0
  221. +#define TX0_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f)
  222. +#define TX0_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00)
  223. +#define TX0_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000)
  224. +#define TX0_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000)
  225. +#define TX1_BB_GAIN_ATTEN 0x13c4
  226. +#define TX1_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f)
  227. +#define TX1_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00)
  228. +#define TX1_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000)
  229. +#define TX1_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000)
  230. +
  231. +/* TX_ALC_VGA3: TX Automatic Level Correction Variable Gain Amplifier 3 */
  232. +#define TX_ALC_VGA3 0x13c8
  233. +#define TX_ALC_VGA3_TX0_ALC_VGA3 FIELD32(0x0000001f)
  234. +#define TX_ALC_VGA3_TX1_ALC_VGA3 FIELD32(0x00001f00)
  235. +#define TX_ALC_VGA3_TX0_ALC_VGA2 FIELD32(0x001f0000)
  236. +#define TX_ALC_VGA3_TX1_ALC_VGA2 FIELD32(0x1f000000)
  237. +
  238. /* TX_PWR_CFG_7 */
  239. #define TX_PWR_CFG_7 0x13d4
  240. #define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f)
  241. @@ -1555,6 +1699,10 @@
  242. #define TX_PWR_CFG_7_MCS7_CH0 FIELD32(0x000f0000)
  243. #define TX_PWR_CFG_7_MCS7_CH1 FIELD32(0x00f00000)
  244. #define TX_PWR_CFG_7_MCS7_CH2 FIELD32(0x0f000000)
  245. +/* bits for new 2T devices */
  246. +#define TX_PWR_CFG_7B_54MBS FIELD32(0x000000ff)
  247. +#define TX_PWR_CFG_7B_MCS7 FIELD32(0x00ff0000)
  248. +
  249. /* TX_PWR_CFG_8 */
  250. #define TX_PWR_CFG_8 0x13d8
  251. @@ -1564,12 +1712,17 @@
  252. #define TX_PWR_CFG_8_MCS23_CH0 FIELD32(0x000f0000)
  253. #define TX_PWR_CFG_8_MCS23_CH1 FIELD32(0x00f00000)
  254. #define TX_PWR_CFG_8_MCS23_CH2 FIELD32(0x0f000000)
  255. +/* bits for new 2T devices */
  256. +#define TX_PWR_CFG_8B_MCS15 FIELD32(0x000000ff)
  257. +
  258. /* TX_PWR_CFG_9 */
  259. #define TX_PWR_CFG_9 0x13dc
  260. #define TX_PWR_CFG_9_STBC7_CH0 FIELD32(0x0000000f)
  261. #define TX_PWR_CFG_9_STBC7_CH1 FIELD32(0x000000f0)
  262. #define TX_PWR_CFG_9_STBC7_CH2 FIELD32(0x00000f00)
  263. +/* bits for new 2T devices */
  264. +#define TX_PWR_CFG_9B_STBC_MCS7 FIELD32(0x000000ff)
  265. /*
  266. * RX_FILTER_CFG: RX configuration register.
  267. @@ -2137,11 +2290,14 @@ struct mac_iveiv_entry {
  268. #define RFCSR1_TX1_PD FIELD8(0x20)
  269. #define RFCSR1_RX2_PD FIELD8(0x40)
  270. #define RFCSR1_TX2_PD FIELD8(0x80)
  271. +#define RFCSR1_TX2_EN_MT7620 FIELD8(0x02)
  272. /*
  273. * RFCSR 2:
  274. */
  275. #define RFCSR2_RESCAL_EN FIELD8(0x80)
  276. +#define RFCSR2_RX2_EN_MT7620 FIELD8(0x02)
  277. +#define RFCSR2_TX2_EN_MT7620 FIELD8(0x20)
  278. /*
  279. * RFCSR 3:
  280. @@ -2160,6 +2316,12 @@ struct mac_iveiv_entry {
  281. #define RFCSR3_BIT5 FIELD8(0x20)
  282. /*
  283. + * RFCSR 4:
  284. + * VCOCAL_EN used by MT7620
  285. + */
  286. +#define RFCSR4_VCOCAL_EN FIELD8(0x80)
  287. +
  288. +/*
  289. * FRCSR 5:
  290. */
  291. #define RFCSR5_R1 FIELD8(0x0c)
  292. @@ -2214,6 +2376,7 @@ struct mac_iveiv_entry {
  293. */
  294. #define RFCSR13_TX_POWER FIELD8(0x1f)
  295. #define RFCSR13_DR0 FIELD8(0xe0)
  296. +#define RFCSR13_RDIV_MT7620 FIELD8(0x03)
  297. /*
  298. * RFCSR 15:
  299. @@ -2224,6 +2387,8 @@ struct mac_iveiv_entry {
  300. * RFCSR 16:
  301. */
  302. #define RFCSR16_TXMIXER_GAIN FIELD8(0x07)
  303. +#define RFCSR16_RF_PLL_FREQ_SEL_MT7620 FIELD8(0x0F)
  304. +#define RFCSR16_SDM_MODE_MT7620 FIELD8(0xE0)
  305. /*
  306. * RFCSR 17:
  307. @@ -2236,6 +2401,8 @@ struct mac_iveiv_entry {
  308. /* RFCSR 18 */
  309. #define RFCSR18_XO_TUNE_BYPASS FIELD8(0x40)
  310. +/* RFCSR 19 */
  311. +#define RFCSR19_K FIELD8(0x03)
  312. /*
  313. * RFCSR 20:
  314. @@ -2246,11 +2413,14 @@ struct mac_iveiv_entry {
  315. * RFCSR 21:
  316. */
  317. #define RFCSR21_RX_LO2_EN FIELD8(0x08)
  318. +#define RFCSR21_BIT1 FIELD8(0x01)
  319. +#define RFCSR21_BIT8 FIELD8(0x80)
  320. /*
  321. * RFCSR 22:
  322. */
  323. #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
  324. +#define RFCSR22_FREQPLAN_D_MT7620 FIELD8(0x07)
  325. /*
  326. * RFCSR 23:
  327. @@ -2273,6 +2443,11 @@ struct mac_iveiv_entry {
  328. #define RFCSR27_R4 FIELD8(0x40)
  329. /*
  330. + * RFCSR 28:
  331. + */
  332. +#define RFCSR28_CH11_HT40 FIELD8(0x04)
  333. +
  334. +/*
  335. * RFCSR 29:
  336. */
  337. #define RFCSR29_ADC6_TEST FIELD8(0x01)
  338. @@ -2333,6 +2508,7 @@ struct mac_iveiv_entry {
  339. */
  340. #define RFCSR42_BIT1 FIELD8(0x01)
  341. #define RFCSR42_BIT4 FIELD8(0x08)
  342. +#define RFCSR42_TX2_EN_MT7620 FIELD8(0x40)
  343. /*
  344. * RFCSR 49:
  345. @@ -2435,6 +2611,7 @@ enum rt2800_eeprom_word {
  346. EEPROM_TSSI_BOUND_BG5,
  347. EEPROM_TXPOWER_A1,
  348. EEPROM_TXPOWER_A2,
  349. + EEPROM_TXPOWER_INIT,
  350. EEPROM_TSSI_BOUND_A1,
  351. EEPROM_TSSI_BOUND_A2,
  352. EEPROM_TSSI_BOUND_A3,
  353. diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  354. index 8d00c599e47a..201b12ed90c6 100644
  355. --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  356. +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  357. @@ -59,6 +59,9 @@
  358. rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  359. #define WAIT_FOR_RFCSR(__dev, __reg) \
  360. rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  361. +#define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
  362. + rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
  363. + (__reg))
  364. #define WAIT_FOR_RF(__dev, __reg) \
  365. rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  366. #define WAIT_FOR_MCU(__dev, __reg) \
  367. @@ -150,19 +153,56 @@ static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
  368. * Wait until the RFCSR becomes available, afterwards we
  369. * can safely write the new data into the register.
  370. */
  371. - if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  372. - reg = 0;
  373. - rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
  374. - rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  375. - rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
  376. - rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  377. + switch (rt2x00dev->chip.rt) {
  378. + case RT6352:
  379. + if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
  380. + reg = 0;
  381. + rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
  382. + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
  383. + word);
  384. + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
  385. + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
  386. +
  387. + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  388. + }
  389. + break;
  390. - rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  391. + default:
  392. + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  393. + reg = 0;
  394. + rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
  395. + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  396. + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
  397. + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  398. +
  399. + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  400. + }
  401. + break;
  402. }
  403. mutex_unlock(&rt2x00dev->csr_mutex);
  404. }
  405. +static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
  406. + const unsigned int reg, const u8 value)
  407. +{
  408. + rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
  409. +}
  410. +
  411. +static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
  412. + const unsigned int reg, const u8 value)
  413. +{
  414. + rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
  415. + rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
  416. +}
  417. +
  418. +static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
  419. + const unsigned int reg, const u8 value)
  420. +{
  421. + rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
  422. + rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
  423. +}
  424. +
  425. static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
  426. const unsigned int word, u8 *value)
  427. {
  428. @@ -178,22 +218,48 @@ static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
  429. * doesn't become available in time, reg will be 0xffffffff
  430. * which means we return 0xff to the caller.
  431. */
  432. - if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  433. - reg = 0;
  434. - rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  435. - rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
  436. - rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  437. + switch (rt2x00dev->chip.rt) {
  438. + case RT6352:
  439. + if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
  440. + reg = 0;
  441. + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
  442. + word);
  443. + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
  444. + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
  445. - rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  446. + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  447. - WAIT_FOR_RFCSR(rt2x00dev, &reg);
  448. - }
  449. + WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
  450. + }
  451. - *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
  452. + *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
  453. + break;
  454. +
  455. + default:
  456. + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  457. + reg = 0;
  458. + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  459. + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
  460. + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  461. +
  462. + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  463. +
  464. + WAIT_FOR_RFCSR(rt2x00dev, &reg);
  465. + }
  466. +
  467. + *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
  468. + break;
  469. + }
  470. mutex_unlock(&rt2x00dev->csr_mutex);
  471. }
  472. +static void rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
  473. + const unsigned int reg, u8 *value)
  474. +{
  475. + rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)), value);
  476. +}
  477. +
  478. static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
  479. const unsigned int word, const u32 value)
  480. {
  481. @@ -250,6 +316,7 @@ static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
  482. [EEPROM_TSSI_BOUND_BG5] = 0x003b,
  483. [EEPROM_TXPOWER_A1] = 0x003c,
  484. [EEPROM_TXPOWER_A2] = 0x0053,
  485. + [EEPROM_TXPOWER_INIT] = 0x0068,
  486. [EEPROM_TSSI_BOUND_A1] = 0x006a,
  487. [EEPROM_TSSI_BOUND_A2] = 0x006b,
  488. [EEPROM_TSSI_BOUND_A3] = 0x006c,
  489. @@ -524,6 +591,7 @@ void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
  490. break;
  491. case RT5592:
  492. + case RT6352:
  493. *txwi_size = TXWI_DESC_SIZE_5WORDS;
  494. *rxwi_size = RXWI_DESC_SIZE_6WORDS;
  495. break;
  496. @@ -2810,7 +2878,8 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
  497. rt2800_rfcsr_write(rt2x00dev, 59,
  498. r59_nonbt_rev[idx]);
  499. } else if (rt2x00_rt(rt2x00dev, RT5390) ||
  500. - rt2x00_rt(rt2x00dev, RT5392)) {
  501. + rt2x00_rt(rt2x00dev, RT5392) ||
  502. + rt2x00_rt(rt2x00dev, RT6352)) {
  503. static const char r59_non_bt[] = {0x8f, 0x8f,
  504. 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
  505. 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
  506. @@ -3104,6 +3173,242 @@ static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
  507. rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
  508. }
  509. +static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
  510. + struct ieee80211_conf *conf,
  511. + struct rf_channel *rf,
  512. + struct channel_info *info)
  513. +{
  514. + struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
  515. + u8 rx_agc_fc, tx_agc_fc;
  516. + u8 rfcsr;
  517. +
  518. + /* Frequeny plan setting */
  519. + /* Rdiv setting (set 0x03 if Xtal==20)
  520. + * R13[1:0]
  521. + */
  522. + rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
  523. + rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
  524. + rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
  525. + rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
  526. +
  527. + /* N setting
  528. + * R20[7:0] in rf->rf1
  529. + * R21[0] always 0
  530. + */
  531. + rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
  532. + rfcsr = (rf->rf1 & 0x00ff);
  533. + rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
  534. +
  535. + rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
  536. + rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
  537. + rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
  538. +
  539. + /* K setting (always 0)
  540. + * R16[3:0] (RF PLL freq selection)
  541. + */
  542. + rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
  543. + rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
  544. + rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
  545. +
  546. + /* D setting (always 0)
  547. + * R22[2:0] (D=15, R22[2:0]=<111>)
  548. + */
  549. + rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
  550. + rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
  551. + rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
  552. +
  553. + /* Ksd setting
  554. + * Ksd: R17<7:0> in rf->rf2
  555. + * R18<7:0> in rf->rf3
  556. + * R19<1:0> in rf->rf4
  557. + */
  558. + rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
  559. + rfcsr = rf->rf2;
  560. + rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
  561. +
  562. + rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
  563. + rfcsr = rf->rf3;
  564. + rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
  565. +
  566. + rt2800_rfcsr_read(rt2x00dev, 19, &rfcsr);
  567. + rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
  568. + rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
  569. +
  570. + /* Default: XO=20MHz , SDM mode */
  571. + rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
  572. + rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
  573. + rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
  574. +
  575. + rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
  576. + rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
  577. + rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
  578. +
  579. + rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
  580. + rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
  581. + rt2x00dev->default_ant.tx_chain_num != 1);
  582. + rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
  583. +
  584. + rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
  585. + rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
  586. + rt2x00dev->default_ant.tx_chain_num != 1);
  587. + rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
  588. + rt2x00dev->default_ant.rx_chain_num != 1);
  589. + rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
  590. +
  591. + rt2800_rfcsr_read(rt2x00dev, 42, &rfcsr);
  592. + rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
  593. + rt2x00dev->default_ant.tx_chain_num != 1);
  594. + rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
  595. +
  596. + /* RF for DC Cal BW */
  597. + if (conf_is_ht40(conf)) {
  598. + rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
  599. + rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
  600. + rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
  601. + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
  602. + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
  603. + } else {
  604. + rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
  605. + rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
  606. + rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
  607. + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
  608. + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
  609. + }
  610. +
  611. + if (conf_is_ht40(conf)) {
  612. + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
  613. + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
  614. + } else {
  615. + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
  616. + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
  617. + }
  618. +
  619. + rt2800_rfcsr_read(rt2x00dev, 28, &rfcsr);
  620. + rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
  621. + conf_is_ht40(conf) && (rf->channel == 11));
  622. + rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
  623. +
  624. + if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
  625. + if (conf_is_ht40(conf)) {
  626. + rx_agc_fc = drv_data->rx_calibration_bw40;
  627. + tx_agc_fc = drv_data->tx_calibration_bw40;
  628. + } else {
  629. + rx_agc_fc = drv_data->rx_calibration_bw20;
  630. + tx_agc_fc = drv_data->tx_calibration_bw20;
  631. + }
  632. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rfcsr);
  633. + rfcsr &= (~0x3F);
  634. + rfcsr |= rx_agc_fc;
  635. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
  636. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rfcsr);
  637. + rfcsr &= (~0x3F);
  638. + rfcsr |= rx_agc_fc;
  639. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
  640. + rt2800_rfcsr_read_bank(rt2x00dev, 7, 6, &rfcsr);
  641. + rfcsr &= (~0x3F);
  642. + rfcsr |= rx_agc_fc;
  643. + rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
  644. + rt2800_rfcsr_read_bank(rt2x00dev, 7, 7, &rfcsr);
  645. + rfcsr &= (~0x3F);
  646. + rfcsr |= rx_agc_fc;
  647. + rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
  648. +
  649. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rfcsr);
  650. + rfcsr &= (~0x3F);
  651. + rfcsr |= tx_agc_fc;
  652. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
  653. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rfcsr);
  654. + rfcsr &= (~0x3F);
  655. + rfcsr |= tx_agc_fc;
  656. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
  657. + rt2800_rfcsr_read_bank(rt2x00dev, 7, 58, &rfcsr);
  658. + rfcsr &= (~0x3F);
  659. + rfcsr |= tx_agc_fc;
  660. + rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
  661. + rt2800_rfcsr_read_bank(rt2x00dev, 7, 59, &rfcsr);
  662. + rfcsr &= (~0x3F);
  663. + rfcsr |= tx_agc_fc;
  664. + rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
  665. + }
  666. +}
  667. +
  668. +static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
  669. + struct ieee80211_channel *chan,
  670. + int power_level) {
  671. + u16 eeprom, target_power, max_power;
  672. + u32 mac_sys_ctrl, mac_status;
  673. + u32 reg;
  674. + u8 bbp;
  675. + int i;
  676. +
  677. + /* hardware unit is 0.5dBm, limited to 23.5dBm */
  678. + power_level *= 2;
  679. + if (power_level > 0x2f)
  680. + power_level = 0x2f;
  681. +
  682. + max_power = chan->max_power * 2;
  683. + if (max_power > 0x2f)
  684. + max_power = 0x2f;
  685. +
  686. + rt2800_register_read(rt2x00dev, TX_ALC_CFG_0, &reg);
  687. + rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, power_level);
  688. + rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, power_level);
  689. + rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, max_power);
  690. + rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, max_power);
  691. +
  692. + rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
  693. + if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
  694. + /* init base power by eeprom target power */
  695. + rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_INIT,
  696. + &target_power);
  697. + rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
  698. + rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
  699. + }
  700. + rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
  701. +
  702. + rt2800_register_read(rt2x00dev, TX_ALC_CFG_1, &reg);
  703. + rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
  704. + rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
  705. +
  706. + /* Save MAC SYS CTRL registers */
  707. + rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &mac_sys_ctrl);
  708. + /* Disable Tx/Rx */
  709. + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
  710. + /* Check MAC Tx/Rx idle */
  711. + for (i = 0; i < 10000; i++) {
  712. + rt2800_register_read(rt2x00dev, MAC_STATUS_CFG,
  713. + &mac_status);
  714. + if (mac_status & 0x3)
  715. + usleep_range(50, 200);
  716. + else
  717. + break;
  718. + }
  719. +
  720. + if (i == 10000)
  721. + rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
  722. +
  723. + if (chan->center_freq > 2457) {
  724. + rt2800_bbp_read(rt2x00dev, 30, &bbp);
  725. + bbp = 0x40;
  726. + rt2800_bbp_write(rt2x00dev, 30, bbp);
  727. + rt2800_rfcsr_write(rt2x00dev, 39, 0);
  728. + if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
  729. + rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
  730. + else
  731. + rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
  732. + } else {
  733. + rt2800_bbp_read(rt2x00dev, 30, &bbp);
  734. + bbp = 0x1f;
  735. + rt2800_bbp_write(rt2x00dev, 30, bbp);
  736. + rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
  737. + if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
  738. + rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
  739. + else
  740. + rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
  741. + }
  742. + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
  743. +}
  744. +
  745. static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
  746. const unsigned int word,
  747. const u8 value)
  748. @@ -3228,7 +3533,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
  749. struct channel_info *info)
  750. {
  751. u32 reg;
  752. - unsigned int tx_pin;
  753. + u32 tx_pin;
  754. u8 bbp, rfcsr;
  755. info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
  756. @@ -3273,6 +3578,9 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
  757. case RF5592:
  758. rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
  759. break;
  760. + case RF7620:
  761. + rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
  762. + break;
  763. default:
  764. rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
  765. }
  766. @@ -3347,7 +3655,8 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
  767. if (rf->channel <= 14) {
  768. if (!rt2x00_rt(rt2x00dev, RT5390) &&
  769. - !rt2x00_rt(rt2x00dev, RT5392)) {
  770. + !rt2x00_rt(rt2x00dev, RT5392) &&
  771. + !rt2x00_rt(rt2x00dev, RT6352)) {
  772. if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
  773. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  774. rt2800_bbp_write(rt2x00dev, 75, 0x46);
  775. @@ -3367,7 +3676,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
  776. rt2800_bbp_write(rt2x00dev, 82, 0x94);
  777. else if (rt2x00_rt(rt2x00dev, RT3593))
  778. rt2800_bbp_write(rt2x00dev, 82, 0x82);
  779. - else
  780. + else if (!rt2x00_rt(rt2x00dev, RT6352))
  781. rt2800_bbp_write(rt2x00dev, 82, 0xf2);
  782. if (rt2x00_rt(rt2x00dev, RT3593))
  783. @@ -3388,7 +3697,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
  784. if (rt2x00_rt(rt2x00dev, RT3572))
  785. rt2800_rfcsr_write(rt2x00dev, 8, 0);
  786. - tx_pin = 0;
  787. + rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
  788. switch (rt2x00dev->default_ant.tx_chain_num) {
  789. case 3:
  790. @@ -3437,6 +3746,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
  791. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
  792. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
  793. + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */
  794. rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
  795. @@ -3495,7 +3805,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
  796. usleep_range(1000, 1500);
  797. }
  798. - if (rt2x00_rt(rt2x00dev, RT5592)) {
  799. + if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
  800. rt2800_bbp_write(rt2x00dev, 195, 141);
  801. rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
  802. @@ -4182,6 +4492,128 @@ static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
  803. (unsigned long) regs[i]);
  804. }
  805. +static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
  806. + struct ieee80211_channel *chan,
  807. + int power_level)
  808. +{
  809. + u32 reg, pwreg;
  810. + u16 eeprom;
  811. + u32 data, gdata;
  812. + u8 t, i;
  813. + enum nl80211_band band = chan->band;
  814. + int delta;
  815. +
  816. + /* Warn user if bw_comp is set in EEPROM */
  817. + delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
  818. +
  819. + if (delta)
  820. + rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
  821. + delta);
  822. +
  823. + /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
  824. + * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
  825. + * driver does as well, though it looks kinda wrong.
  826. + * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
  827. + * the hardware has a problem handling 0x20, and as the code initially
  828. + * used a fixed offset between HT20 and HT40 rates they had to work-
  829. + * around that issue and most likely just forgot about it later on.
  830. + * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
  831. + * however, the corresponding EEPROM value is not respected by the
  832. + * vendor driver, so maybe this is rather being taken care of the
  833. + * TXALC and the driver doesn't need to handle it...?
  834. + * Though this is all very awkward, just do as they did, as that's what
  835. + * board vendors expected when they populated the EEPROM...
  836. + */
  837. + for (i = 0; i < 5; i++) {
  838. + rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
  839. + i * 2, &eeprom);
  840. +
  841. + data = eeprom;
  842. +
  843. + t = eeprom & 0x3f;
  844. + if (t == 32)
  845. + t++;
  846. +
  847. + gdata = t;
  848. +
  849. + t = (eeprom & 0x3f00) >> 8;
  850. + if (t == 32)
  851. + t++;
  852. +
  853. + gdata |= (t << 8);
  854. +
  855. + rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
  856. + (i * 2) + 1, &eeprom);
  857. +
  858. + t = eeprom & 0x3f;
  859. + if (t == 32)
  860. + t++;
  861. +
  862. + gdata |= (t << 16);
  863. +
  864. + t = (eeprom & 0x3f00) >> 8;
  865. + if (t == 32)
  866. + t++;
  867. +
  868. + gdata |= (t << 24);
  869. + data |= (eeprom << 16);
  870. +
  871. + if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
  872. + /* HT20 */
  873. + if (data != 0xffffffff)
  874. + rt2800_register_write(rt2x00dev,
  875. + TX_PWR_CFG_0 + (i * 4),
  876. + data);
  877. + } else {
  878. + /* HT40 */
  879. + if (gdata != 0xffffffff)
  880. + rt2800_register_write(rt2x00dev,
  881. + TX_PWR_CFG_0 + (i * 4),
  882. + gdata);
  883. + }
  884. + }
  885. +
  886. + /* Aparently Ralink ran out of space in the BYRATE calibration section
  887. + * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
  888. + * registers. As recent 2T chips use 8-bit instead of 4-bit values for
  889. + * power-offsets more space would be needed. Ralink decided to keep the
  890. + * EEPROM layout untouched and rather have some shared values covering
  891. + * multiple bitrates.
  892. + * Populate the registers not covered by the EEPROM in the same way the
  893. + * vendor driver does.
  894. + */
  895. +
  896. + /* For OFDM 54MBS use value from OFDM 48MBS */
  897. + pwreg = 0;
  898. + rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
  899. + t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
  900. + rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
  901. +
  902. + /* For MCS 7 use value from MCS 6 */
  903. + rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
  904. + t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
  905. + rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
  906. + rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
  907. +
  908. + /* For MCS 15 use value from MCS 14 */
  909. + pwreg = 0;
  910. + rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
  911. + t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
  912. + rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
  913. + rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
  914. +
  915. + /* For STBC MCS 7 use value from STBC MCS 6 */
  916. + pwreg = 0;
  917. + rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
  918. + t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
  919. + rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
  920. + rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
  921. +
  922. + rt2800_config_alc(rt2x00dev, chan, power_level);
  923. +
  924. + /* TODO: temperature compensation code! */
  925. +}
  926. +
  927. /*
  928. * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
  929. * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
  930. @@ -4378,6 +4810,8 @@ static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
  931. {
  932. if (rt2x00_rt(rt2x00dev, RT3593))
  933. rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
  934. + else if (rt2x00_rt(rt2x00dev, RT6352))
  935. + rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
  936. else
  937. rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
  938. }
  939. @@ -4393,6 +4827,7 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
  940. {
  941. u32 tx_pin;
  942. u8 rfcsr;
  943. + unsigned long min_sleep = 0;
  944. /*
  945. * A voltage-controlled oscillator(VCO) is an electronic oscillator
  946. @@ -4431,6 +4866,15 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
  947. rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
  948. rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
  949. rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
  950. + min_sleep = 1000;
  951. + break;
  952. + case RF7620:
  953. + rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
  954. + rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
  955. + rt2800_rfcsr_read(rt2x00dev, 4, &rfcsr);
  956. + rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
  957. + rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
  958. + min_sleep = 2000;
  959. break;
  960. default:
  961. WARN_ONCE(1, "Not supported RF chipet %x for VCO recalibration",
  962. @@ -4438,7 +4882,8 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
  963. return;
  964. }
  965. - usleep_range(1000, 1500);
  966. + if (min_sleep > 0)
  967. + usleep_range(min_sleep, min_sleep * 2);
  968. rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
  969. if (rt2x00dev->rf_channel <= 14) {
  970. @@ -4470,6 +4915,42 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
  971. }
  972. rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
  973. + if (rt2x00_rt(rt2x00dev, RT6352)) {
  974. + if (rt2x00dev->default_ant.tx_chain_num == 1) {
  975. + rt2800_bbp_write(rt2x00dev, 91, 0x07);
  976. + rt2800_bbp_write(rt2x00dev, 95, 0x1A);
  977. + rt2800_bbp_write(rt2x00dev, 195, 128);
  978. + rt2800_bbp_write(rt2x00dev, 196, 0xA0);
  979. + rt2800_bbp_write(rt2x00dev, 195, 170);
  980. + rt2800_bbp_write(rt2x00dev, 196, 0x12);
  981. + rt2800_bbp_write(rt2x00dev, 195, 171);
  982. + rt2800_bbp_write(rt2x00dev, 196, 0x10);
  983. + } else {
  984. + rt2800_bbp_write(rt2x00dev, 91, 0x06);
  985. + rt2800_bbp_write(rt2x00dev, 95, 0x9A);
  986. + rt2800_bbp_write(rt2x00dev, 195, 128);
  987. + rt2800_bbp_write(rt2x00dev, 196, 0xE0);
  988. + rt2800_bbp_write(rt2x00dev, 195, 170);
  989. + rt2800_bbp_write(rt2x00dev, 196, 0x30);
  990. + rt2800_bbp_write(rt2x00dev, 195, 171);
  991. + rt2800_bbp_write(rt2x00dev, 196, 0x30);
  992. + }
  993. +
  994. + if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
  995. + rt2800_bbp_write(rt2x00dev, 75, 0x60);
  996. + rt2800_bbp_write(rt2x00dev, 76, 0x44);
  997. + rt2800_bbp_write(rt2x00dev, 79, 0x1C);
  998. + rt2800_bbp_write(rt2x00dev, 80, 0x0C);
  999. + rt2800_bbp_write(rt2x00dev, 82, 0xB6);
  1000. + }
  1001. +
  1002. + /* On 11A, We should delay and wait RF/BBP to be stable
  1003. + * and the appropriate time should be 1000 micro seconds
  1004. + * 2005/06/05 - On 11G, we also need this delay time.
  1005. + * Otherwise it's difficult to pass the WHQL.
  1006. + */
  1007. + usleep_range(1000, 1500);
  1008. + }
  1009. }
  1010. EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
  1011. @@ -4568,7 +5049,8 @@ static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
  1012. rt2x00_rt(rt2x00dev, RT3593) ||
  1013. rt2x00_rt(rt2x00dev, RT5390) ||
  1014. rt2x00_rt(rt2x00dev, RT5392) ||
  1015. - rt2x00_rt(rt2x00dev, RT5592))
  1016. + rt2x00_rt(rt2x00dev, RT5592) ||
  1017. + rt2x00_rt(rt2x00dev, RT6352))
  1018. vgc = 0x1c + (2 * rt2x00dev->lna_gain);
  1019. else
  1020. vgc = 0x2e + rt2x00dev->lna_gain;
  1021. @@ -4795,7 +5277,8 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
  1022. 0x00000000);
  1023. }
  1024. } else if (rt2x00_rt(rt2x00dev, RT5390) ||
  1025. - rt2x00_rt(rt2x00dev, RT5392)) {
  1026. + rt2x00_rt(rt2x00dev, RT5392) ||
  1027. + rt2x00_rt(rt2x00dev, RT6352)) {
  1028. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
  1029. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  1030. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
  1031. @@ -4805,6 +5288,24 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
  1032. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
  1033. } else if (rt2x00_rt(rt2x00dev, RT5350)) {
  1034. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
  1035. + } else if (rt2x00_rt(rt2x00dev, RT6352)) {
  1036. + rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
  1037. + rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
  1038. + rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
  1039. + rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002);
  1040. + rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F);
  1041. + rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x06060606);
  1042. + rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
  1043. + rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
  1044. + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
  1045. + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
  1046. + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
  1047. + 0x3630363A);
  1048. + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
  1049. + 0x3630363A);
  1050. + rt2800_register_read(rt2x00dev, TX_ALC_CFG_1, &reg);
  1051. + rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
  1052. + rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
  1053. } else {
  1054. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
  1055. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  1056. @@ -5786,6 +6287,231 @@ static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
  1057. rt2800_bbp_write(rt2x00dev, 103, 0xc0);
  1058. }
  1059. +static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
  1060. + const u8 reg, const u8 value)
  1061. +{
  1062. + rt2800_bbp_write(rt2x00dev, 195, reg);
  1063. + rt2800_bbp_write(rt2x00dev, 196, value);
  1064. +}
  1065. +
  1066. +static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
  1067. + const u8 reg, const u8 value)
  1068. +{
  1069. + rt2800_bbp_write(rt2x00dev, 158, reg);
  1070. + rt2800_bbp_write(rt2x00dev, 159, value);
  1071. +}
  1072. +
  1073. +static void rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev,
  1074. + const u8 reg, u8 *value)
  1075. +{
  1076. + rt2800_bbp_write(rt2x00dev, 158, reg);
  1077. + rt2800_bbp_read(rt2x00dev, 159, value);
  1078. +}
  1079. +
  1080. +static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
  1081. +{
  1082. + u8 bbp;
  1083. +
  1084. + /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
  1085. + rt2800_bbp_read(rt2x00dev, 105, &bbp);
  1086. + rt2x00_set_field8(&bbp, BBP105_MLD,
  1087. + rt2x00dev->default_ant.rx_chain_num == 2);
  1088. + rt2800_bbp_write(rt2x00dev, 105, bbp);
  1089. +
  1090. + /* Avoid data loss and CRC errors */
  1091. + rt2800_bbp4_mac_if_ctrl(rt2x00dev);
  1092. +
  1093. + /* Fix I/Q swap issue */
  1094. + rt2800_bbp_read(rt2x00dev, 1, &bbp);
  1095. + bbp |= 0x04;
  1096. + rt2800_bbp_write(rt2x00dev, 1, bbp);
  1097. +
  1098. + /* BBP for G band */
  1099. + rt2800_bbp_write(rt2x00dev, 3, 0x08);
  1100. + rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
  1101. + rt2800_bbp_write(rt2x00dev, 6, 0x08);
  1102. + rt2800_bbp_write(rt2x00dev, 14, 0x09);
  1103. + rt2800_bbp_write(rt2x00dev, 15, 0xFF);
  1104. + rt2800_bbp_write(rt2x00dev, 16, 0x01);
  1105. + rt2800_bbp_write(rt2x00dev, 20, 0x06);
  1106. + rt2800_bbp_write(rt2x00dev, 21, 0x00);
  1107. + rt2800_bbp_write(rt2x00dev, 22, 0x00);
  1108. + rt2800_bbp_write(rt2x00dev, 27, 0x00);
  1109. + rt2800_bbp_write(rt2x00dev, 28, 0x00);
  1110. + rt2800_bbp_write(rt2x00dev, 30, 0x00);
  1111. + rt2800_bbp_write(rt2x00dev, 31, 0x48);
  1112. + rt2800_bbp_write(rt2x00dev, 47, 0x40);
  1113. + rt2800_bbp_write(rt2x00dev, 62, 0x00);
  1114. + rt2800_bbp_write(rt2x00dev, 63, 0x00);
  1115. + rt2800_bbp_write(rt2x00dev, 64, 0x00);
  1116. + rt2800_bbp_write(rt2x00dev, 65, 0x2C);
  1117. + rt2800_bbp_write(rt2x00dev, 66, 0x1C);
  1118. + rt2800_bbp_write(rt2x00dev, 67, 0x20);
  1119. + rt2800_bbp_write(rt2x00dev, 68, 0xDD);
  1120. + rt2800_bbp_write(rt2x00dev, 69, 0x10);
  1121. + rt2800_bbp_write(rt2x00dev, 70, 0x05);
  1122. + rt2800_bbp_write(rt2x00dev, 73, 0x18);
  1123. + rt2800_bbp_write(rt2x00dev, 74, 0x0F);
  1124. + rt2800_bbp_write(rt2x00dev, 75, 0x60);
  1125. + rt2800_bbp_write(rt2x00dev, 76, 0x44);
  1126. + rt2800_bbp_write(rt2x00dev, 77, 0x59);
  1127. + rt2800_bbp_write(rt2x00dev, 78, 0x1E);
  1128. + rt2800_bbp_write(rt2x00dev, 79, 0x1C);
  1129. + rt2800_bbp_write(rt2x00dev, 80, 0x0C);
  1130. + rt2800_bbp_write(rt2x00dev, 81, 0x3A);
  1131. + rt2800_bbp_write(rt2x00dev, 82, 0xB6);
  1132. + rt2800_bbp_write(rt2x00dev, 83, 0x9A);
  1133. + rt2800_bbp_write(rt2x00dev, 84, 0x9A);
  1134. + rt2800_bbp_write(rt2x00dev, 86, 0x38);
  1135. + rt2800_bbp_write(rt2x00dev, 88, 0x90);
  1136. + rt2800_bbp_write(rt2x00dev, 91, 0x04);
  1137. + rt2800_bbp_write(rt2x00dev, 92, 0x02);
  1138. + rt2800_bbp_write(rt2x00dev, 95, 0x9A);
  1139. + rt2800_bbp_write(rt2x00dev, 96, 0x00);
  1140. + rt2800_bbp_write(rt2x00dev, 103, 0xC0);
  1141. + rt2800_bbp_write(rt2x00dev, 104, 0x92);
  1142. + /* FIXME BBP105 owerwrite */
  1143. + rt2800_bbp_write(rt2x00dev, 105, 0x3C);
  1144. + rt2800_bbp_write(rt2x00dev, 106, 0x12);
  1145. + rt2800_bbp_write(rt2x00dev, 109, 0x00);
  1146. + rt2800_bbp_write(rt2x00dev, 134, 0x10);
  1147. + rt2800_bbp_write(rt2x00dev, 135, 0xA6);
  1148. + rt2800_bbp_write(rt2x00dev, 137, 0x04);
  1149. + rt2800_bbp_write(rt2x00dev, 142, 0x30);
  1150. + rt2800_bbp_write(rt2x00dev, 143, 0xF7);
  1151. + rt2800_bbp_write(rt2x00dev, 160, 0xEC);
  1152. + rt2800_bbp_write(rt2x00dev, 161, 0xC4);
  1153. + rt2800_bbp_write(rt2x00dev, 162, 0x77);
  1154. + rt2800_bbp_write(rt2x00dev, 163, 0xF9);
  1155. + rt2800_bbp_write(rt2x00dev, 164, 0x00);
  1156. + rt2800_bbp_write(rt2x00dev, 165, 0x00);
  1157. + rt2800_bbp_write(rt2x00dev, 186, 0x00);
  1158. + rt2800_bbp_write(rt2x00dev, 187, 0x00);
  1159. + rt2800_bbp_write(rt2x00dev, 188, 0x00);
  1160. + rt2800_bbp_write(rt2x00dev, 186, 0x00);
  1161. + rt2800_bbp_write(rt2x00dev, 187, 0x01);
  1162. + rt2800_bbp_write(rt2x00dev, 188, 0x00);
  1163. + rt2800_bbp_write(rt2x00dev, 189, 0x00);
  1164. +
  1165. + rt2800_bbp_write(rt2x00dev, 91, 0x06);
  1166. + rt2800_bbp_write(rt2x00dev, 92, 0x04);
  1167. + rt2800_bbp_write(rt2x00dev, 93, 0x54);
  1168. + rt2800_bbp_write(rt2x00dev, 99, 0x50);
  1169. + rt2800_bbp_write(rt2x00dev, 148, 0x84);
  1170. + rt2800_bbp_write(rt2x00dev, 167, 0x80);
  1171. + rt2800_bbp_write(rt2x00dev, 178, 0xFF);
  1172. + rt2800_bbp_write(rt2x00dev, 106, 0x13);
  1173. +
  1174. + /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
  1175. + rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
  1176. + rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
  1177. + rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
  1178. + rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
  1179. + rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
  1180. + rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
  1181. + rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
  1182. + rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
  1183. + rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
  1184. + rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
  1185. + rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
  1186. + rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
  1187. + rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
  1188. + rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
  1189. + rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
  1190. + rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
  1191. + rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
  1192. + rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
  1193. + rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
  1194. + rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
  1195. + rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
  1196. + rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
  1197. + rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
  1198. + rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
  1199. + rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
  1200. + rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
  1201. + rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
  1202. + rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
  1203. + rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
  1204. + rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
  1205. + rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
  1206. + rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
  1207. + rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
  1208. + rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
  1209. + rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
  1210. + rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
  1211. + rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
  1212. + rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
  1213. + rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
  1214. + rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
  1215. + rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
  1216. + rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
  1217. + rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
  1218. + rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
  1219. + rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
  1220. + rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
  1221. + rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
  1222. + rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
  1223. + rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
  1224. + rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
  1225. + rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
  1226. + rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
  1227. + rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
  1228. + rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
  1229. + rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
  1230. + rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
  1231. + rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
  1232. + rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
  1233. + rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
  1234. + rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
  1235. + rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
  1236. + rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
  1237. + rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
  1238. + rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
  1239. + rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
  1240. + rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
  1241. + rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
  1242. + rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
  1243. + rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
  1244. + rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
  1245. + rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
  1246. + rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
  1247. + rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
  1248. + rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
  1249. + rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
  1250. + rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
  1251. + rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
  1252. + rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
  1253. + rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
  1254. + rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
  1255. + rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
  1256. + rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
  1257. + rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
  1258. +
  1259. + /* BBP for G band DCOC function */
  1260. + rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
  1261. + rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
  1262. + rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
  1263. + rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
  1264. + rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
  1265. + rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
  1266. + rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
  1267. + rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
  1268. + rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
  1269. + rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
  1270. + rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
  1271. + rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
  1272. + rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
  1273. + rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
  1274. + rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
  1275. + rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
  1276. + rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
  1277. + rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
  1278. + rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
  1279. + rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
  1280. +
  1281. + rt2800_bbp4_mac_if_ctrl(rt2x00dev);
  1282. +}
  1283. +
  1284. static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
  1285. {
  1286. unsigned int i;
  1287. @@ -5830,6 +6556,9 @@ static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
  1288. case RT5592:
  1289. rt2800_init_bbp_5592(rt2x00dev);
  1290. return;
  1291. + case RT6352:
  1292. + rt2800_init_bbp_6352(rt2x00dev);
  1293. + break;
  1294. }
  1295. for (i = 0; i < EEPROM_BBP_SIZE; i++) {
  1296. @@ -6901,6 +7630,615 @@ static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
  1297. rt2800_led_open_drain_enable(rt2x00dev);
  1298. }
  1299. +static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
  1300. + bool set_bw, bool is_ht40)
  1301. +{
  1302. + u8 bbp_val;
  1303. +
  1304. + rt2800_bbp_read(rt2x00dev, 21, &bbp_val);
  1305. + bbp_val |= 0x1;
  1306. + rt2800_bbp_write(rt2x00dev, 21, bbp_val);
  1307. + usleep_range(100, 200);
  1308. +
  1309. + if (set_bw) {
  1310. + rt2800_bbp_read(rt2x00dev, 4, &bbp_val);
  1311. + rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
  1312. + rt2800_bbp_write(rt2x00dev, 4, bbp_val);
  1313. + usleep_range(100, 200);
  1314. + }
  1315. +
  1316. + rt2800_bbp_read(rt2x00dev, 21, &bbp_val);
  1317. + bbp_val &= (~0x1);
  1318. + rt2800_bbp_write(rt2x00dev, 21, bbp_val);
  1319. + usleep_range(100, 200);
  1320. +}
  1321. +
  1322. +static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
  1323. +{
  1324. + u8 rf_val;
  1325. +
  1326. + if (btxcal)
  1327. + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
  1328. + else
  1329. + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
  1330. +
  1331. + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
  1332. +
  1333. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 17, &rf_val);
  1334. + rf_val |= 0x80;
  1335. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
  1336. +
  1337. + if (btxcal) {
  1338. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
  1339. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
  1340. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
  1341. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 3, &rf_val);
  1342. + rf_val &= (~0x3F);
  1343. + rf_val |= 0x3F;
  1344. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
  1345. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 4, &rf_val);
  1346. + rf_val &= (~0x3F);
  1347. + rf_val |= 0x3F;
  1348. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
  1349. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
  1350. + } else {
  1351. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
  1352. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
  1353. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
  1354. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 3, &rf_val);
  1355. + rf_val &= (~0x3F);
  1356. + rf_val |= 0x34;
  1357. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
  1358. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 4, &rf_val);
  1359. + rf_val &= (~0x3F);
  1360. + rf_val |= 0x34;
  1361. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
  1362. + }
  1363. +
  1364. + return 0;
  1365. +}
  1366. +
  1367. +static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
  1368. +{
  1369. + unsigned int cnt;
  1370. + u8 bbp_val;
  1371. + char cal_val;
  1372. +
  1373. + rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
  1374. +
  1375. + cnt = 0;
  1376. + do {
  1377. + usleep_range(500, 2000);
  1378. + rt2800_bbp_read(rt2x00dev, 159, &bbp_val);
  1379. + if (bbp_val == 0x02 || cnt == 20)
  1380. + break;
  1381. +
  1382. + cnt++;
  1383. + } while (cnt < 20);
  1384. +
  1385. + rt2800_bbp_dcoc_read(rt2x00dev, 0x39, &bbp_val);
  1386. + cal_val = bbp_val & 0x7F;
  1387. + if (cal_val >= 0x40)
  1388. + cal_val -= 128;
  1389. +
  1390. + return cal_val;
  1391. +}
  1392. +
  1393. +static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
  1394. + bool btxcal)
  1395. +{
  1396. + struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
  1397. + u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
  1398. + u8 filter_target;
  1399. + u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
  1400. + u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
  1401. + int loop = 0, is_ht40, cnt;
  1402. + u8 bbp_val, rf_val;
  1403. + char cal_r32_init, cal_r32_val, cal_diff;
  1404. + u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
  1405. + u8 saverfb5r06, saverfb5r07;
  1406. + u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
  1407. + u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
  1408. + u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
  1409. + u8 saverfb5r58, saverfb5r59;
  1410. + u8 savebbp159r0, savebbp159r2, savebbpr23;
  1411. + u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
  1412. +
  1413. + /* Save MAC registers */
  1414. + rt2800_register_read(rt2x00dev, RF_CONTROL0, &MAC_RF_CONTROL0);
  1415. + rt2800_register_read(rt2x00dev, RF_BYPASS0, &MAC_RF_BYPASS0);
  1416. +
  1417. + /* save BBP registers */
  1418. + rt2800_bbp_read(rt2x00dev, 23, &savebbpr23);
  1419. +
  1420. + rt2800_bbp_dcoc_read(rt2x00dev, 0, &savebbp159r0);
  1421. + rt2800_bbp_dcoc_read(rt2x00dev, 2, &savebbp159r2);
  1422. +
  1423. + /* Save RF registers */
  1424. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 0, &saverfb5r00);
  1425. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 1, &saverfb5r01);
  1426. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 3, &saverfb5r03);
  1427. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 4, &saverfb5r04);
  1428. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 5, &saverfb5r05);
  1429. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &saverfb5r06);
  1430. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &saverfb5r07);
  1431. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 8, &saverfb5r08);
  1432. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 17, &saverfb5r17);
  1433. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 18, &saverfb5r18);
  1434. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 19, &saverfb5r19);
  1435. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 20, &saverfb5r20);
  1436. +
  1437. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 37, &saverfb5r37);
  1438. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 38, &saverfb5r38);
  1439. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 39, &saverfb5r39);
  1440. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 40, &saverfb5r40);
  1441. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 41, &saverfb5r41);
  1442. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 42, &saverfb5r42);
  1443. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 43, &saverfb5r43);
  1444. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 44, &saverfb5r44);
  1445. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 45, &saverfb5r45);
  1446. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 46, &saverfb5r46);
  1447. +
  1448. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &saverfb5r58);
  1449. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &saverfb5r59);
  1450. +
  1451. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 0, &rf_val);
  1452. + rf_val |= 0x3;
  1453. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
  1454. +
  1455. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 1, &rf_val);
  1456. + rf_val |= 0x1;
  1457. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
  1458. +
  1459. + cnt = 0;
  1460. + do {
  1461. + usleep_range(500, 2000);
  1462. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 1, &rf_val);
  1463. + if (((rf_val & 0x1) == 0x00) || (cnt == 40))
  1464. + break;
  1465. + cnt++;
  1466. + } while (cnt < 40);
  1467. +
  1468. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 0, &rf_val);
  1469. + rf_val &= (~0x3);
  1470. + rf_val |= 0x1;
  1471. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
  1472. +
  1473. + /* I-3 */
  1474. + rt2800_bbp_read(rt2x00dev, 23, &bbp_val);
  1475. + bbp_val &= (~0x1F);
  1476. + bbp_val |= 0x10;
  1477. + rt2800_bbp_write(rt2x00dev, 23, bbp_val);
  1478. +
  1479. + do {
  1480. + /* I-4,5,6,7,8,9 */
  1481. + if (loop == 0) {
  1482. + is_ht40 = false;
  1483. +
  1484. + if (btxcal)
  1485. + filter_target = tx_filter_target_20m;
  1486. + else
  1487. + filter_target = rx_filter_target_20m;
  1488. + } else {
  1489. + is_ht40 = true;
  1490. +
  1491. + if (btxcal)
  1492. + filter_target = tx_filter_target_40m;
  1493. + else
  1494. + filter_target = rx_filter_target_40m;
  1495. + }
  1496. +
  1497. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 8, &rf_val);
  1498. + rf_val &= (~0x04);
  1499. + if (loop == 1)
  1500. + rf_val |= 0x4;
  1501. +
  1502. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
  1503. +
  1504. + rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
  1505. +
  1506. + rt2800_rf_lp_config(rt2x00dev, btxcal);
  1507. + if (btxcal) {
  1508. + tx_agc_fc = 0;
  1509. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rf_val);
  1510. + rf_val &= (~0x7F);
  1511. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
  1512. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rf_val);
  1513. + rf_val &= (~0x7F);
  1514. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
  1515. + } else {
  1516. + rx_agc_fc = 0;
  1517. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rf_val);
  1518. + rf_val &= (~0x7F);
  1519. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
  1520. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rf_val);
  1521. + rf_val &= (~0x7F);
  1522. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
  1523. + }
  1524. +
  1525. + usleep_range(1000, 2000);
  1526. +
  1527. + rt2800_bbp_dcoc_read(rt2x00dev, 2, &bbp_val);
  1528. + bbp_val &= (~0x6);
  1529. + rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
  1530. +
  1531. + rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
  1532. +
  1533. + cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
  1534. +
  1535. + rt2800_bbp_dcoc_read(rt2x00dev, 2, &bbp_val);
  1536. + bbp_val |= 0x6;
  1537. + rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
  1538. +do_cal:
  1539. + if (btxcal) {
  1540. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rf_val);
  1541. + rf_val &= (~0x7F);
  1542. + rf_val |= tx_agc_fc;
  1543. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
  1544. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rf_val);
  1545. + rf_val &= (~0x7F);
  1546. + rf_val |= tx_agc_fc;
  1547. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
  1548. + } else {
  1549. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rf_val);
  1550. + rf_val &= (~0x7F);
  1551. + rf_val |= rx_agc_fc;
  1552. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
  1553. + rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rf_val);
  1554. + rf_val &= (~0x7F);
  1555. + rf_val |= rx_agc_fc;
  1556. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
  1557. + }
  1558. +
  1559. + usleep_range(500, 1000);
  1560. +
  1561. + rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
  1562. +
  1563. + cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
  1564. +
  1565. + cal_diff = cal_r32_init - cal_r32_val;
  1566. +
  1567. + if (btxcal)
  1568. + cmm_agc_fc = tx_agc_fc;
  1569. + else
  1570. + cmm_agc_fc = rx_agc_fc;
  1571. +
  1572. + if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
  1573. + ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
  1574. + if (btxcal)
  1575. + tx_agc_fc = 0;
  1576. + else
  1577. + rx_agc_fc = 0;
  1578. + } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
  1579. + if (btxcal)
  1580. + tx_agc_fc++;
  1581. + else
  1582. + rx_agc_fc++;
  1583. + goto do_cal;
  1584. + }
  1585. +
  1586. + if (btxcal) {
  1587. + if (loop == 0)
  1588. + drv_data->tx_calibration_bw20 = tx_agc_fc;
  1589. + else
  1590. + drv_data->tx_calibration_bw40 = tx_agc_fc;
  1591. + } else {
  1592. + if (loop == 0)
  1593. + drv_data->rx_calibration_bw20 = rx_agc_fc;
  1594. + else
  1595. + drv_data->rx_calibration_bw40 = rx_agc_fc;
  1596. + }
  1597. +
  1598. + loop++;
  1599. + } while (loop <= 1);
  1600. +
  1601. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
  1602. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
  1603. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
  1604. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
  1605. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
  1606. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
  1607. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
  1608. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
  1609. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
  1610. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
  1611. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
  1612. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
  1613. +
  1614. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
  1615. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
  1616. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
  1617. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
  1618. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
  1619. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
  1620. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
  1621. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
  1622. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
  1623. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
  1624. +
  1625. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
  1626. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
  1627. +
  1628. + rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
  1629. +
  1630. + rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
  1631. + rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
  1632. +
  1633. + rt2800_bbp_read(rt2x00dev, 4, &bbp_val);
  1634. + rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
  1635. + 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
  1636. + rt2800_bbp_write(rt2x00dev, 4, bbp_val);
  1637. +
  1638. + rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
  1639. + rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
  1640. +}
  1641. +
  1642. +static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
  1643. +{
  1644. + /* Initialize RF central register to default value */
  1645. + rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
  1646. + rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
  1647. + rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
  1648. + rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
  1649. + rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
  1650. + rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
  1651. + rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
  1652. + rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
  1653. + rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
  1654. + rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
  1655. + rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
  1656. + rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
  1657. + rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
  1658. + rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
  1659. + rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
  1660. + rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
  1661. + rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
  1662. + rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
  1663. + rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
  1664. + rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
  1665. + rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
  1666. + rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
  1667. + rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
  1668. + rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
  1669. + rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
  1670. + rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
  1671. + rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
  1672. + rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
  1673. + rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
  1674. + rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
  1675. + rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
  1676. + rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
  1677. + rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
  1678. + rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
  1679. + rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
  1680. + rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
  1681. + rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
  1682. + rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
  1683. + rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
  1684. + rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
  1685. + rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
  1686. + rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
  1687. + rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
  1688. + rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
  1689. +
  1690. + rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
  1691. + if (rt2800_clk_is_20mhz(rt2x00dev))
  1692. + rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
  1693. + else
  1694. + rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
  1695. + rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
  1696. + rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
  1697. + rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
  1698. + rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
  1699. + rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
  1700. + rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
  1701. + rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
  1702. + rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
  1703. + rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
  1704. + rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
  1705. + rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
  1706. + rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
  1707. + rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
  1708. + rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
  1709. + rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
  1710. + rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
  1711. +
  1712. + rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
  1713. + rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
  1714. + rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
  1715. +
  1716. + /* Initialize RF channel register to default value */
  1717. + rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
  1718. + rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
  1719. + rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
  1720. + rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
  1721. + rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
  1722. + rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
  1723. + rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
  1724. + rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
  1725. + rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
  1726. + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
  1727. + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
  1728. + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
  1729. + rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
  1730. + rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
  1731. + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
  1732. + rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
  1733. + rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
  1734. + rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
  1735. + rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
  1736. + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
  1737. + rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
  1738. + rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
  1739. + rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
  1740. + rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
  1741. + rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
  1742. + rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
  1743. + rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
  1744. + rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
  1745. + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
  1746. + rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
  1747. + rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
  1748. + rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
  1749. + rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
  1750. + rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
  1751. + rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
  1752. + rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
  1753. + rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
  1754. + rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
  1755. + rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
  1756. + rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
  1757. + rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
  1758. + rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
  1759. + rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
  1760. + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
  1761. + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
  1762. + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
  1763. + rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
  1764. + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
  1765. + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
  1766. + rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
  1767. + rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
  1768. + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
  1769. + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
  1770. + rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
  1771. + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
  1772. + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
  1773. + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
  1774. + rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
  1775. + rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
  1776. + rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
  1777. +
  1778. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
  1779. +
  1780. + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
  1781. + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
  1782. + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
  1783. + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
  1784. + rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
  1785. + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
  1786. + rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
  1787. + rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
  1788. + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
  1789. + rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
  1790. + rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
  1791. + rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
  1792. + rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
  1793. + rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
  1794. + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
  1795. + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
  1796. + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
  1797. + rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
  1798. + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x69);
  1799. + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
  1800. + rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x20);
  1801. + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
  1802. + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
  1803. + rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
  1804. + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
  1805. + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
  1806. + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
  1807. + rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
  1808. +
  1809. + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
  1810. + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
  1811. + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
  1812. + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
  1813. + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
  1814. + rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
  1815. + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
  1816. + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
  1817. + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
  1818. +
  1819. + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
  1820. + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
  1821. + rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
  1822. + rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
  1823. + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
  1824. + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
  1825. +
  1826. + /* Initialize RF channel register for DRQFN */
  1827. + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
  1828. + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
  1829. + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
  1830. + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
  1831. + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
  1832. + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
  1833. + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
  1834. + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
  1835. +
  1836. + /* Initialize RF DC calibration register to default value */
  1837. + rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
  1838. + rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
  1839. + rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
  1840. + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
  1841. + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
  1842. + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
  1843. + rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
  1844. + rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
  1845. + rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
  1846. + rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
  1847. + rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
  1848. + rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
  1849. + rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
  1850. + rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
  1851. + rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
  1852. + rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
  1853. + rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
  1854. + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
  1855. + rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
  1856. + rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
  1857. + rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
  1858. + rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
  1859. + rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
  1860. + rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
  1861. + rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
  1862. + rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
  1863. + rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
  1864. + rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
  1865. + rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
  1866. + rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
  1867. + rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
  1868. + rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
  1869. + rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
  1870. + rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
  1871. + rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
  1872. + rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
  1873. + rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
  1874. + rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
  1875. + rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
  1876. + rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
  1877. + rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
  1878. + rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
  1879. + rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
  1880. + rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
  1881. + rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
  1882. + rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
  1883. + rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
  1884. + rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
  1885. + rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
  1886. + rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
  1887. + rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
  1888. + rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
  1889. + rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
  1890. + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
  1891. + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
  1892. + rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
  1893. + rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
  1894. + rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
  1895. + rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
  1896. +
  1897. + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
  1898. + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
  1899. + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
  1900. +
  1901. + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
  1902. + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
  1903. +
  1904. + rt2800_bw_filter_calibration(rt2x00dev, true);
  1905. + rt2800_bw_filter_calibration(rt2x00dev, false);
  1906. +}
  1907. +
  1908. static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
  1909. {
  1910. if (rt2800_is_305x_soc(rt2x00dev)) {
  1911. @@ -6941,6 +8279,9 @@ static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
  1912. case RT5592:
  1913. rt2800_init_rfcsr_5592(rt2x00dev);
  1914. break;
  1915. + case RT6352:
  1916. + rt2800_init_rfcsr_6352(rt2x00dev);
  1917. + break;
  1918. }
  1919. }
  1920. @@ -7307,7 +8648,8 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
  1921. */
  1922. if (rt2x00_rt(rt2x00dev, RT3290) ||
  1923. rt2x00_rt(rt2x00dev, RT5390) ||
  1924. - rt2x00_rt(rt2x00dev, RT5392))
  1925. + rt2x00_rt(rt2x00dev, RT5392) ||
  1926. + rt2x00_rt(rt2x00dev, RT6352))
  1927. rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
  1928. else if (rt2x00_rt(rt2x00dev, RT3352))
  1929. rf = RF3322;
  1930. @@ -7339,6 +8681,7 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
  1931. case RF5390:
  1932. case RF5392:
  1933. case RF5592:
  1934. + case RF7620:
  1935. break;
  1936. default:
  1937. rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
  1938. @@ -7746,6 +9089,23 @@ static const struct rf_channel rf_vals_5592_xtal40[] = {
  1939. {196, 83, 0, 12, 1},
  1940. };
  1941. +static const struct rf_channel rf_vals_7620[] = {
  1942. + {1, 0x50, 0x99, 0x99, 1},
  1943. + {2, 0x50, 0x44, 0x44, 2},
  1944. + {3, 0x50, 0xEE, 0xEE, 2},
  1945. + {4, 0x50, 0x99, 0x99, 3},
  1946. + {5, 0x51, 0x44, 0x44, 0},
  1947. + {6, 0x51, 0xEE, 0xEE, 0},
  1948. + {7, 0x51, 0x99, 0x99, 1},
  1949. + {8, 0x51, 0x44, 0x44, 2},
  1950. + {9, 0x51, 0xEE, 0xEE, 2},
  1951. + {10, 0x51, 0x99, 0x99, 3},
  1952. + {11, 0x52, 0x44, 0x44, 0},
  1953. + {12, 0x52, 0xEE, 0xEE, 0},
  1954. + {13, 0x52, 0x99, 0x99, 1},
  1955. + {14, 0x52, 0x33, 0x33, 3},
  1956. +};
  1957. +
  1958. static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  1959. {
  1960. struct hw_mode_spec *spec = &rt2x00dev->spec;
  1961. @@ -7849,6 +9209,11 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  1962. spec->channels = rf_vals_3x;
  1963. break;
  1964. + case RF7620:
  1965. + spec->num_channels = ARRAY_SIZE(rf_vals_7620);
  1966. + spec->channels = rf_vals_7620;
  1967. + break;
  1968. +
  1969. case RF3052:
  1970. case RF3053:
  1971. spec->num_channels = ARRAY_SIZE(rf_vals_3x);
  1972. @@ -7980,6 +9345,7 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  1973. case RF5390:
  1974. case RF5392:
  1975. case RF5592:
  1976. + case RF7620:
  1977. __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
  1978. break;
  1979. }
  1980. @@ -8024,6 +9390,9 @@ static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
  1981. return -ENODEV;
  1982. }
  1983. + if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
  1984. + rt = RT6352;
  1985. +
  1986. rt2x00_set_rt(rt2x00dev, rt, rev);
  1987. return 0;
  1988. diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
  1989. index d9ef260d542a..f357531d9488 100644
  1990. --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
  1991. +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
  1992. @@ -33,6 +33,10 @@
  1993. struct rt2800_drv_data {
  1994. u8 calibration_bw20;
  1995. u8 calibration_bw40;
  1996. + char rx_calibration_bw20;
  1997. + char rx_calibration_bw40;
  1998. + char tx_calibration_bw20;
  1999. + char tx_calibration_bw40;
  2000. u8 bbp25;
  2001. u8 bbp26;
  2002. u8 txmixer_gain_24g;
  2003. diff --git a/drivers/net/wireless/ralink/rt2x00/rt2x00.h b/drivers/net/wireless/ralink/rt2x00/rt2x00.h
  2004. index ce340bfd71a0..8fdd2f9726ee 100644
  2005. --- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h
  2006. +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h
  2007. @@ -174,6 +174,7 @@ struct rt2x00_chip {
  2008. #define RT5390 0x5390 /* 2.4GHz */
  2009. #define RT5392 0x5392 /* 2.4GHz */
  2010. #define RT5592 0x5592
  2011. +#define RT6352 0x6352 /* WSOC 2.4GHz */
  2012. u16 rf;
  2013. u16 rev;
  2014. --
  2015. 2.12.1