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600-10-rt2x00-rt2800lib-add-RFCSR-initialization-for-RT3883.patch 6.0 KB

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  1. From 99c659cf345640fd0f733cbcaf4583cc2c868ec0 Mon Sep 17 00:00:00 2001
  2. From: Gabor Juhos <juhosg@openwrt.org>
  3. Date: Mon, 29 Apr 2013 13:21:48 +0200
  4. Subject: [PATCH] rt2x00: rt2800lib: add RFCSR initialization for RT3883
  5. Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  6. ---
  7. drivers/net/wireless/ralink/rt2x00/rt2800.h | 1 +
  8. drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 141 +++++++++++++++++++++++++++++++
  9. 2 files changed, 142 insertions(+)
  10. --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
  11. +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
  12. @@ -2311,6 +2311,7 @@ struct mac_iveiv_entry {
  13. /*
  14. * RFCSR 2:
  15. */
  16. +#define RFCSR2_RESCAL_BP FIELD8(0x40)
  17. #define RFCSR2_RESCAL_EN FIELD8(0x80)
  18. #define RFCSR2_RX2_EN_MT7620 FIELD8(0x02)
  19. #define RFCSR2_TX2_EN_MT7620 FIELD8(0x20)
  20. --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  21. +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  22. @@ -7685,6 +7685,144 @@ static void rt2800_init_rfcsr_5350(struc
  23. rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
  24. }
  25. +static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev)
  26. +{
  27. + u8 rfcsr;
  28. +
  29. + /* TODO: get the actual ECO value from the SoC */
  30. + const unsigned int eco = 5;
  31. +
  32. + rt2800_rf_init_calibration(rt2x00dev, 2);
  33. +
  34. + rt2800_rfcsr_write(rt2x00dev, 0, 0xe0);
  35. + rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
  36. + rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
  37. + rt2800_rfcsr_write(rt2x00dev, 3, 0x20);
  38. + rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
  39. + rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
  40. + rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
  41. + rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
  42. + rt2800_rfcsr_write(rt2x00dev, 8, 0x5b);
  43. + rt2800_rfcsr_write(rt2x00dev, 9, 0x08);
  44. + rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
  45. + rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
  46. + rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
  47. + rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
  48. + rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
  49. + rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
  50. + rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
  51. +
  52. + /* RFCSR 17 will be initialized later based on the
  53. + * frequency offset stored in the EEPROM
  54. + */
  55. +
  56. + rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
  57. + rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
  58. + rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
  59. + rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
  60. + rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
  61. + rt2800_rfcsr_write(rt2x00dev, 23, 0xc0);
  62. + rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
  63. + rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
  64. + rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
  65. + rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
  66. + rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
  67. + rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
  68. + rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
  69. + rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
  70. + rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
  71. + rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
  72. + rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
  73. + rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
  74. + rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
  75. + rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
  76. + rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
  77. + rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
  78. + rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
  79. + rt2800_rfcsr_write(rt2x00dev, 41, 0x00);
  80. + rt2800_rfcsr_write(rt2x00dev, 42, 0x00);
  81. + rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
  82. + rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
  83. + rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
  84. + rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
  85. + rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
  86. + rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
  87. + rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
  88. + rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
  89. + rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
  90. + rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
  91. + rt2800_rfcsr_write(rt2x00dev, 53, 0x76);
  92. + rt2800_rfcsr_write(rt2x00dev, 54, 0x76);
  93. + rt2800_rfcsr_write(rt2x00dev, 55, 0x76);
  94. + rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
  95. + rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
  96. + rt2800_rfcsr_write(rt2x00dev, 58, 0x00);
  97. + rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
  98. + rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
  99. + rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
  100. + rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
  101. + rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
  102. +
  103. + /* TODO: rx filter calibration? */
  104. +
  105. + rt2800_bbp_write(rt2x00dev, 137, 0x0f);
  106. +
  107. + rt2800_bbp_write(rt2x00dev, 163, 0x9d);
  108. +
  109. + rt2800_bbp_write(rt2x00dev, 105, 0x05);
  110. +
  111. + rt2800_bbp_write(rt2x00dev, 179, 0x02);
  112. + rt2800_bbp_write(rt2x00dev, 180, 0x00);
  113. + rt2800_bbp_write(rt2x00dev, 182, 0x40);
  114. + rt2800_bbp_write(rt2x00dev, 180, 0x01);
  115. + rt2800_bbp_write(rt2x00dev, 182, 0x9c);
  116. +
  117. + rt2800_bbp_write(rt2x00dev, 179, 0x00);
  118. +
  119. + rt2800_bbp_write(rt2x00dev, 142, 0x04);
  120. + rt2800_bbp_write(rt2x00dev, 143, 0x3b);
  121. + rt2800_bbp_write(rt2x00dev, 142, 0x06);
  122. + rt2800_bbp_write(rt2x00dev, 143, 0xa0);
  123. + rt2800_bbp_write(rt2x00dev, 142, 0x07);
  124. + rt2800_bbp_write(rt2x00dev, 143, 0xa1);
  125. + rt2800_bbp_write(rt2x00dev, 142, 0x08);
  126. + rt2800_bbp_write(rt2x00dev, 143, 0xa2);
  127. + rt2800_bbp_write(rt2x00dev, 148, 0xc8);
  128. +
  129. + if (eco == 5) {
  130. + rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
  131. + rt2800_rfcsr_write(rt2x00dev, 33, 0x32);
  132. + }
  133. +
  134. + rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
  135. + rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0);
  136. + rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
  137. + rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
  138. + msleep(1);
  139. + rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
  140. + rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
  141. +
  142. + rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
  143. + rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
  144. + rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
  145. +
  146. + rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
  147. + rfcsr |= 0xc0;
  148. + rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
  149. +
  150. + rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
  151. + rfcsr |= 0x20;
  152. + rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
  153. +
  154. + rt2800_rfcsr_read(rt2x00dev, 46, &rfcsr);
  155. + rfcsr |= 0x20;
  156. + rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
  157. +
  158. + rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
  159. + rfcsr &= ~0xee;
  160. + rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
  161. +}
  162. +
  163. static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
  164. {
  165. rt2800_rf_init_calibration(rt2x00dev, 2);
  166. @@ -8525,6 +8663,9 @@ static void rt2800_init_rfcsr(struct rt2
  167. case RT3390:
  168. rt2800_init_rfcsr_3390(rt2x00dev);
  169. break;
  170. + case RT3883:
  171. + rt2800_init_rfcsr_3883(rt2x00dev);
  172. + break;
  173. case RT3572:
  174. rt2800_init_rfcsr_3572(rt2x00dev);
  175. break;