952-qca955x-enable-ddr-wb-flush.patch 1.3 KB

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  1. --- a/arch/mips/ath79/common.c
  2. +++ b/arch/mips/ath79/common.c
  3. @@ -49,6 +49,8 @@ void ath79_ddr_ctrl_init(void)
  4. if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) {
  5. ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
  6. ath79_ddr_pci_win_base = 0;
  7. + } else if (soc_is_qca953x() || soc_is_qca955x()) {
  8. + ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
  9. } else {
  10. ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
  11. ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
  12. --- a/arch/mips/ath79/irq.c
  13. +++ b/arch/mips/ath79/irq.c
  14. @@ -105,12 +105,12 @@ static void qca955x_ip2_irq_dispatch(str
  15. }
  16. if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
  17. - /* TODO: flush DDR? */
  18. + ath79_ddr_wb_flush(3);
  19. generic_handle_irq(ATH79_IP2_IRQ(0));
  20. }
  21. if (status & QCA955X_EXT_INT_WMAC_ALL) {
  22. - /* TODO: flush DDR? */
  23. + ath79_ddr_wb_flush(4);
  24. generic_handle_irq(ATH79_IP2_IRQ(1));
  25. }
  26. }
  27. @@ -130,17 +130,17 @@ static void qca955x_ip3_irq_dispatch(str
  28. }
  29. if (status & QCA955X_EXT_INT_USB1) {
  30. - /* TODO: flush DDR? */
  31. + ath79_ddr_wb_flush(2);
  32. generic_handle_irq(ATH79_IP3_IRQ(0));
  33. }
  34. if (status & QCA955X_EXT_INT_USB2) {
  35. - /* TODO: flush DDR? */
  36. + ath79_ddr_wb_flush(2);
  37. generic_handle_irq(ATH79_IP3_IRQ(1));
  38. }
  39. if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
  40. - /* TODO: flush DDR? */
  41. + ath79_ddr_wb_flush(3);
  42. generic_handle_irq(ATH79_IP3_IRQ(2));
  43. }
  44. }