ar7100.dtsi 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include <dt-bindings/clock/ath79-clk.h>
  3. #include "ath79.dtsi"
  4. / {
  5. compatible = "qca,ar7100";
  6. cpus {
  7. #address-cells = <1>;
  8. #size-cells = <0>;
  9. cpu@0 {
  10. device_type = "cpu";
  11. compatible = "mips,mips24Kc";
  12. clocks = <&pll ATH79_CLK_CPU>;
  13. reg = <0>;
  14. };
  15. };
  16. ahb {
  17. apb {
  18. ddr_ctrl: memory-controller@18000000 {
  19. compatible = "qca,ar7100-ddr-controller";
  20. reg = <0x18000000 0x100>;
  21. #qca,ddr-wb-channel-cells = <1>;
  22. };
  23. uart: uart@18020000 {
  24. compatible = "ns16550a";
  25. reg = <0x18020000 0x20>;
  26. interrupts = <3>;
  27. clocks = <&pll ATH79_CLK_AHB>;
  28. clock-names = "uart";
  29. reg-io-width = <4>;
  30. reg-shift = <2>;
  31. no-loopback-test;
  32. status = "disabled";
  33. };
  34. usb_phy: usb-phy@18030000 {
  35. compatible = "qca,ar7100-usb-phy";
  36. reg = <0x18030000 0x10>;
  37. reset-names = "usb-phy", "usb-host", "usb-ohci-dll";
  38. resets = <&rst 4>, <&rst 5>, <&rst 6>;
  39. #phy-cells = <0>;
  40. status = "disabled";
  41. };
  42. gpio: gpio@18040000 {
  43. compatible = "qca,ar7100-gpio";
  44. reg = <0x18040000 0x30>;
  45. interrupts = <2>;
  46. ngpios = <16>;
  47. gpio-controller;
  48. #gpio-cells = <2>;
  49. interrupt-controller;
  50. #interrupt-cells = <2>;
  51. };
  52. pll: pll-controller@18050000 {
  53. compatible = "qca,ar7100-pll", "syscon";
  54. reg = <0x18050000 0x20>;
  55. clock-names = "ref";
  56. /* The board must provides the ref clock */
  57. #clock-cells = <1>;
  58. clock-output-names = "cpu", "ddr", "ahb";
  59. };
  60. wdt: wdt@18060008 {
  61. compatible = "qca,ar7130-wdt";
  62. reg = <0x18060008 0x8>;
  63. interrupts = <4>;
  64. clocks = <&pll ATH79_CLK_AHB>;
  65. clock-names = "wdt";
  66. };
  67. pci_intc: interrupt-controller@18060018 {
  68. compatible = "qca,ar7100-misc-intc";
  69. reg = <0x18060018 0x4>;
  70. interrupt-parent = <&cpuintc>;
  71. interrupts = <2>;
  72. interrupt-controller;
  73. #interrupt-cells = <1>;
  74. };
  75. rst: reset-controller@18060024 {
  76. compatible = "qca,ar7100-reset";
  77. reg = <0x18060024 0x4>;
  78. #reset-cells = <1>;
  79. };
  80. pcie0: pcie-controller@17010000 {
  81. compatible = "qca,ar7100-pci";
  82. #address-cells = <3>;
  83. #size-cells = <2>;
  84. bus-range = <0x0 0x0>;
  85. reg = <0x17010000 0x100>;
  86. reg-names = "cfg_base";
  87. ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000 /* pci memory */
  88. 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
  89. interrupt-parent = <&pci_intc>;
  90. interrupts = <4>;
  91. #interrupt-cells = <1>;
  92. interrupt-map-mask = <0xf800 0 0 0>;
  93. interrupt-map = <0x8800 0 0 0 &pci_intc 0
  94. 0x9000 0 0 0 &pci_intc 1
  95. 0x9800 0 0 0 &pci_intc 2>;
  96. status = "disabled";
  97. };
  98. };
  99. };
  100. usb2: usb@1b000000 {
  101. compatible = "generic-ehci";
  102. reg = <0x1b000000 0x1000>;
  103. interrupt-parent = <&cpuintc>;
  104. interrupts = <3>;
  105. phy-names = "usb-phy";
  106. phys = <&usb_phy>;
  107. has-synopsys-hc-bug;
  108. status = "disabled";
  109. };
  110. usb1: usb@1c000000 {
  111. compatible = "generic-ohci";
  112. reg = <0x1c000000 0x1000>;
  113. interrupt-parent = <&miscintc>;
  114. interrupts = <6>;
  115. phy-names = "usb-phy";
  116. phys = <&usb_phy>;
  117. status = "disabled";
  118. };
  119. spi: spi@1f000000 {
  120. compatible = "qca,ar7100-spi";
  121. reg = <0x1f000000 0x10>;
  122. clocks = <&pll ATH79_CLK_AHB>;
  123. clock-names = "ahb";
  124. #address-cells = <1>;
  125. #size-cells = <0>;
  126. status = "disabled";
  127. };
  128. };
  129. &cpuintc {
  130. qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
  131. qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
  132. <&ddr_ctrl 0>, <&ddr_ctrl 1>;
  133. };
  134. &miscintc {
  135. compatible = "qca,ar7100-misc-intc";
  136. };
  137. &eth0 {
  138. compatible = "qca,ar7100-eth", "syscon";
  139. reg = <0x19000000 0x200
  140. 0x18070000 0x4>;
  141. pll-data = <0x00110000 0x00001099 0x00991099>;
  142. pll-reg = <0x4 0x10 17>;
  143. pll-handle = <&pll>;
  144. phy-mode = "rgmii";
  145. resets = <&rst 9>;
  146. reset-names = "mac";
  147. qca,mac-idx = <0>;
  148. };
  149. &mdio1 {
  150. builtin-switch;
  151. };
  152. &eth1 {
  153. compatible = "qca,ar7100-eth", "syscon";
  154. reg = <0x1a000000 0x200
  155. 0x18070004 0x4>;
  156. pll-data = <0x00110000 0x00001099 0x00991099>;
  157. pll-reg = <0x4 0x14 19>;
  158. pll-handle = <&pll>;
  159. phy-mode = "rgmii";
  160. resets = <&rst 13>;
  161. reset-names = "mac";
  162. qca,mac-idx = <1>;
  163. };