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ar7161_dlink_dir-825-b1.dts 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /dts-v1/;
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include "ar7100.dtsi"
  6. / {
  7. compatible = "dlink,dir-825-b1", "qca,ar7161";
  8. model = "D-Link DIR825B1";
  9. aliases {
  10. led-boot = &orange_power;
  11. led-failsafe = &orange_power;
  12. led-running = &blue_power;
  13. led-upgrade = &orange_power;
  14. };
  15. chosen {
  16. bootargs = "console=ttyS0,115200";
  17. };
  18. extosc: ref {
  19. compatible = "fixed-clock";
  20. #clock-cells = <0>;
  21. clock-output-names = "ref";
  22. clock-frequency = <40000000>;
  23. };
  24. leds {
  25. compatible = "gpio-leds";
  26. blue_usb {
  27. label = "d-link:blue:usb";
  28. gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
  29. trigger-sources = <&usb_ochi_port>, <&usb_echi_port>;
  30. linux,default-trigger = "usbport";
  31. };
  32. orange_power: orange_power {
  33. label = "d-link:orange:power";
  34. gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
  35. default-state = "on";
  36. };
  37. blue_power: blue_power {
  38. label = "d-link:blue:power";
  39. gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
  40. };
  41. blue_wps {
  42. label = "d-link:blue:wps";
  43. gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
  44. };
  45. orange_planet {
  46. label = "d-link:orange:planet";
  47. gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
  48. };
  49. blue_planet {
  50. label = "d-link:blue:planet";
  51. gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
  52. };
  53. };
  54. ath9k-leds {
  55. compatible = "gpio-leds";
  56. wlan2g {
  57. label = "d-link:blue:wlan2g";
  58. gpios = <&ath9k0 5 GPIO_ACTIVE_LOW>;
  59. linux,default-trigger = "phy0tpt";
  60. };
  61. wlan5g {
  62. label = "d-link:blue:wlan5g";
  63. gpios = <&ath9k1 5 GPIO_ACTIVE_LOW>;
  64. linux,default-trigger = "phy1tpt";
  65. };
  66. };
  67. keys {
  68. compatible = "gpio-keys-polled";
  69. poll-interval = <20>;
  70. reset {
  71. label = "reset";
  72. linux,code = <KEY_RESTART>;
  73. gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
  74. debounce-interval = <60>;
  75. };
  76. wps {
  77. label = "wps";
  78. linux,code = <KEY_WPS_BUTTON>;
  79. gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
  80. debounce-interval = <60>;
  81. };
  82. };
  83. rtl8366s {
  84. compatible = "realtek,rtl8366s";
  85. gpio-sda = <&gpio 5 GPIO_ACTIVE_HIGH>;
  86. gpio-sck = <&gpio 7 GPIO_ACTIVE_HIGH>;
  87. realtek,initvals = <0x06 0x0108>;
  88. mdio-bus {
  89. #address-cells = <1>;
  90. #size-cells = <0>;
  91. status = "okay";
  92. phy-mask = <0x10>;
  93. phy4: ethernet-phy@4 {
  94. reg = <4>;
  95. phy-mode = "rgmii";
  96. };
  97. };
  98. };
  99. };
  100. &usb1 {
  101. #address-cells = <1>;
  102. #size-cells = <0>;
  103. status = "okay";
  104. usb_ochi_port: port@1 {
  105. reg = <1>;
  106. #trigger-source-cells = <0>;
  107. };
  108. };
  109. &usb2 {
  110. #address-cells = <1>;
  111. #size-cells = <0>;
  112. status = "okay";
  113. usb_echi_port: port@1 {
  114. reg = <1>;
  115. #trigger-source-cells = <0>;
  116. };
  117. };
  118. &usb_phy {
  119. status = "okay";
  120. };
  121. &pcie0 {
  122. status = "okay";
  123. ath9k0: wifi@0,11 {
  124. compatible = "pci168c,0029";
  125. reg = <0x8800 0 0 0 0>;
  126. qca,no-eeprom;
  127. #gpio-cells = <2>;
  128. gpio-controller;
  129. };
  130. ath9k1: wifi@0,12 {
  131. compatible = "pci168c,0029";
  132. reg = <0x9000 0 0 0 0>;
  133. qca,no-eeprom;
  134. #gpio-cells = <2>;
  135. gpio-controller;
  136. };
  137. };
  138. &uart {
  139. status = "okay";
  140. };
  141. &pll {
  142. clocks = <&extosc>;
  143. };
  144. &spi {
  145. status = "okay";
  146. num-cs = <1>;
  147. flash@0 {
  148. compatible = "jedec,spi-nor";
  149. reg = <0>;
  150. spi-max-frequency = <25000000>;
  151. partitions {
  152. compatible = "fixed-partitions";
  153. #address-cells = <1>;
  154. #size-cells = <1>;
  155. partition@0 {
  156. label = "u-boot";
  157. reg = <0x000000 0x040000>;
  158. read-only;
  159. };
  160. partition@40000 {
  161. label = "config";
  162. reg = <0x040000 0x010000>;
  163. read-only;
  164. };
  165. partition@50000 {
  166. compatible = "denx,uimage";
  167. label = "firmware";
  168. reg = <0x050000 0x610000>;
  169. };
  170. caldata: partition@60000 {
  171. label = "caldata";
  172. reg = <0x660000 0x010000>;
  173. read-only;
  174. };
  175. partition@670000 {
  176. label = "unknown";
  177. reg = <0x670000 0x190000>;
  178. read-only;
  179. };
  180. };
  181. };
  182. };
  183. &eth0 {
  184. status = "okay";
  185. pll-data = <0x11110000 0x00001099 0x00991099>;
  186. fixed-link {
  187. speed = <1000>;
  188. full-duplex;
  189. };
  190. };
  191. &eth1 {
  192. status = "okay";
  193. pll-data = <0x11110000 0x00001099 0x00991099>;
  194. phy-handle = <&phy4>;
  195. };