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ar9330.dtsi 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include <dt-bindings/clock/ath79-clk.h>
  3. #include "ath79.dtsi"
  4. / {
  5. compatible = "qca,ar9330";
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. cpus {
  9. #address-cells = <1>;
  10. #size-cells = <0>;
  11. cpu@0 {
  12. device_type = "cpu";
  13. compatible = "mips,mips24Kc";
  14. clocks = <&pll ATH79_CLK_CPU>;
  15. reg = <0>;
  16. };
  17. };
  18. chosen {
  19. bootargs = "console=ttyATH0,115200";
  20. };
  21. ahb {
  22. apb {
  23. ddr_ctrl: memory-controller@18000000 {
  24. compatible = "qca,ar7240-ddr-controller";
  25. reg = <0x18000000 0x100>;
  26. #qca,ddr-wb-channel-cells = <1>;
  27. };
  28. uart: uart@18020000 {
  29. compatible = "qca,ar9330-uart";
  30. reg = <0x18020000 0x14>;
  31. interrupts = <3>;
  32. clocks = <&pll ATH79_CLK_REF>;
  33. clock-names = "uart";
  34. status = "disabled";
  35. };
  36. gpio: gpio@18040000 {
  37. compatible = "qca,ar7100-gpio";
  38. reg = <0x18040000 0x34>;
  39. interrupts = <2>;
  40. ngpios = <30>;
  41. gpio-controller;
  42. #gpio-cells = <2>;
  43. interrupt-controller;
  44. #interrupt-cells = <2>;
  45. status = "disabled";
  46. };
  47. pinmux: pinmux@18040028 {
  48. compatible = "pinctrl-single";
  49. reg = <0x18040028 0x8>;
  50. pinctrl-single,bit-per-mux;
  51. pinctrl-single,register-width = <32>;
  52. pinctrl-single,function-mask = <0x1>;
  53. #pinctrl-cells = <2>;
  54. jtag_disable_pins: pinmux_jtag_disable_pins {
  55. pinctrl-single,bits = <0x0 0x1 0x1>;
  56. };
  57. switch_led_disable_pins: pinmux_switch_led_disable_pins {
  58. pinctrl-single,bits = <0x0 0x0 0xf8>;
  59. };
  60. };
  61. pll: pll-controller@18050000 {
  62. compatible = "qca,ar9330-pll";
  63. reg = <0x18050000 0x100>;
  64. #clock-cells = <1>;
  65. };
  66. wdt: wdt@18060008 {
  67. compatible = "qca,ar7130-wdt";
  68. reg = <0x18060008 0x8>;
  69. interrupts = <4>;
  70. clocks = <&pll ATH79_CLK_AHB>;
  71. clock-names = "wdt";
  72. };
  73. rst: reset-controller@1806001c {
  74. compatible = "qca,ar7100-reset";
  75. reg = <0x1806001c 0x4>;
  76. #reset-cells = <1>;
  77. };
  78. };
  79. usb: usb@1b000000 {
  80. compatible = "chipidea,usb2";
  81. reg = <0x1b000000 0x200>;
  82. interrupts = <3>;
  83. resets = <&rst 5>;
  84. reset-names = "usb-host";
  85. phy-names = "usb-phy";
  86. phys = <&usb_phy>;
  87. status = "disabled";
  88. };
  89. spi: spi@1f000000 {
  90. compatible = "qca,ar7100-spi";
  91. reg = <0x1f000000 0x10>;
  92. clocks = <&pll ATH79_CLK_AHB>;
  93. clock-names = "ahb";
  94. #address-cells = <1>;
  95. #size-cells = <0>;
  96. status = "disabled";
  97. };
  98. gmac: gmac@18070000 {
  99. compatible = "qca,ar9330-gmac";
  100. reg = <0x18070000 0x4>;
  101. };
  102. wmac: wmac@18100000 {
  103. compatible = "qca,ar9330-wmac";
  104. reg = <0x18100000 0x20000>;
  105. interrupts = <2>;
  106. status = "disabled";
  107. };
  108. };
  109. usb_phy: usb-phy {
  110. compatible = "qca,ar7200-usb-phy";
  111. reset-names = "usb-phy", "usb-suspend-override";
  112. resets = <&rst 4>, <&rst 3>;
  113. #phy-cells = <0>;
  114. status = "disabled";
  115. };
  116. };
  117. &cpuintc {
  118. qca,ddr-wb-channel-interrupts = <2>, <3>;
  119. qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
  120. };
  121. &eth0 {
  122. compatible = "qca,ar9330-eth", "syscon";
  123. pll-data = <0x00110000 0x00001099 0x00991099>;
  124. resets = <&rst 9>;
  125. reset-names = "mac";
  126. phy-mode = "mii";
  127. phy-handle = <&swphy4>;
  128. };
  129. &mdio1 {
  130. status = "okay";
  131. compatible = "qca,ar9330-mdio";
  132. resets = <&rst 23>;
  133. reset-names = "mdio";
  134. builtin-switch;
  135. builtin_switch: switch0@1f {
  136. compatible = "qca,ar7240sw";
  137. reg = <0x1f>;
  138. resets = <&rst 8>;
  139. reset-names = "switch";
  140. qca,mib-poll-interval = <500>;
  141. mdio-bus {
  142. #address-cells = <1>;
  143. #size-cells = <0>;
  144. swphy4: ethernet-phy@4 {
  145. reg = <4>;
  146. phy-mode = "mii";
  147. };
  148. };
  149. };
  150. };
  151. &eth1 {
  152. compatible = "qca,ar9330-eth", "syscon";
  153. pll-data = <0x00110000 0x00001099 0x00991099>;
  154. phy-mode = "gmii";
  155. resets = <&rst 13>;
  156. reset-names = "mac";
  157. fixed-link {
  158. speed = <1000>;
  159. full-duplex;
  160. };
  161. };