ar9344_tplink_tl-wdr4300.dtsi 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include <dt-bindings/gpio/gpio.h>
  3. #include <dt-bindings/input/input.h>
  4. #include "ar9344.dtsi"
  5. / {
  6. aliases {
  7. led-boot = &system;
  8. led-failsafe = &system;
  9. led-running = &system;
  10. led-upgrade = &system;
  11. };
  12. leds {
  13. compatible = "gpio-leds";
  14. usb1 {
  15. label = "tp-link:green:usb1";
  16. gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
  17. trigger-sources = <&hub_port1>;
  18. linux,default-trigger = "usbport";
  19. };
  20. usb2 {
  21. label = "tp-link:green:usb2";
  22. gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
  23. trigger-sources = <&hub_port2>;
  24. linux,default-trigger = "usbport";
  25. };
  26. wlan2g {
  27. label = "tp-link:green:wlan2g";
  28. gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
  29. linux,default-trigger = "phy0tpt";
  30. };
  31. system: system {
  32. label = "tp-link:green:system";
  33. gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
  34. default-state = "on";
  35. };
  36. qss {
  37. label = "tp-link:green:qss";
  38. gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
  39. };
  40. };
  41. ath9k-leds {
  42. compatible = "gpio-leds";
  43. wlan5g {
  44. label = "tp-link:green:wlan5g";
  45. gpios = <&ath9k 0 GPIO_ACTIVE_LOW>;
  46. linux,default-trigger = "phy1tpt";
  47. };
  48. };
  49. keys {
  50. compatible = "gpio-keys-polled";
  51. poll-interval = <20>;
  52. reset {
  53. linux,code = <KEY_RESTART>;
  54. gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
  55. debounce-interval = <60>;
  56. };
  57. wifi {
  58. linux,code = <KEY_RFKILL>;
  59. linux,input-type = <EV_SW>;
  60. gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
  61. debounce-interval = <60>;
  62. };
  63. };
  64. gpio-export {
  65. compatible = "gpio-export";
  66. gpio_usb1_power {
  67. gpio-export,name = "tp-link:power:usb1";
  68. gpio-export,output = <1>;
  69. gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  70. };
  71. gpio_usb2_power {
  72. gpio-export,name = "tp-link:power:usb2";
  73. gpio-export,output = <1>;
  74. gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;
  75. };
  76. gpio_ext_lna0 {
  77. gpio-export,name = "tp-link:ext:lna0";
  78. gpio-export,output = <1>;
  79. gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
  80. };
  81. gpio_ext_lna1 {
  82. gpio-export,name = "tp-link:ext:lna1";
  83. gpio-export,output = <1>;
  84. gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
  85. };
  86. };
  87. };
  88. &ref {
  89. clock-frequency = <40000000>;
  90. };
  91. &uart {
  92. status = "okay";
  93. };
  94. &gpio {
  95. status = "okay";
  96. };
  97. &spi {
  98. num-cs = <1>;
  99. status = "okay";
  100. flash@0 {
  101. compatible = "jedec,spi-nor";
  102. reg = <0>;
  103. spi-max-frequency = <25000000>;
  104. partitions {
  105. compatible = "fixed-partitions";
  106. #address-cells = <1>;
  107. #size-cells = <1>;
  108. uboot: partition@0 {
  109. label = "u-boot";
  110. reg = <0x000000 0x020000>;
  111. read-only;
  112. };
  113. partition@20000 {
  114. compatible = "tplink,firmware";
  115. label = "firmware";
  116. reg = <0x020000 0x7d0000>;
  117. };
  118. art: partition@7f0000 {
  119. label = "art";
  120. reg = <0x7f0000 0x010000>;
  121. read-only;
  122. };
  123. };
  124. };
  125. };
  126. &usb {
  127. #address-cells = <1>;
  128. #size-cells = <0>;
  129. status = "okay";
  130. port@1 {
  131. #address-cells = <1>;
  132. #size-cells = <0>;
  133. reg = <1>;
  134. #trigger-source-cells = <0>;
  135. hub_port1: port@1 {
  136. reg = <1>;
  137. #trigger-source-cells = <0>;
  138. };
  139. hub_port2: port@2 {
  140. reg = <2>;
  141. #trigger-source-cells = <0>;
  142. };
  143. };
  144. };
  145. &usb_phy {
  146. status = "okay";
  147. };
  148. &pcie {
  149. status = "okay";
  150. ath9k: wifi@0,0 {
  151. compatible = "pci168c,0033";
  152. reg = <0x0000 0 0 0 0>;
  153. mtd-mac-address = <&uboot 0x1fc00>;
  154. qca,no-eeprom;
  155. #gpio-cells = <2>;
  156. gpio-controller;
  157. };
  158. };
  159. &wmac {
  160. status = "okay";
  161. mtd-cal-data = <&art 0x1000>;
  162. mtd-mac-address = <&uboot 0x1fc00>;
  163. mtd-mac-address-increment = <(-1)>;
  164. };
  165. &mdio0 {
  166. status = "okay";
  167. phy-mask = <0>;
  168. phy0: ethernet-phy@0 {
  169. reg = <0>;
  170. phy-mode = "rgmii";
  171. qca,ar8327-initvals = <
  172. 0x04 0x07600000 /* PORT0 PAD MODE CTRL */
  173. 0x10 0x80000080 /* POWER_ON_STRIP */
  174. 0x50 0xc737c737 /* LED_CTRL0 */
  175. 0x54 0x00000000 /* LED_CTRL1 */
  176. 0x58 0x00000000 /* LED_CTRL2 */
  177. 0x5c 0x0030c300 /* LED_CTRL3 */
  178. 0x7c 0x0000007e /* PORT0_STATUS */
  179. >;
  180. };
  181. };
  182. &eth0 {
  183. status = "okay";
  184. /* default for ar934x, except for 1000M */
  185. pll-data = <0x06000000 0x00000101 0x00001616>;
  186. mtd-mac-address = <&uboot 0x1fc00>;
  187. phy-mode = "rgmii";
  188. phy-handle = <&phy0>;
  189. };