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qca9557.dtsi 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include <dt-bindings/clock/ath79-clk.h>
  3. #include "ath79.dtsi"
  4. / {
  5. compatible = "qca,qca9557";
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. cpus {
  9. #address-cells = <1>;
  10. #size-cells = <0>;
  11. cpu@0 {
  12. device_type = "cpu";
  13. compatible = "mips,mips74Kc";
  14. clocks = <&pll ATH79_CLK_CPU>;
  15. reg = <0>;
  16. };
  17. };
  18. extosc: ref {
  19. compatible = "fixed-clock";
  20. #clock-cells = <0>;
  21. clock-output-names = "ref";
  22. clock-frequency = <40000000>;
  23. };
  24. ahb {
  25. apb {
  26. ddr_ctrl: memory-controller@18000000 {
  27. compatible = "qca,ar9557-ddr-controller",
  28. "qca,ar7240-ddr-controller";
  29. reg = <0x18000000 0x100>;
  30. #qca,ddr-wb-channel-cells = <1>;
  31. };
  32. uart: uart@18020000 {
  33. compatible = "ns16550a";
  34. reg = <0x18020000 0x20>;
  35. interrupts = <3>;
  36. clocks = <&pll ATH79_CLK_REF>;
  37. clock-names = "uart";
  38. reg-io-width = <4>;
  39. reg-shift = <2>;
  40. no-loopback-test;
  41. status = "disabled";
  42. };
  43. usb_phy0: usb-phy0@18030000 {
  44. compatible ="qca,qca9550-usb-phy", "qca,ar7200-usb-phy";
  45. reg = <0x18030000 4>, <0x18030004 4>;
  46. reset-names = "usb-phy", "usb-suspend-override";
  47. resets = <&rst 4>, <&rst 3>;
  48. #phy-cells = <0>;
  49. status = "disabled";
  50. };
  51. usb_phy1: usb-phy1@18030010 {
  52. compatible = "qca,qca9550-usb-phy", "qca,ar7200-usb-phy";
  53. reg = <0x18030010 4>, <0x18030014 4>;
  54. reset-names = "usb-phy", "usb-suspend-override";
  55. resets = <&rst2 4>, <&rst2 3>;
  56. #phy-cells = <0>;
  57. status = "disabled";
  58. };
  59. gpio: gpio@18040000 {
  60. compatible = "qca,ar9557-gpio",
  61. "qca,ar9340-gpio";
  62. reg = <0x18040000 0x28>;
  63. interrupts = <2>;
  64. ngpios = <24>;
  65. gpio-controller;
  66. #gpio-cells = <2>;
  67. interrupt-controller;
  68. #interrupt-cells = <2>;
  69. };
  70. pinmux: pinmux@1804002c {
  71. compatible = "pinctrl-single";
  72. reg = <0x1804002c 0x44>;
  73. #size-cells = <0>;
  74. pinctrl-single,bit-per-mux;
  75. pinctrl-single,register-width = <32>;
  76. pinctrl-single,function-mask = <0x1>;
  77. #pinctrl-cells = <2>;
  78. jtag_disable_pins: pinmux_jtag_disable_pins {
  79. pinctrl-single,bits = <0x40 0x2 0x2>;
  80. };
  81. };
  82. pll: pll-controller@18050000 {
  83. compatible = "qca,ar9557-pll",
  84. "qca,qca9550-pll", "syscon";
  85. reg = <0x18050000 0x50>;
  86. #clock-cells = <1>;
  87. clock-output-names = "cpu", "ddr", "ahb";
  88. clocks = <&extosc>;
  89. };
  90. wdt: wdt@18060008 {
  91. compatible = "qca,ar7130-wdt";
  92. reg = <0x18060008 0x8>;
  93. interrupts = <4>;
  94. clocks = <&pll ATH79_CLK_AHB>;
  95. clock-names = "wdt";
  96. };
  97. rst: reset-controller@1806001c {
  98. compatible = "qca,qca9550-reset",
  99. "qca,ar7100-reset";
  100. reg = <0x1806001c 0x4>;
  101. #reset-cells = <1>;
  102. interrupt-parent = <&cpuintc>;
  103. intc2: interrupt-controller2 {
  104. compatible = "qca,ar9340-intc";
  105. interrupt-parent = <&cpuintc>;
  106. interrupts = <2>;
  107. interrupt-controller;
  108. #interrupt-cells = <1>;
  109. qca,int-status-addr = <0xac>;
  110. qca,pending-bits = <0xf>, /* wmac */
  111. <0x1f0>; /* pcie rc 0 */
  112. };
  113. intc3: interrupt-controller3 {
  114. compatible = "qca,ar9340-intc";
  115. interrupt-parent = <&cpuintc>;
  116. interrupts = <3>;
  117. interrupt-controller;
  118. #interrupt-cells = <1>;
  119. qca,int-status-addr = <0xac>;
  120. qca,pending-bits = <0x1f000>, /* pcie rc 1 */
  121. <0x1000000>, /* usb1 */
  122. <0x10000000>; /* usb2 */
  123. };
  124. };
  125. rst2: reset-controller@180600c0 {
  126. compatible = "qca,qca9550-reset",
  127. "qca,ar7100-reset",
  128. "simple-bus";
  129. reg = <0x180600c0 0x4>;
  130. #reset-cells = <1>;
  131. };
  132. pcie0: pcie-controller@180c0000 {
  133. compatible = "qcom,ar7240-pci";
  134. #address-cells = <3>;
  135. #size-cells = <2>;
  136. bus-range = <0x0 0x0>;
  137. reg = <0x180c0000 0x1000>, /* CRP */
  138. <0x180f0000 0x100>, /* CTRL */
  139. <0x14000000 0x1000>; /* CFG */
  140. reg-names = "crp_base", "ctrl_base", "cfg_base";
  141. ranges = <0x2000000 0 0x10000000 0x10000000 0 0x02000000 /* pci memory */
  142. 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
  143. interrupt-parent = <&intc2>;
  144. interrupts = <1>;
  145. interrupt-controller;
  146. #interrupt-cells = <1>;
  147. interrupt-map-mask = <0 0 0 1>;
  148. interrupt-map = <0 0 0 0 &pcie0 0>;
  149. status = "disabled";
  150. };
  151. pcie1: pcie-controller@18250000 {
  152. compatible = "qcom,ar7240-pci";
  153. #address-cells = <3>;
  154. #size-cells = <2>;
  155. bus-range = <0x0 0x0>;
  156. reg = <0x18250000 0x1000>, /* CRP */
  157. <0x18280000 0x100>, /* CTRL */
  158. <0x16000000 0x1000>; /* CFG */
  159. reg-names = "crp_base", "ctrl_base", "cfg_base";
  160. ranges = <0x2000000 0 0x12000000 0x12000000 0 0x02000000 /* pci memory */
  161. 0x1000000 0 0x00000000 0x0000001 0 0x000001>; /* io space */
  162. interrupt-parent = <&intc3>;
  163. interrupts = <0>;
  164. interrupt-controller;
  165. #interrupt-cells = <1>;
  166. interrupt-map-mask = <0 0 0 1>;
  167. interrupt-map = <0 0 0 0 &pcie1 0>;
  168. status = "disabled";
  169. };
  170. gmac: gmac@18070000 {
  171. compatible = "qca,qca9550-gmac";
  172. reg = <0x18070000 0x58>;
  173. };
  174. wmac: wmac@18100000 {
  175. compatible = "qca,qca9550-wmac";
  176. reg = <0x18100000 0x10000>;
  177. interrupt-parent = <&intc2>;
  178. interrupts = <0>;
  179. status = "disabled";
  180. };
  181. };
  182. usb0: usb@1b000000 {
  183. compatible = "generic-ehci";
  184. reg = <0x1b000000 0x1fc>;
  185. interrupt-parent = <&intc3>;
  186. interrupts = <1>;
  187. resets = <&rst 5>;
  188. reset-names = "usb-host";
  189. has-transaction-translator;
  190. caps-offset = <0x100>;
  191. phy-names = "usb-phy0";
  192. phys = <&usb_phy0>;
  193. status = "disabled";
  194. };
  195. usb1: usb@1b400000 {
  196. compatible = "generic-ehci";
  197. reg = <0x1b400000 0x1fc>;
  198. interrupt-parent = <&intc3>;
  199. interrupts = <2>;
  200. resets = <&rst2 5>;
  201. reset-names = "usb-host";
  202. has-transaction-translator;
  203. caps-offset = <0x100>;
  204. phy-names = "usb-phy1";
  205. phys = <&usb_phy1>;
  206. status = "disabled";
  207. };
  208. spi: spi@1f000000 {
  209. compatible = "qca,ar9557-spi", "qca,ar7100-spi";
  210. reg = <0x1f000000 0x10>;
  211. clocks = <&pll ATH79_CLK_AHB>;
  212. clock-names = "ahb";
  213. status = "disabled";
  214. #address-cells = <1>;
  215. #size-cells = <0>;
  216. };
  217. };
  218. };
  219. &mdio0 {
  220. compatible = "qca,ar9340-mdio";
  221. };
  222. &eth0 {
  223. compatible = "qca,qca9550-eth", "syscon";
  224. pll-reg = <0 0x28 0>;
  225. pll-handle = <&pll>;
  226. pll-data = <0x16000000 0x00000101 0x00001616>;
  227. phy-mode = "rgmii";
  228. resets = <&rst 9>, <&rst 22>;
  229. reset-names = "mac", "mdio";
  230. };
  231. &mdio1 {
  232. compatible = "qca,ar9340-mdio";
  233. };
  234. &eth1 {
  235. compatible = "qca,qca9550-eth", "syscon";
  236. pll-reg = <0 0x48 0>;
  237. pll-handle = <&pll>;
  238. pll-data = <0x16000000 0x00000101 0x00001616>;
  239. phy-mode = "sgmii";
  240. resets = <&rst 13>, <&rst 23>;
  241. reset-names = "mac", "mdio";
  242. };