300-MIPS-r4k_cache-use-more-efficient-cache-blast.patch 2.2 KB

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  1. From: Ben Menchaca <ben.menchaca@qca.qualcomm.com>
  2. Date: Fri, 7 Jun 2013 18:35:22 -0500
  3. Subject: MIPS: r4k_cache: use more efficient cache blast
  4. Optimize the compiler output for larger cache blast cases that are
  5. common for DMA-based networking.
  6. Signed-off-by: Ben Menchaca <ben.menchaca@qca.qualcomm.com>
  7. Signed-off-by: Felix Fietkau <nbd@nbd.name>
  8. ---
  9. --- a/arch/mips/include/asm/r4kcache.h
  10. +++ b/arch/mips/include/asm/r4kcache.h
  11. @@ -683,16 +683,48 @@ static inline void prot##extra##blast_##
  12. unsigned long end) \
  13. { \
  14. unsigned long lsize = cpu_##desc##_line_size(); \
  15. + unsigned long lsize_2 = lsize * 2; \
  16. + unsigned long lsize_3 = lsize * 3; \
  17. + unsigned long lsize_4 = lsize * 4; \
  18. + unsigned long lsize_5 = lsize * 5; \
  19. + unsigned long lsize_6 = lsize * 6; \
  20. + unsigned long lsize_7 = lsize * 7; \
  21. + unsigned long lsize_8 = lsize * 8; \
  22. unsigned long addr = start & ~(lsize - 1); \
  23. - unsigned long aend = (end - 1) & ~(lsize - 1); \
  24. + unsigned long aend = (end + lsize - 1) & ~(lsize - 1); \
  25. + int lines = (aend - addr) / lsize; \
  26. \
  27. __##pfx##flush_prologue \
  28. \
  29. - while (1) { \
  30. + while (lines >= 8) { \
  31. + prot##cache_op(hitop, addr); \
  32. + prot##cache_op(hitop, addr + lsize); \
  33. + prot##cache_op(hitop, addr + lsize_2); \
  34. + prot##cache_op(hitop, addr + lsize_3); \
  35. + prot##cache_op(hitop, addr + lsize_4); \
  36. + prot##cache_op(hitop, addr + lsize_5); \
  37. + prot##cache_op(hitop, addr + lsize_6); \
  38. + prot##cache_op(hitop, addr + lsize_7); \
  39. + addr += lsize_8; \
  40. + lines -= 8; \
  41. + } \
  42. + \
  43. + if (lines & 0x4) { \
  44. + prot##cache_op(hitop, addr); \
  45. + prot##cache_op(hitop, addr + lsize); \
  46. + prot##cache_op(hitop, addr + lsize_2); \
  47. + prot##cache_op(hitop, addr + lsize_3); \
  48. + addr += lsize_4; \
  49. + } \
  50. + \
  51. + if (lines & 0x2) { \
  52. + prot##cache_op(hitop, addr); \
  53. + prot##cache_op(hitop, addr + lsize); \
  54. + addr += lsize_2; \
  55. + } \
  56. + \
  57. + if (lines & 0x1) { \
  58. prot##cache_op(hitop, addr); \
  59. - if (addr == aend) \
  60. - break; \
  61. - addr += lsize; \
  62. } \
  63. \
  64. __##pfx##flush_epilogue \