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101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch 1.8 KB

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  1. From: William Wu <william.wu@rock-chips.com>
  2. RK3328 has one USB 3.0 OTG controller which uses DWC_USB3
  3. core's general architecture. It can act as static xHCI host
  4. controller, static device controller, USB 3.0/2.0 OTG basing
  5. on ID of USB3.0 PHY.
  6. Signed-off-by: William Wu <william.wu@rock-chips.com>
  7. Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
  8. ---
  9. NOTE: This binding still has issues. From the original thread:
  10. the rk3328 usb3-phy has an issue with detecting any plugin events
  11. after a previous device got removed - see the inno-usb3-phy driver
  12. in the vendor kernel.
  13. The current state is good-enough for enabling the USB3 attached LAN
  14. port of the NanoPi R2S. However, it might explode depending on your
  15. use-case. You've been warned.
  16. ---
  17. arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++
  18. 1 file changed, 27 insertions(+)
  19. --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
  20. +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
  21. @@ -810,6 +810,33 @@
  22. status = "disabled";
  23. };
  24. + usbdrd3: usb@ff600000 {
  25. + compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
  26. + clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
  27. + <&cru ACLK_USB3OTG>;
  28. + clock-names = "ref_clk", "suspend_clk",
  29. + "bus_clk";
  30. + #address-cells = <2>;
  31. + #size-cells = <2>;
  32. + ranges;
  33. + status = "disabled";
  34. +
  35. + usbdrd_dwc3: dwc3@ff600000 {
  36. + compatible = "snps,dwc3";
  37. + reg = <0x0 0xff600000 0x0 0x100000>;
  38. + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  39. + dr_mode = "otg";
  40. + phy_type = "utmi_wide";
  41. + snps,dis_enblslpm_quirk;
  42. + snps,dis-u2-freeclk-exists-quirk;
  43. + snps,dis_u2_susphy_quirk;
  44. + snps,dis_u3_susphy_quirk;
  45. + snps,dis-del-phy-power-chg-quirk;
  46. + snps,dis-tx-ipgap-linecheck-quirk;
  47. + status = "disabled";
  48. + };
  49. + };
  50. +
  51. gic: interrupt-controller@ff811000 {
  52. compatible = "arm,gic-400";
  53. #interrupt-cells = <3>;