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0022-wifi-ath11k-update-hal-srng-regs-for-IPQ5018.patch 4.7 KB

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  1. From 711b80acbdfb9667a9cf8374e13320a6e624ce73 Mon Sep 17 00:00:00 2001
  2. From: Sriram R <quic_srirrama@quicinc.com>
  3. Date: Fri, 2 Dec 2022 23:37:14 +0200
  4. Subject: [PATCH] wifi: ath11k: update hal srng regs for IPQ5018
  5. IPQ5018 hal srng register address & offsets are not
  6. similar to IPQ8074/IPQ6018/QCN9074, hence define a
  7. new set of srng register group data for IPQ5018.
  8. Tested-on: IPQ5018 hw1.0 AHB WLAN.HK.2.6.0.1-00861-QCAHKSWPL_SILICONZ-1
  9. Signed-off-by: Sriram R <quic_srirrama@quicinc.com>
  10. Co-developed-by: Karthikeyan Kathirvel <quic_kathirve@quicinc.com>
  11. Signed-off-by: Karthikeyan Kathirvel <quic_kathirve@quicinc.com>
  12. Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
  13. Link: https://lore.kernel.org/r/20221122132152.17771-6-quic_kathirve@quicinc.com
  14. ---
  15. drivers/net/wireless/ath/ath11k/core.c | 1 +
  16. drivers/net/wireless/ath/ath11k/hw.c | 79 ++++++++++++++++++++++++++
  17. drivers/net/wireless/ath/ath11k/hw.h | 1 +
  18. 3 files changed, 81 insertions(+)
  19. --- a/drivers/net/wireless/ath/ath11k/core.c
  20. +++ b/drivers/net/wireless/ath/ath11k/core.c
  21. @@ -634,6 +634,7 @@ static const struct ath11k_hw_params ath
  22. .max_fft_bins = 1024,
  23. },
  24. .internal_sleep_clock = false,
  25. + .regs = &ipq5018_regs,
  26. .host_ce_config = ath11k_host_ce_config_qcn9074,
  27. .ce_count = CE_CNT_5018,
  28. .target_ce_config = ath11k_target_ce_config_wlan_ipq5018,
  29. --- a/drivers/net/wireless/ath/ath11k/hw.c
  30. +++ b/drivers/net/wireless/ath/ath11k/hw.c
  31. @@ -2645,6 +2645,85 @@ static const struct ath11k_hw_tcl2wbm_rb
  32. },
  33. };
  34. +const struct ath11k_hw_regs ipq5018_regs = {
  35. + /* SW2TCL(x) R0 ring configuration address */
  36. + .hal_tcl1_ring_base_lsb = 0x00000694,
  37. + .hal_tcl1_ring_base_msb = 0x00000698,
  38. + .hal_tcl1_ring_id = 0x0000069c,
  39. + .hal_tcl1_ring_misc = 0x000006a4,
  40. + .hal_tcl1_ring_tp_addr_lsb = 0x000006b0,
  41. + .hal_tcl1_ring_tp_addr_msb = 0x000006b4,
  42. + .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4,
  43. + .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8,
  44. + .hal_tcl1_ring_msi1_base_lsb = 0x000006dc,
  45. + .hal_tcl1_ring_msi1_base_msb = 0x000006e0,
  46. + .hal_tcl1_ring_msi1_data = 0x000006e4,
  47. + .hal_tcl2_ring_base_lsb = 0x000006ec,
  48. + .hal_tcl_ring_base_lsb = 0x0000079c,
  49. +
  50. + /* TCL STATUS ring address */
  51. + .hal_tcl_status_ring_base_lsb = 0x000008a4,
  52. +
  53. + /* REO2SW(x) R0 ring configuration address */
  54. + .hal_reo1_ring_base_lsb = 0x000001ec,
  55. + .hal_reo1_ring_base_msb = 0x000001f0,
  56. + .hal_reo1_ring_id = 0x000001f4,
  57. + .hal_reo1_ring_misc = 0x000001fc,
  58. + .hal_reo1_ring_hp_addr_lsb = 0x00000200,
  59. + .hal_reo1_ring_hp_addr_msb = 0x00000204,
  60. + .hal_reo1_ring_producer_int_setup = 0x00000210,
  61. + .hal_reo1_ring_msi1_base_lsb = 0x00000234,
  62. + .hal_reo1_ring_msi1_base_msb = 0x00000238,
  63. + .hal_reo1_ring_msi1_data = 0x0000023c,
  64. + .hal_reo2_ring_base_lsb = 0x00000244,
  65. + .hal_reo1_aging_thresh_ix_0 = 0x00000564,
  66. + .hal_reo1_aging_thresh_ix_1 = 0x00000568,
  67. + .hal_reo1_aging_thresh_ix_2 = 0x0000056c,
  68. + .hal_reo1_aging_thresh_ix_3 = 0x00000570,
  69. +
  70. + /* REO2SW(x) R2 ring pointers (head/tail) address */
  71. + .hal_reo1_ring_hp = 0x00003028,
  72. + .hal_reo1_ring_tp = 0x0000302c,
  73. + .hal_reo2_ring_hp = 0x00003030,
  74. +
  75. + /* REO2TCL R0 ring configuration address */
  76. + .hal_reo_tcl_ring_base_lsb = 0x000003fc,
  77. + .hal_reo_tcl_ring_hp = 0x00003058,
  78. +
  79. + /* SW2REO ring address */
  80. + .hal_sw2reo_ring_base_lsb = 0x0000013c,
  81. + .hal_sw2reo_ring_hp = 0x00003018,
  82. +
  83. + /* REO CMD ring address */
  84. + .hal_reo_cmd_ring_base_lsb = 0x000000e4,
  85. + .hal_reo_cmd_ring_hp = 0x00003010,
  86. +
  87. + /* REO status address */
  88. + .hal_reo_status_ring_base_lsb = 0x00000504,
  89. + .hal_reo_status_hp = 0x00003070,
  90. +
  91. + /* WCSS relative address */
  92. + .hal_seq_wcss_umac_ce0_src_reg = 0x08400000
  93. + - HAL_IPQ5018_CE_WFSS_REG_BASE,
  94. + .hal_seq_wcss_umac_ce0_dst_reg = 0x08401000
  95. + - HAL_IPQ5018_CE_WFSS_REG_BASE,
  96. + .hal_seq_wcss_umac_ce1_src_reg = 0x08402000
  97. + - HAL_IPQ5018_CE_WFSS_REG_BASE,
  98. + .hal_seq_wcss_umac_ce1_dst_reg = 0x08403000
  99. + - HAL_IPQ5018_CE_WFSS_REG_BASE,
  100. +
  101. + /* WBM Idle address */
  102. + .hal_wbm_idle_link_ring_base_lsb = 0x00000874,
  103. + .hal_wbm_idle_link_ring_misc = 0x00000884,
  104. +
  105. + /* SW2WBM release address */
  106. + .hal_wbm_release_ring_base_lsb = 0x000001ec,
  107. +
  108. + /* WBM2SW release address */
  109. + .hal_wbm0_release_ring_base_lsb = 0x00000924,
  110. + .hal_wbm1_release_ring_base_lsb = 0x0000097c,
  111. +};
  112. +
  113. const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = {
  114. .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM,
  115. .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074,
  116. --- a/drivers/net/wireless/ath/ath11k/hw.h
  117. +++ b/drivers/net/wireless/ath/ath11k/hw.h
  118. @@ -415,6 +415,7 @@ extern const struct ath11k_hw_regs qca63
  119. extern const struct ath11k_hw_regs qcn9074_regs;
  120. extern const struct ath11k_hw_regs wcn6855_regs;
  121. extern const struct ath11k_hw_regs wcn6750_regs;
  122. +extern const struct ath11k_hw_regs ipq5018_regs;
  123. static inline const char *ath11k_bd_ie_type_str(enum ath11k_bd_ie_type type)
  124. {