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- From 69968f88f1770d61cae0febef805fd00d66cf6a1 Mon Sep 17 00:00:00 2001
- From: Sriram R <quic_srirrama@quicinc.com>
- Date: Fri, 2 Dec 2022 23:37:15 +0200
- Subject: [PATCH] wifi: ath11k: add new hw ops for IPQ5018 to get rx dest ring
- hashmap
- The Destination ring control register is different
- for IPQ5018 when compared to IPQ8074/IPQ6018/QCN9074.
- Hence create a new hw ops to fetch the hash ring map
- for different device variants. ipq5018 hw ops
- is similar to qcn9074 except for this change, so reuse
- all the qcn9074 ops for ipq5018.
- Tested-on: IPQ5018 hw1.0 AHB WLAN.HK.2.6.0.1-00861-QCAHKSWPL_SILICONZ-1
- Signed-off-by: Sriram R <quic_srirrama@quicinc.com>
- Co-developed-by: Karthikeyan Kathirvel <quic_kathirve@quicinc.com>
- Signed-off-by: Karthikeyan Kathirvel <quic_kathirve@quicinc.com>
- Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
- Link: https://lore.kernel.org/r/20221122132152.17771-8-quic_kathirve@quicinc.com
- ---
- drivers/net/wireless/ath/ath11k/hw.c | 44 ++++++++++++++++++++++++++++
- 1 file changed, 44 insertions(+)
- --- a/drivers/net/wireless/ath/ath11k/hw.c
- +++ b/drivers/net/wireless/ath/ath11k/hw.c
- @@ -791,6 +791,49 @@ static void ath11k_hw_wcn6855_reo_setup(
- ring_hash_map);
- }
-
- +static void ath11k_hw_ipq5018_reo_setup(struct ath11k_base *ab)
- +{
- + u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
- + u32 val;
- +
- + /* Each hash entry uses three bits to map to a particular ring. */
- + u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
- + HAL_HASH_ROUTING_RING_SW2 << 4 |
- + HAL_HASH_ROUTING_RING_SW3 << 8 |
- + HAL_HASH_ROUTING_RING_SW4 << 12 |
- + HAL_HASH_ROUTING_RING_SW1 << 16 |
- + HAL_HASH_ROUTING_RING_SW2 << 20 |
- + HAL_HASH_ROUTING_RING_SW3 << 24 |
- + HAL_HASH_ROUTING_RING_SW4 << 28;
- +
- + val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
- +
- + val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING;
- + val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING,
- + HAL_SRNG_RING_ID_REO2SW1) |
- + FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
- + FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
- + ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
- +
- + ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
- + HAL_DEFAULT_REO_TIMEOUT_USEC);
- + ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
- + HAL_DEFAULT_REO_TIMEOUT_USEC);
- + ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
- + HAL_DEFAULT_REO_TIMEOUT_USEC);
- + ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
- + HAL_DEFAULT_REO_TIMEOUT_USEC);
- +
- + ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
- + ring_hash_map);
- + ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
- + ring_hash_map);
- + ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
- + ring_hash_map);
- + ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
- + ring_hash_map);
- +}
- +
- static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data)
- {
- u16 peer_id = 0;
- @@ -1117,6 +1160,7 @@ const struct ath11k_hw_ops ipq5018_ops =
- .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id,
- .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
- .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
- + .reo_setup = ath11k_hw_ipq5018_reo_setup,
- .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
- .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
- .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid,
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