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@@ -0,0 +1,43 @@
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+diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
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+index fe9ceb7..2151975 100644
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+--- a/drivers/mtd/devices/m25p80.c
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++++ b/drivers/mtd/devices/m25p80.c
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+@@ -27,6 +27,9 @@
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+ #include <linux/spi/flash.h>
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+ #include <linux/mtd/spi-nor.h>
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+
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++#define OPCODE_RESET_ENABLE 0x66
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++#define OPCODE_RESET 0x99
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++
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+ #define MAX_CMD_SIZE 6
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+ struct m25p {
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+ struct spi_device *spi;
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+@@ -168,6 +171,17 @@ static int m25p80_erase(struct spi_nor *nor, loff_t offset)
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+ return 0;
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+ }
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+
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++void m25p80_reboot(struct mtd_info *mtd)
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++{
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++ struct spi_nor *nor = container_of(mtd, struct spi_nor, mtd);
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++ struct m25p *flash = nor->priv;
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++
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++ flash->command[0] = OPCODE_RESET_ENABLE;
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++ spi_write(flash->spi, flash->command, 1);
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++ flash->command[0] = OPCODE_RESET;
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++ spi_write(flash->spi, flash->command, 1);
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++}
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++
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+ /*
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+ * board specific setup should have ensured the SPI clock used here
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+ * matches what the READ command supports, at least until this driver
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+@@ -197,6 +211,7 @@ static int m25p_probe(struct spi_device *spi)
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+ nor->erase = m25p80_erase;
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+ nor->write_reg = m25p80_write_reg;
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+ nor->read_reg = m25p80_read_reg;
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++ nor->mtd._reboot = m25p80_reboot;
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+
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+ nor->dev = &spi->dev;
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+ nor->flash_node = spi->dev.of_node;
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+--
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+2.9.3
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+
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