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NA930.dts 2.4 KB

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  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. / {
  5. compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
  6. model = "Sercomm NA930";
  7. chosen {
  8. bootargs = "console=ttyS1,57600";
  9. };
  10. nand {
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. compatible = "mtk,mt7620-nand";
  14. partition@0 {
  15. label = "u-boot";
  16. reg = <0x0 0x20000>;
  17. read-only;
  18. };
  19. partition@200000 {
  20. label = "factory";
  21. reg = <0x200000 0x40000>;
  22. read-only;
  23. };
  24. partition@240000 {
  25. label = "Config";
  26. reg = <0x240000 0x400000>;
  27. read-only;
  28. };
  29. partition@640000 {
  30. label = "firmware";
  31. reg = <0x640000 0x1400000>;
  32. };
  33. };
  34. gpio-keys-polled {
  35. compatible = "gpio-keys-polled";
  36. #address-cells = <1>;
  37. #size-cells = <0>;
  38. poll-interval = <20>;
  39. reset {
  40. label = "reset";
  41. gpios = <&gpio0 11 1>;
  42. linux,code = <KEY_RESTART>;
  43. };
  44. zwave {
  45. label = "zwave";
  46. gpios = <&gpio0 12 1>;
  47. linux,code = <BTN_0>;
  48. };
  49. wps {
  50. label = "wps";
  51. gpios = <&gpio0 14 1>;
  52. linux,code = <KEY_WPS_BUTTON>;
  53. };
  54. };
  55. gpio-leds {
  56. compatible = "gpio-leds";
  57. zwave {
  58. label = "na930:blue:zwave";
  59. gpios = <&gpio2 0 1>;
  60. };
  61. status {
  62. label = "na930:blue:status";
  63. gpios = <&gpio2 26 1>;
  64. };
  65. service {
  66. label = "na930:blue:service";
  67. gpios = <&gpio2 28 1>;
  68. };
  69. power {
  70. label = "na930:blue:power";
  71. gpios = <&gpio2 29 1>;
  72. };
  73. };
  74. gpio_export {
  75. compatible = "gpio-export";
  76. #size-cells = <0>;
  77. telit {
  78. gpio-export,name = "telit";
  79. gpio-export,output = <1>;
  80. gpios = <&gpio0 13 0>;
  81. };
  82. };
  83. };
  84. &pinctrl {
  85. state_default: pinctrl0 {
  86. gpio {
  87. ralink,group = "i2c", "rgmii2", "spi", "ephy";
  88. ralink,function = "gpio";
  89. };
  90. uartf_gpio {
  91. ralink,group = "uartf";
  92. ralink,function = "gpio uartf";
  93. };
  94. };
  95. };
  96. &uart {
  97. status = "okay";
  98. };
  99. &gpio1 {
  100. status = "okay";
  101. };
  102. &gpio2 {
  103. status = "okay";
  104. };
  105. &ethernet {
  106. status = "okay";
  107. pinctrl-names = "default";
  108. pinctrl-0 = <&rgmii1_pins &mdio_pins>;
  109. mediatek,portmap = "llllw";
  110. port@4 {
  111. status = "okay";
  112. phy-handle = <&phy4>;
  113. phy-mode = "rgmii";
  114. };
  115. port@5 {
  116. status = "okay";
  117. phy-handle = <&phy5>;
  118. phy-mode = "rgmii";
  119. };
  120. mdio-bus {
  121. status = "okay";
  122. phy4: ethernet-phy@4 {
  123. reg = <4>;
  124. phy-mode = "rgmii";
  125. };
  126. phy5: ethernet-phy@5 {
  127. reg = <5>;
  128. phy-mode = "rgmii";
  129. };
  130. };
  131. };
  132. &gsw {
  133. mediatek,port4 = "gmac";
  134. };
  135. &ehci {
  136. status = "okay";
  137. };
  138. &ohci {
  139. status = "okay";
  140. };