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0001-qi_lb60-add-nand-spl-support.patch 27 KB

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  1. From 0329cf7965956a5a7044827e0ce88ae8d5150e54 Mon Sep 17 00:00:00 2001
  2. From: Xiangfu <xiangfu@openmobilefree.net>
  3. Date: Fri, 12 Oct 2012 09:46:58 +0800
  4. Subject: [PATCH 1/6] qi_lb60: add nand spl support
  5. The JZ4740 CPU can load 8KB from two different addresses:
  6. 1. the normal area up to 8KB starting from NAND flash address 0x00000000
  7. 2. the backup area up to 8KB starting from NAND flash address 0x00002000
  8. Signed-off-by: Xiangfu <xiangfu@openmobilefree.net>
  9. ---
  10. Makefile | 12 +++
  11. arch/mips/cpu/xburst/Makefile | 7 +-
  12. arch/mips/cpu/xburst/cpu.c | 4 +
  13. arch/mips/cpu/xburst/jz4740.c | 82 +++++++----------
  14. arch/mips/cpu/xburst/spl/Makefile | 47 ++++++++++
  15. arch/mips/cpu/xburst/spl/start.S | 63 +++++++++++++
  16. board/qi/qi_lb60/Makefile | 4 +
  17. board/qi/qi_lb60/qi_lb60-spl.c | 30 +++++++
  18. board/qi/qi_lb60/qi_lb60.c | 8 +-
  19. board/qi/qi_lb60/u-boot-spl.lds | 61 +++++++++++++
  20. drivers/mtd/nand/jz4740_nand.c | 39 ++++++++-
  21. include/configs/qi_lb60.h | 175 ++++++++++++++++++-------------------
  22. 12 files changed, 386 insertions(+), 146 deletions(-)
  23. create mode 100644 arch/mips/cpu/xburst/spl/Makefile
  24. create mode 100644 arch/mips/cpu/xburst/spl/start.S
  25. create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c
  26. create mode 100644 board/qi/qi_lb60/u-boot-spl.lds
  27. diff --git a/Makefile b/Makefile
  28. index 34d9075..a22778e 100644
  29. --- a/Makefile
  30. +++ b/Makefile
  31. @@ -393,6 +393,10 @@ ALL-y += $(obj)u-boot-nodtb-tegra.bin
  32. endif
  33. endif
  34. +ifeq ($(CPU),xburst)
  35. +ALL-y += $(obj)u-boot-xburst.bin
  36. +endif
  37. +
  38. all: $(ALL-y) $(SUBDIR_EXAMPLES)
  39. $(obj)u-boot.dtb: $(obj)u-boot
  40. @@ -506,6 +510,14 @@ $(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
  41. endif
  42. endif
  43. +ifeq ($(CPU),xburst)
  44. +$(obj)u-boot-xburst.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
  45. + dd if=$(obj)spl/u-boot-spl.bin of=$(obj)spl/u-boot-pad.bin conv=sync bs=8192 count=1
  46. + dd if=$(obj)spl/u-boot-spl.bin of=$(obj)spl/u-boot-pad.bin conv=sync,notrunc oflag=append bs=8192 count=1
  47. + tr '\0' '\377' < /dev/zero | dd of=$(obj)spl/u-boot-pad.bin conv=sync,notrunc oflag=append bs=16384 count=1
  48. + cat $(obj)spl/u-boot-pad.bin u-boot.bin > $@
  49. +endif
  50. +
  51. ifeq ($(CONFIG_SANDBOX),y)
  52. GEN_UBOOT = \
  53. cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
  54. diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile
  55. index b1f2ae4..ec35e55 100644
  56. --- a/arch/mips/cpu/xburst/Makefile
  57. +++ b/arch/mips/cpu/xburst/Makefile
  58. @@ -24,9 +24,12 @@ include $(TOPDIR)/config.mk
  59. LIB = $(obj)lib$(CPU).o
  60. +COBJS-y = cpu.o jz_serial.o
  61. +
  62. +ifneq ($(CONFIG_SPL_BUILD),y)
  63. START = start.o
  64. -SOBJS-y =
  65. -COBJS-y = cpu.o timer.o jz_serial.o
  66. +COBJS-y += timer.o
  67. +endif
  68. COBJS-$(CONFIG_JZ4740) += jz4740.o
  69. diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
  70. index ddcbfaa..1432838 100644
  71. --- a/arch/mips/cpu/xburst/cpu.c
  72. +++ b/arch/mips/cpu/xburst/cpu.c
  73. @@ -42,6 +42,8 @@
  74. : \
  75. : "i" (op), "R" (*(unsigned char *)(addr)))
  76. +#ifndef CONFIG_SPL_BUILD
  77. +
  78. void __attribute__((weak)) _machine_restart(void)
  79. {
  80. struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
  81. @@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
  82. cache_op(Hit_Invalidate_D, addr);
  83. }
  84. +#endif
  85. +
  86. void flush_icache_all(void)
  87. {
  88. u32 addr, t = 0;
  89. diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c
  90. index c0b9817..8816aa3 100644
  91. --- a/arch/mips/cpu/xburst/jz4740.c
  92. +++ b/arch/mips/cpu/xburst/jz4740.c
  93. @@ -32,31 +32,19 @@ int disable_interrupts(void)
  94. return 0;
  95. }
  96. -/*
  97. - * PLL output clock = EXTAL * NF / (NR * NO)
  98. - * NF = FD + 2, NR = RD + 2
  99. - * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
  100. - */
  101. void pll_init(void)
  102. {
  103. struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
  104. - register unsigned int cfcr, plcr1;
  105. - int n2FR[33] = {
  106. - 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
  107. - 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
  108. - 9
  109. - };
  110. - int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
  111. - int nf, pllout2;
  112. + register unsigned int cfcr, plcr;
  113. + unsigned int nf, pllout2;
  114. cfcr = CPM_CPCCR_CLKOEN |
  115. - CPM_CPCCR_PCS |
  116. - (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
  117. - (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
  118. - (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
  119. - (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
  120. - (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
  121. + (0 << CPM_CPCCR_CDIV_BIT) |
  122. + (2 << CPM_CPCCR_HDIV_BIT) |
  123. + (2 << CPM_CPCCR_PDIV_BIT) |
  124. + (2 << CPM_CPCCR_MDIV_BIT) |
  125. + (2 << CPM_CPCCR_LDIV_BIT);
  126. pllout2 = (cfcr & CPM_CPCCR_PCS) ?
  127. CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
  128. @@ -65,15 +53,18 @@ void pll_init(void)
  129. writel(pllout2 / 48000000 - 1, &cpm->uhccdr);
  130. nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
  131. - plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
  132. + plcr = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
  133. (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
  134. (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
  135. - (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
  136. + (0x32 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
  137. CPM_CPPCR_PLLEN; /* enable PLL */
  138. /* init PLL */
  139. writel(cfcr, &cpm->cpccr);
  140. - writel(plcr1, &cpm->cppcr);
  141. + writel(plcr, &cpm->cppcr);
  142. +
  143. + while (!(readl(&cpm->cppcr) & CPM_CPPCR_PLLS))
  144. + ;
  145. }
  146. void sdram_init(void)
  147. @@ -92,26 +83,12 @@ void sdram_init(void)
  148. 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
  149. };
  150. - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
  151. -
  152. cpu_clk = CONFIG_SYS_CPU_SPEED;
  153. - mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
  154. + mem_clk = 84000000;
  155. writel(0, &emc->bcr); /* Disable bus release */
  156. writew(0, &emc->rtcsr); /* Disable clock for counting */
  157. - /* Fault DMCR value for mode register setting*/
  158. -#define SDRAM_ROW0 11
  159. -#define SDRAM_COL0 8
  160. -#define SDRAM_BANK40 0
  161. -
  162. - dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
  163. - ((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
  164. - (SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
  165. - (SDRAM_BW16 << EMC_DMCR_BW_BIT) |
  166. - EMC_DMCR_EPIN |
  167. - cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
  168. -
  169. /* Basic DMCR value */
  170. dmcr = ((SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
  171. ((SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
  172. @@ -128,31 +105,31 @@ void sdram_init(void)
  173. if (tmp > 11)
  174. tmp = 11;
  175. dmcr |= (tmp - 4) << EMC_DMCR_TRAS_BIT;
  176. - tmp = SDRAM_RCD / ns;
  177. + tmp = SDRAM_RCD / ns;
  178. if (tmp > 3)
  179. tmp = 3;
  180. dmcr |= tmp << EMC_DMCR_RCD_BIT;
  181. - tmp = SDRAM_TPC / ns;
  182. + tmp = SDRAM_TPC / ns;
  183. if (tmp > 7)
  184. tmp = 7;
  185. dmcr |= tmp << EMC_DMCR_TPC_BIT;
  186. - tmp = SDRAM_TRWL / ns;
  187. + tmp = SDRAM_TRWL / ns;
  188. if (tmp > 3)
  189. tmp = 3;
  190. dmcr |= tmp << EMC_DMCR_TRWL_BIT;
  191. - tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
  192. + tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
  193. if (tmp > 14)
  194. tmp = 14;
  195. dmcr |= ((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT;
  196. /* SDRAM mode value */
  197. - sdmode = EMC_SDMR_BT_SEQ |
  198. - EMC_SDMR_OM_NORMAL |
  199. - EMC_SDMR_BL_4 |
  200. + sdmode = EMC_SDMR_BT_SEQ |
  201. + EMC_SDMR_OM_NORMAL |
  202. + EMC_SDMR_BL_4 |
  203. cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
  204. /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
  205. @@ -172,8 +149,8 @@ void sdram_init(void)
  206. if (tmp > 0xff)
  207. tmp = 0xff;
  208. writew(tmp, &emc->rtcor);
  209. +
  210. writew(0, &emc->rtcnt);
  211. - /* Divisor is 64, CKO/64 */
  212. writew(EMC_RTCSR_CKS_64, &emc->rtcsr);
  213. /* Wait for number of auto-refresh cycles */
  214. @@ -182,13 +159,17 @@ void sdram_init(void)
  215. ;
  216. /* Stage 3. Mode Register Set */
  217. + dmcr0 = (11 << EMC_DMCR_RA_BIT) |
  218. + (8 << EMC_DMCR_CA_BIT) |
  219. + (0 << EMC_DMCR_BA_BIT) |
  220. + EMC_DMCR_EPIN |
  221. + (SDRAM_BW16 << EMC_DMCR_BW_BIT) |
  222. + cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
  223. writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
  224. writeb(0, JZ4740_EMC_SDMR0 | sdmode);
  225. /* Set back to basic DMCR value */
  226. writel(dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
  227. -
  228. - /* everything is ok now */
  229. }
  230. DECLARE_GLOBAL_DATA_PTR;
  231. @@ -232,9 +213,10 @@ void rtc_init(void)
  232. phys_size_t initdram(int board_type)
  233. {
  234. struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
  235. - u32 dmcr;
  236. - u32 rows, cols, dw, banks;
  237. - ulong size;
  238. +
  239. + unsigned int dmcr;
  240. + unsigned int rows, cols, dw, banks;
  241. + unsigned long size;
  242. dmcr = readl(&emc->dmcr);
  243. rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
  244. diff --git a/arch/mips/cpu/xburst/spl/Makefile b/arch/mips/cpu/xburst/spl/Makefile
  245. new file mode 100644
  246. index 0000000..f45e8c8
  247. --- /dev/null
  248. +++ b/arch/mips/cpu/xburst/spl/Makefile
  249. @@ -0,0 +1,47 @@
  250. +#
  251. +# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
  252. +#
  253. +# See file CREDITS for list of people who contributed to this
  254. +# project.
  255. +#
  256. +# This program is free software; you can redistribute it and/or
  257. +# modify it under the terms of the GNU General Public License as
  258. +# published by the Free Software Foundation; either version 2 of
  259. +# the License, or (at your option) any later version.
  260. +#
  261. +# This program is distributed in the hope that it will be useful,
  262. +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  263. +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  264. +# GNU General Public License for more details.
  265. +#
  266. +# You should have received a copy of the GNU General Public License
  267. +# along with this program; if not, write to the Free Software
  268. +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  269. +# MA 02111-1307 USA
  270. +#
  271. +
  272. +include $(TOPDIR)/config.mk
  273. +
  274. +LIB = $(obj)lib$(CPU).o
  275. +
  276. +START = start.o
  277. +SOBJS-y =
  278. +COBJS-y =
  279. +
  280. +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
  281. +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
  282. +START := $(addprefix $(obj),$(START))
  283. +
  284. +all: $(obj).depend $(START) $(LIB)
  285. +
  286. +$(LIB): $(OBJS)
  287. + $(call cmd_link_o_target, $(OBJS))
  288. +
  289. +#########################################################################
  290. +
  291. +# defines $(obj).depend target
  292. +include $(SRCTREE)/rules.mk
  293. +
  294. +sinclude $(obj).depend
  295. +
  296. +#########################################################################
  297. diff --git a/arch/mips/cpu/xburst/spl/start.S b/arch/mips/cpu/xburst/spl/start.S
  298. new file mode 100644
  299. index 0000000..e31c4c8
  300. --- /dev/null
  301. +++ b/arch/mips/cpu/xburst/spl/start.S
  302. @@ -0,0 +1,63 @@
  303. +/*
  304. + * Copyright (c) 2010 Xiangfu Liu <xiangfu@openmobilefree.net>
  305. + *
  306. + * See file CREDITS for list of people who contributed to this
  307. + * project.
  308. + *
  309. + * This program is free software; you can redistribute it and/or
  310. + * modify it under the terms of the GNU General Public License as
  311. + * published by the Free Software Foundation; either version 3 of
  312. + * the License, or (at your option) any later version.
  313. + *
  314. + * This program is distributed in the hope that it will be useful,
  315. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  316. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  317. + * GNU General Public License for more details.
  318. + *
  319. + * You should have received a copy of the GNU General Public License
  320. + * along with this program; if not, write to the Free Software
  321. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  322. + * MA 02111-1307 USA
  323. + */
  324. +
  325. +#include <config.h>
  326. +#include <version.h>
  327. +#include <asm/regdef.h>
  328. +#include <asm/mipsregs.h>
  329. +#include <asm/addrspace.h>
  330. +#include <asm/cacheops.h>
  331. +
  332. +#include <asm/jz4740.h>
  333. +
  334. + .set noreorder
  335. +
  336. + .globl _start
  337. + .text
  338. +_start:
  339. + .word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
  340. +reset:
  341. + /*
  342. + * STATUS register
  343. + * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
  344. + */
  345. + li t0, 0x0040FC04
  346. + mtc0 t0, CP0_STATUS
  347. + /*
  348. + * CAUSE register
  349. + * IV=1, use the specical interrupt vector (0x200)
  350. + */
  351. + li t1, 0x00800000
  352. + mtc0 t1, CP0_CAUSE
  353. +
  354. + bal 1f
  355. + nop
  356. + .word _GLOBAL_OFFSET_TABLE_
  357. +1:
  358. + move gp, ra
  359. + lw t1, 0(ra)
  360. + move gp, t1
  361. +
  362. + la sp, 0x80004000
  363. + la t9, nand_spl_boot
  364. + j t9
  365. + nop
  366. diff --git a/board/qi/qi_lb60/Makefile b/board/qi/qi_lb60/Makefile
  367. index 5dae11b..e399246 100644
  368. --- a/board/qi/qi_lb60/Makefile
  369. +++ b/board/qi/qi_lb60/Makefile
  370. @@ -22,7 +22,11 @@ include $(TOPDIR)/config.mk
  371. LIB = $(obj)lib$(BOARD).o
  372. +ifeq ($(CONFIG_SPL_BUILD),y)
  373. +COBJS := $(BOARD)-spl.o
  374. +else
  375. COBJS := $(BOARD).o
  376. +endif
  377. SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  378. OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
  379. diff --git a/board/qi/qi_lb60/qi_lb60-spl.c b/board/qi/qi_lb60/qi_lb60-spl.c
  380. new file mode 100644
  381. index 0000000..3fe3fa3
  382. --- /dev/null
  383. +++ b/board/qi/qi_lb60/qi_lb60-spl.c
  384. @@ -0,0 +1,30 @@
  385. +/*
  386. + * Authors: Xiangfu Liu <xiangfu@openmobilefree.cc>
  387. + *
  388. + * This program is free software; you can redistribute it and/or
  389. + * modify it under the terms of the GNU General Public License
  390. + * as published by the Free Software Foundation; either version
  391. + * 3 of the License, or (at your option) any later version.
  392. + */
  393. +
  394. +#include <common.h>
  395. +#include <nand.h>
  396. +#include <asm/io.h>
  397. +#include <asm/jz4740.h>
  398. +
  399. +void nand_spl_boot(void)
  400. +{
  401. + __gpio_as_sdram_16bit_4720();
  402. + __gpio_as_uart0();
  403. + __gpio_jtag_to_uart0();
  404. +
  405. + serial_init();
  406. +
  407. + pll_init();
  408. + sdram_init();
  409. +
  410. + nand_init();
  411. +
  412. + puts("\nQi LB60 SPL: Starting U-Boot ...\n");
  413. + nand_boot();
  414. +}
  415. diff --git a/board/qi/qi_lb60/qi_lb60.c b/board/qi/qi_lb60/qi_lb60.c
  416. index d975209..3bd4e2f 100644
  417. --- a/board/qi/qi_lb60/qi_lb60.c
  418. +++ b/board/qi/qi_lb60/qi_lb60.c
  419. @@ -1,5 +1,5 @@
  420. /*
  421. - * Authors: Xiangfu Liu <xiangfu@sharism.cc>
  422. + * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
  423. *
  424. * This program is free software; you can redistribute it and/or
  425. * modify it under the terms of the GNU General Public License
  426. @@ -97,8 +97,10 @@ int board_early_init_f(void)
  427. /* U-Boot common routines */
  428. int checkboard(void)
  429. {
  430. - printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %ld MHz)\n",
  431. - gd->cpu_clk / 1000000);
  432. + printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC)\n");
  433. + printf(" CPU: %ld\n", gd->cpu_clk);
  434. + printf(" MEM: %ld\n", gd->mem_clk);
  435. + printf(" DEV: %ld\n", gd->dev_clk);
  436. return 0;
  437. }
  438. diff --git a/board/qi/qi_lb60/u-boot-spl.lds b/board/qi/qi_lb60/u-boot-spl.lds
  439. new file mode 100644
  440. index 0000000..930537f
  441. --- /dev/null
  442. +++ b/board/qi/qi_lb60/u-boot-spl.lds
  443. @@ -0,0 +1,61 @@
  444. +/*
  445. + * (C) Copyright 2012 Xiangfu Liu <xiangfu@openmobilefree.net>
  446. + *
  447. + * This program is free software; you can redistribute it and/or
  448. + * modify it under the terms of the GNU General Public License as
  449. + * published by the Free Software Foundation; either version 2 of
  450. + * the License, or (at your option) any later version.
  451. + *
  452. + * This program is distributed in the hope that it will be useful,
  453. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  454. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  455. + * GNU General Public License for more details.
  456. + *
  457. + * You should have received a copy of the GNU General Public License
  458. + * along with this program; if not, write to the Free Software
  459. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  460. + * MA 02111-1307 USA
  461. + */
  462. +
  463. +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
  464. +
  465. +OUTPUT_ARCH(mips)
  466. +ENTRY(_start)
  467. +SECTIONS
  468. +{
  469. + . = 0x80000000;
  470. + . = ALIGN(4);
  471. + .text :
  472. + {
  473. + *(.text)
  474. + }
  475. +
  476. + . = ALIGN(4);
  477. + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
  478. +
  479. + . = ALIGN(4);
  480. + .data : { *(.data) }
  481. +
  482. + . = ALIGN(4);
  483. + .sdata : { *(.sdata) }
  484. +
  485. + _gp = ALIGN(16);
  486. +
  487. + __got_start = .;
  488. + .got : { *(.got) }
  489. + __got_end = .;
  490. +
  491. + . = .;
  492. + __u_boot_cmd_start = .;
  493. + .u_boot_cmd : { *(.u_boot_cmd) }
  494. + __u_boot_cmd_end = .;
  495. +
  496. + uboot_end_data = .;
  497. + num_got_entries = (__got_end - __got_start) >> 2;
  498. +
  499. + . = ALIGN(4);
  500. + .sbss : { *(.sbss) }
  501. + .bss : { *(.bss) }
  502. + uboot_end = .;
  503. +}
  504. +ASSERT(uboot_end <= 0x80002000, "NAND bootstrap too big");
  505. diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
  506. index 3ec34f3..24a4921 100644
  507. --- a/drivers/mtd/nand/jz4740_nand.c
  508. +++ b/drivers/mtd/nand/jz4740_nand.c
  509. @@ -15,6 +15,9 @@
  510. #include <asm/io.h>
  511. #include <asm/jz4740.h>
  512. +#ifdef CONFIG_SPL_BUILD
  513. +#define printf(s) puts(s)
  514. +#endif
  515. #define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
  516. #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
  517. #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
  518. @@ -176,7 +179,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
  519. for (k = 0; k < 9; k++)
  520. writeb(read_ecc[k], &emc->nfpar[k]);
  521. }
  522. - /* Set PRDY */
  523. +
  524. writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
  525. /* Wait for completion */
  526. @@ -184,7 +187,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
  527. status = readl(&emc->nfints);
  528. } while (!(status & EMC_NFINTS_DECF));
  529. - /* disable ecc */
  530. + /* Disable ECC */
  531. writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
  532. /* Check decoding */
  533. @@ -192,7 +195,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
  534. return 0;
  535. if (status & EMC_NFINTS_UNCOR) {
  536. - printf("uncorrectable ecc\n");
  537. + printf("JZ4740 uncorrectable ECC\n");
  538. return -1;
  539. }
  540. @@ -230,6 +233,32 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
  541. return errcnt;
  542. }
  543. +#ifdef CONFIG_SPL_BUILD
  544. +static void jz_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  545. +{
  546. + int i;
  547. + struct nand_chip *this = mtd->priv;
  548. +
  549. +#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3) || \
  550. + (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2)
  551. + for (i = 0; i < len; i += 2)
  552. + buf[i] = readw(this->IO_ADDR_R);
  553. +#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3) || \
  554. + (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2)
  555. + for (i = 0; i < len; i++)
  556. + buf[i] = readb(this->IO_ADDR_R);
  557. +#else
  558. + #error JZ4740_NANDBOOT_CFG not defined or wrong
  559. +#endif
  560. +}
  561. +
  562. +static uint8_t jz_nand_read_byte(struct mtd_info *mtd)
  563. +{
  564. + struct nand_chip *this = mtd->priv;
  565. + return readb(this->IO_ADDR_R);
  566. +}
  567. +#endif
  568. +
  569. /*
  570. * Main initialization routine
  571. */
  572. @@ -254,6 +283,10 @@ int board_nand_init(struct nand_chip *nand)
  573. nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
  574. nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
  575. nand->ecc.layout = &qi_lb60_ecclayout_2gb;
  576. +#ifdef CONFIG_SPL_BUILD
  577. + nand->read_byte = jz_nand_read_byte;
  578. + nand->read_buf = jz_nand_read_buf;
  579. +#endif
  580. nand->chip_delay = 50;
  581. nand->options = NAND_USE_FLASH_BBT;
  582. diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
  583. index 4bb5bbc..7bff444 100644
  584. --- a/include/configs/qi_lb60.h
  585. +++ b/include/configs/qi_lb60.h
  586. @@ -1,5 +1,5 @@
  587. /*
  588. - * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
  589. + * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
  590. *
  591. * This program is free software; you can redistribute it and/or
  592. * modify it under the terms of the GNU General Public License
  593. @@ -14,7 +14,6 @@
  594. #define CONFIG_SYS_LITTLE_ENDIAN
  595. #define CONFIG_JZSOC /* Jz SoC */
  596. #define CONFIG_JZ4740 /* Jz4740 SoC */
  597. -#define CONFIG_NAND_JZ4740
  598. #define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
  599. #define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
  600. @@ -24,24 +23,43 @@
  601. #define CONFIG_SYS_UART_BASE JZ4740_UART0_BASE /* Base of the UART channel */
  602. #define CONFIG_BAUDRATE 57600
  603. +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
  604. +#define CONFIG_BOOTDELAY 0
  605. +#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
  606. +#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x280000;bootm"
  607. +
  608. +/*
  609. + * Miscellaneous configurable options
  610. + */
  611. +#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
  612. +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
  613. +#define CONFIG_SYS_LOAD_ADDR 0x80600000
  614. +#define CONFIG_SYS_MEMTEST_START 0x80100000
  615. +#define CONFIG_SYS_MEMTEST_END 0x80A00000
  616. +#define CONFIG_SYS_TEXT_BASE 0x80100000
  617. +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  618. +
  619. +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  620. +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
  621. +
  622. +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  623. +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  624. +
  625. +#define CONFIG_SYS_LONGHELP
  626. +#define CONFIG_SYS_MAXARGS 16
  627. +#define CONFIG_SYS_PROMPT "NanoNote# "
  628. +
  629. #define CONFIG_SKIP_LOWLEVEL_INIT
  630. #define CONFIG_BOARD_EARLY_INIT_F
  631. #define CONFIG_SYS_NO_FLASH
  632. #define CONFIG_SYS_FLASH_BASE 0 /* init flash_base as 0 */
  633. -#define CONFIG_ENV_OVERWRITE
  634. -
  635. -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
  636. -#define CONFIG_BOOTDELAY 0
  637. -#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
  638. -#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
  639. /*
  640. - * Command line configuration.
  641. + * Command line configuration
  642. */
  643. #define CONFIG_CMD_BOOTD /* bootd */
  644. #define CONFIG_CMD_CONSOLE /* coninfo */
  645. #define CONFIG_CMD_ECHO /* echo arguments */
  646. -
  647. #define CONFIG_CMD_LOADB /* loadb */
  648. #define CONFIG_CMD_LOADS /* loads */
  649. #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
  650. @@ -58,45 +76,16 @@
  651. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  652. /*
  653. - * Miscellaneous configurable options
  654. - */
  655. -#define CONFIG_SYS_MAXARGS 16
  656. -#define CONFIG_SYS_LONGHELP
  657. -#define CONFIG_SYS_PROMPT "NanoNote# "
  658. -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  659. -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  660. -
  661. -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  662. -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
  663. -
  664. -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
  665. -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
  666. -#define CONFIG_SYS_LOAD_ADDR 0x80600000
  667. -#define CONFIG_SYS_MEMTEST_START 0x80100000
  668. -#define CONFIG_SYS_MEMTEST_END 0x80800000
  669. -
  670. -/*
  671. - * Environment
  672. + * NAND driver configuration
  673. */
  674. -#define CONFIG_ENV_IS_IN_NAND /* use NAND for environment vars */
  675. -
  676. -#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  677. -/*
  678. - * if board nand flash is 1GB, set to 1
  679. - * if board nand flash is 2GB, set to 2
  680. - * for change the PAGE_SIZE and BLOCK_SIZE
  681. - * will delete when there is no 1GB flash
  682. - */
  683. -#define NANONOTE_NAND_SIZE 2
  684. -
  685. -#define CONFIG_SYS_NAND_PAGE_SIZE (2048 * NANONOTE_NAND_SIZE)
  686. -#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * NANONOTE_NAND_SIZE << 10)
  687. -/* nand bad block was marked at this page in a block, start from 0 */
  688. +#define CONFIG_NAND_JZ4740
  689. +#define CONFIG_SYS_NAND_PAGE_SIZE 4096
  690. +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 << 10)
  691. +/* NAND bad block was marked at this page in a block, start from 0 */
  692. #define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
  693. #define CONFIG_SYS_NAND_PAGE_COUNT 128
  694. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  695. -/* ECC offset position in oob area, default value is 6 if it isn't defined */
  696. -#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE)
  697. +#define CONFIG_SYS_NAND_ECC_POS 12
  698. #define CONFIG_SYS_NAND_ECCSIZE 512
  699. #define CONFIG_SYS_NAND_ECCBYTES 9
  700. #define CONFIG_SYS_NAND_ECCPOS \
  701. @@ -115,10 +104,9 @@
  702. #define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
  703. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  704. #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
  705. -#define CONFIG_NAND_SPL_TEXT_BASE 0x80000000
  706. /*
  707. - * IPL (Initial Program Loader, integrated inside CPU)
  708. + * IPL (Initial Program Loader, integrated inside Ingenic Xburst JZ4740 CPU)
  709. * Will load first 8k from NAND (SPL) into cache and execute it from there.
  710. *
  711. * SPL (Secondary Program Loader)
  712. @@ -130,77 +118,88 @@
  713. * NUB (NAND U-Boot)
  714. * This NAND U-Boot (NUB) is a special U-Boot version which can be started
  715. * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
  716. - *
  717. */
  718. +
  719. +/*
  720. + * NAND SPL configuration
  721. + */
  722. +#define CONFIG_SPL
  723. +#define CONFIG_SPL_LIBGENERIC_SUPPORT
  724. +#define CONFIG_SPL_LIBCOMMON_SUPPORT
  725. +#define CONFIG_SPL_NAND_LOAD
  726. +#define CONFIG_SPL_NAND_SIMPLE
  727. +#define CONFIG_SPL_NAND_SUPPORT
  728. +#define CONFIG_SPL_TEXT_BASE 0x80000000
  729. +#define CONFIG_SPL_START_S_PATH "arch/mips/cpu/xburst/spl"
  730. +
  731. +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  732. +#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
  733. +#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3
  734. +
  735. #define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
  736. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
  737. -/* Start NUB from this addr*/
  738. + /* Start NUB from this addr */
  739. +#define CONFIG_SYS_NAND_U_BOOT_OFFS (32 << 10) /* Offset of NUB */
  740. +#define CONFIG_SYS_NAND_U_BOOT_SIZE (256 << 10) /* Size of NUB */
  741. /*
  742. - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
  743. + * Environment configuration
  744. */
  745. -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
  746. -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
  747. -
  748. +#define CONFIG_ENV_OVERWRITE
  749. +#define CONFIG_ENV_IS_IN_NAND
  750. #define CONFIG_ENV_SIZE (4 << 10)
  751. #define CONFIG_ENV_OFFSET \
  752. (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
  753. #define CONFIG_ENV_OFFSET_REDUND \
  754. (CONFIG_ENV_OFFSET + CONFIG_SYS_NAND_BLOCK_SIZE)
  755. -#define CONFIG_SYS_TEXT_BASE 0x80100000
  756. -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  757. -
  758. /*
  759. - * SDRAM Info.
  760. + * CPU cache configuration
  761. */
  762. -#define CONFIG_NR_DRAM_BANKS 1
  763. +#define CONFIG_SYS_DCACHE_SIZE 16384
  764. +#define CONFIG_SYS_ICACHE_SIZE 16384
  765. +#define CONFIG_SYS_CACHELINE_SIZE 32
  766. /*
  767. - * Cache Configuration
  768. + * SDRAM configuration
  769. */
  770. -#define CONFIG_SYS_DCACHE_SIZE 16384
  771. -#define CONFIG_SYS_ICACHE_SIZE 16384
  772. -#define CONFIG_SYS_CACHELINE_SIZE 32
  773. +#define CONFIG_NR_DRAM_BANKS 1
  774. +
  775. +#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
  776. +#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
  777. +#define SDRAM_ROW 13 /* Row address: 11 to 13 */
  778. +#define SDRAM_COL 9 /* Column address: 8 to 12 */
  779. +#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
  780. +#define SDRAM_TRAS 45 /* RAS# Active Time */
  781. +#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
  782. +#define SDRAM_TPC 20 /* RAS# Precharge Time */
  783. +#define SDRAM_TRWL 7 /* Write Latency Time */
  784. +#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
  785. /*
  786. - * GPIO definition
  787. + * GPIO configuration
  788. */
  789. -#define GPIO_LCD_CS (2 * 32 + 21)
  790. -#define GPIO_AMP_EN (3 * 32 + 4)
  791. +#define GPIO_LCD_CS (2 * 32 + 21)
  792. +#define GPIO_AMP_EN (3 * 32 + 4)
  793. -#define GPIO_SDPW_EN (3 * 32 + 2)
  794. -#define GPIO_SD_DETECT (3 * 32 + 0)
  795. +#define GPIO_SDPW_EN (3 * 32 + 2)
  796. +#define GPIO_SD_DETECT (3 * 32 + 0)
  797. -#define GPIO_BUZZ_PWM (3 * 32 + 27)
  798. -#define GPIO_USB_DETECT (3 * 32 + 28)
  799. +#define GPIO_BUZZ_PWM (3 * 32 + 27)
  800. +#define GPIO_USB_DETECT (3 * 32 + 28)
  801. -#define GPIO_AUDIO_POP (1 * 32 + 29)
  802. -#define GPIO_COB_TEST (1 * 32 + 30)
  803. +#define GPIO_AUDIO_POP (1 * 32 + 29)
  804. +#define GPIO_COB_TEST (1 * 32 + 30)
  805. #define GPIO_KEYOUT_BASE (2 * 32 + 10)
  806. -#define GPIO_KEYIN_BASE (3 * 32 + 18)
  807. -#define GPIO_KEYIN_8 (3 * 32 + 26)
  808. +#define GPIO_KEYIN_BASE (3 * 32 + 18)
  809. +#define GPIO_KEYIN_8 (3 * 32 + 26)
  810. -#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
  811. +#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
  812. #define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */
  813. #define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */
  814. #define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */
  815. #define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */
  816. -/* SDRAM paramters */
  817. -#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
  818. -#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
  819. -#define SDRAM_ROW 13 /* Row address: 11 to 13 */
  820. -#define SDRAM_COL 9 /* Column address: 8 to 12 */
  821. -#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
  822. -
  823. -/* SDRAM Timings, unit: ns */
  824. -#define SDRAM_TRAS 45 /* RAS# Active Time */
  825. -#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
  826. -#define SDRAM_TPC 20 /* RAS# Precharge Time */
  827. -#define SDRAM_TRWL 7 /* Write Latency Time */
  828. -#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
  829. -
  830. #endif
  831. --
  832. 1.7.9.5