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ag71xx.h 10 KB

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  1. /*
  2. * Atheros AR71xx built-in ethernet mac driver
  3. *
  4. * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  5. * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  6. *
  7. * Based on Atheros' AG7100 driver
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License version 2 as published
  11. * by the Free Software Foundation.
  12. */
  13. #ifndef __AG71XX_H
  14. #define __AG71XX_H
  15. #include <linux/types.h>
  16. #include <linux/bitops.h>
  17. #include <asm/ar71xx.h>
  18. // controller has 2 ports
  19. #define MAX_AG71XX_DEVS 2
  20. #define ETH_FCS_LEN 4
  21. #define SPEED_10 10
  22. #define SPEED_100 100
  23. #define SPEED_1000 1000
  24. #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
  25. #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
  26. #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
  27. #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
  28. #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
  29. #define AG71XX_TX_FIFO_LEN 2048
  30. #define AG71XX_TX_MTU_LEN 1536
  31. #define AG71XX_RX_PKT_RESERVE 64
  32. #define AG71XX_RX_PKT_SIZE \
  33. (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
  34. #ifndef CONFIG_SYS_RX_ETH_BUFFER
  35. #define AG71XX_TX_RING_SIZE 4
  36. #define AG71XX_RX_RING_SIZE 4
  37. #else
  38. #define AG71XX_TX_RING_SIZE CONFIG_SYS_RX_ETH_BUFFER
  39. #define AG71XX_RX_RING_SIZE CONFIG_SYS_RX_ETH_BUFFER
  40. #endif
  41. #define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4)
  42. #define AG71XX_TX_THRES_WAKEUP \
  43. (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
  44. struct ag71xx_desc {
  45. u32 data;
  46. u32 ctrl;
  47. #define DESC_EMPTY BIT(31)
  48. #define DESC_MORE BIT(24)
  49. #define DESC_PKTLEN_M 0xfff
  50. u32 next;
  51. u32 pad;
  52. } __attribute__((aligned(4)));
  53. struct ag71xx_buf {
  54. struct sk_buff *skb;
  55. struct ag71xx_desc *desc;
  56. dma_addr_t dma_addr;
  57. u32 pad;
  58. };
  59. struct ag71xx_ring {
  60. struct ag71xx_buf *buf;
  61. u8 *descs_cpu;
  62. u8 *descs_dma;
  63. unsigned int desc_size;
  64. unsigned int curr;
  65. unsigned int size;
  66. };
  67. struct ag71xx {
  68. uint32_t mac_base;
  69. uint32_t mii_ctrl;
  70. struct eth_device *dev;
  71. struct ag71xx_ring rx_ring;
  72. struct ag71xx_ring tx_ring;
  73. char *phyname;
  74. u16 phyid;
  75. u16 phyfixed;
  76. uint32_t link;
  77. uint32_t speed;
  78. int32_t duplex;
  79. uint32_t macNum;
  80. uint32_t mii_if;
  81. };
  82. void ag71xx_link_adjust(struct ag71xx *ag);
  83. int ag71xx_phy_connect(struct ag71xx *ag);
  84. void ag71xx_phy_disconnect(struct ag71xx *ag);
  85. void ag71xx_phy_start(struct ag71xx *ag);
  86. void ag71xx_phy_stop(struct ag71xx *ag);
  87. static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
  88. {
  89. return ((desc->ctrl & DESC_EMPTY) != 0);
  90. }
  91. static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
  92. {
  93. return (desc->ctrl & DESC_PKTLEN_M);
  94. }
  95. /* Register offsets */
  96. #define AG71XX_REG_MAC_CFG1 0x0000
  97. #define AG71XX_REG_MAC_CFG2 0x0004
  98. #define AG71XX_REG_MAC_IPG 0x0008
  99. #define AG71XX_REG_MAC_HDX 0x000c
  100. #define AG71XX_REG_MAC_MFL 0x0010
  101. #define AG71XX_REG_MII_CFG 0x0020
  102. #define AG71XX_REG_MII_CMD 0x0024
  103. #define AG71XX_REG_MII_ADDR 0x0028
  104. #define AG71XX_REG_MII_CTRL 0x002c
  105. #define AG71XX_REG_MII_STATUS 0x0030
  106. #define AG71XX_REG_MII_IND 0x0034
  107. #define AG71XX_REG_MAC_IFCTL 0x0038
  108. #define AG71XX_REG_MAC_ADDR1 0x0040
  109. #define AG71XX_REG_MAC_ADDR2 0x0044
  110. #define AG71XX_REG_FIFO_CFG0 0x0048
  111. #define AG71XX_REG_FIFO_CFG1 0x004c
  112. #define AG71XX_REG_FIFO_CFG2 0x0050
  113. #define AG71XX_REG_FIFO_CFG3 0x0054
  114. #define AG71XX_REG_FIFO_CFG4 0x0058
  115. #define AG71XX_REG_FIFO_CFG5 0x005c
  116. #define AG71XX_REG_FIFO_RAM0 0x0060
  117. #define AG71XX_REG_FIFO_RAM1 0x0064
  118. #define AG71XX_REG_FIFO_RAM2 0x0068
  119. #define AG71XX_REG_FIFO_RAM3 0x006c
  120. #define AG71XX_REG_FIFO_RAM4 0x0070
  121. #define AG71XX_REG_FIFO_RAM5 0x0074
  122. #define AG71XX_REG_FIFO_RAM6 0x0078
  123. #define AG71XX_REG_FIFO_RAM7 0x007c
  124. #define AG71XX_REG_TX_CTRL 0x0180
  125. #define AG71XX_REG_TX_DESC 0x0184
  126. #define AG71XX_REG_TX_STATUS 0x0188
  127. #define AG71XX_REG_RX_CTRL 0x018c
  128. #define AG71XX_REG_RX_DESC 0x0190
  129. #define AG71XX_REG_RX_STATUS 0x0194
  130. #define AG71XX_REG_INT_ENABLE 0x0198
  131. #define AG71XX_REG_INT_STATUS 0x019c
  132. #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
  133. #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
  134. #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
  135. #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
  136. #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
  137. #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
  138. #define MAC_CFG1_LB BIT(8) /* Loopback mode */
  139. #define MAC_CFG1_SR BIT(31) /* Soft Reset */
  140. #define MAC_CFG2_FDX BIT(0)
  141. #define MAC_CFG2_CRC_EN BIT(1)
  142. #define MAC_CFG2_PAD_CRC_EN BIT(2)
  143. #define MAC_CFG2_LEN_CHECK BIT(4)
  144. #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
  145. #define MAC_CFG2_IF_1000 BIT(9)
  146. #define MAC_CFG2_IF_10_100 BIT(8)
  147. #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
  148. #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
  149. #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
  150. #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
  151. #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
  152. #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
  153. | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
  154. #define FIFO_CFG0_ENABLE_SHIFT 8
  155. #define FIFO_CFG4_DE BIT(0) /* Drop Event */
  156. #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
  157. #define FIFO_CFG4_FC BIT(2) /* False Carrier */
  158. #define FIFO_CFG4_CE BIT(3) /* Code Error */
  159. #define FIFO_CFG4_CR BIT(4) /* CRC error */
  160. #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
  161. #define FIFO_CFG4_LO BIT(6) /* Length out of range */
  162. #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
  163. #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
  164. #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
  165. #define FIFO_CFG4_DR BIT(10) /* Dribble */
  166. #define FIFO_CFG4_LE BIT(11) /* Long Event */
  167. #define FIFO_CFG4_CF BIT(12) /* Control Frame */
  168. #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
  169. #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
  170. #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
  171. #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
  172. #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
  173. #define FIFO_CFG5_DE BIT(0) /* Drop Event */
  174. #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
  175. #define FIFO_CFG5_FC BIT(2) /* False Carrier */
  176. #define FIFO_CFG5_CE BIT(3) /* Code Error */
  177. #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
  178. #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
  179. #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
  180. #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
  181. #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
  182. #define FIFO_CFG5_DR BIT(9) /* Dribble */
  183. #define FIFO_CFG5_CF BIT(10) /* Control Frame */
  184. #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
  185. #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
  186. #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
  187. #define FIFO_CFG5_LE BIT(14) /* Long Event */
  188. #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
  189. #define FIFO_CFG5_16 BIT(16) /* unknown */
  190. #define FIFO_CFG5_17 BIT(17) /* unknown */
  191. #define FIFO_CFG5_SF BIT(18) /* Short Frame */
  192. #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
  193. #define AG71XX_INT_TX_PS BIT(0)
  194. #define AG71XX_INT_TX_UR BIT(1)
  195. #define AG71XX_INT_TX_BE BIT(3)
  196. #define AG71XX_INT_RX_PR BIT(4)
  197. #define AG71XX_INT_RX_OF BIT(6)
  198. #define AG71XX_INT_RX_BE BIT(7)
  199. #define MAC_IFCTL_SPEED BIT(16)
  200. #define MII_CFG_CLK_DIV_4 0
  201. #define MII_CFG_CLK_DIV_6 2
  202. #define MII_CFG_CLK_DIV_8 3
  203. #define MII_CFG_CLK_DIV_10 4
  204. #define MII_CFG_CLK_DIV_14 5
  205. #define MII_CFG_CLK_DIV_20 6
  206. #define MII_CFG_CLK_DIV_28 7
  207. #define MII_CFG_RESET BIT(31)
  208. #define MII_CMD_WRITE 0x0
  209. #define MII_CMD_READ 0x1
  210. #define MII_ADDR_SHIFT 8
  211. #define MII_IND_BUSY BIT(0)
  212. #define MII_IND_INVALID BIT(2)
  213. #define TX_CTRL_TXE BIT(0) /* Tx Enable */
  214. #define TX_STATUS_PS BIT(0) /* Packet Sent */
  215. #define TX_STATUS_UR BIT(1) /* Tx Underrun */
  216. #define TX_STATUS_BE BIT(3) /* Bus Error */
  217. #define RX_CTRL_RXE BIT(0) /* Rx Enable */
  218. #define RX_STATUS_PR BIT(0) /* Packet Received */
  219. #define RX_STATUS_OF BIT(2) /* Rx Overflow */
  220. #define RX_STATUS_BE BIT(3) /* Bus Error */
  221. #define MII_CTRL_IF_MASK 3
  222. #define MII_CTRL_SPEED_SHIFT 4
  223. #define MII_CTRL_SPEED_MASK 3
  224. #define MII_CTRL_SPEED_10 0
  225. #define MII_CTRL_SPEED_100 1
  226. #define MII_CTRL_SPEED_1000 2
  227. static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
  228. {
  229. __raw_writel(value, ag->mac_base + reg);
  230. /* flush write */
  231. (void) __raw_readl(ag->mac_base + reg);
  232. }
  233. static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
  234. {
  235. return __raw_readl(ag->mac_base + reg);
  236. }
  237. static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
  238. {
  239. uint32_t r;
  240. r = ag->mac_base + reg;
  241. __raw_writel(__raw_readl(r) | mask, r);
  242. /* flush write */
  243. (void)__raw_readl(r);
  244. }
  245. static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
  246. {
  247. uint32_t r;
  248. r = ag->mac_base + reg;
  249. __raw_writel(__raw_readl(r) & ~mask, r);
  250. /* flush write */
  251. (void) __raw_readl(r);
  252. }
  253. static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
  254. {
  255. ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
  256. }
  257. static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
  258. {
  259. ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
  260. }
  261. static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
  262. {
  263. __raw_writel(value, ag->mii_ctrl);
  264. /* flush write */
  265. __raw_readl(ag->mii_ctrl);
  266. }
  267. static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
  268. {
  269. return __raw_readl(ag->mii_ctrl);
  270. }
  271. static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
  272. unsigned int mii_if)
  273. {
  274. u32 t;
  275. t = ag71xx_mii_ctrl_rr(ag);
  276. t &= ~(MII_CTRL_IF_MASK);
  277. t |= (mii_if & MII_CTRL_IF_MASK);
  278. ag71xx_mii_ctrl_wr(ag, t);
  279. }
  280. static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
  281. unsigned int speed)
  282. {
  283. u32 t;
  284. t = ag71xx_mii_ctrl_rr(ag);
  285. t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
  286. t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
  287. ag71xx_mii_ctrl_wr(ag, t);
  288. }
  289. #ifdef CONFIG_AG71XX_AR8216_SUPPORT
  290. void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
  291. int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
  292. int pktlen);
  293. static inline int ag71xx_has_ar8216(struct ag71xx *ag)
  294. {
  295. return ag71xx_get_pdata(ag)->has_ar8216;
  296. }
  297. #else
  298. static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
  299. struct sk_buff *skb)
  300. {
  301. }
  302. static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
  303. struct sk_buff *skb,
  304. int pktlen)
  305. {
  306. return 0;
  307. }
  308. static inline int ag71xx_has_ar8216(struct ag71xx *ag)
  309. {
  310. return 0;
  311. }
  312. #endif
  313. #endif /* _AG71XX_H */