2
0

mt7620a.dtsi 9.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558
  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "ralink,mtk7620a-soc";
  5. cpus {
  6. cpu@0 {
  7. compatible = "mips,mips24KEc";
  8. };
  9. };
  10. chosen {
  11. bootargs = "console=ttyS0,57600";
  12. };
  13. cpuintc: cpuintc@0 {
  14. #address-cells = <0>;
  15. #interrupt-cells = <1>;
  16. interrupt-controller;
  17. compatible = "mti,cpu-interrupt-controller";
  18. };
  19. aliases {
  20. spi0 = &spi0;
  21. spi1 = &spi1;
  22. serial0 = &uartlite;
  23. };
  24. palmbus: palmbus@10000000 {
  25. compatible = "palmbus";
  26. reg = <0x10000000 0x200000>;
  27. ranges = <0x0 0x10000000 0x1FFFFF>;
  28. #address-cells = <1>;
  29. #size-cells = <1>;
  30. sysc: sysc@0 {
  31. compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc";
  32. reg = <0x0 0x100>;
  33. };
  34. timer: timer@100 {
  35. compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
  36. reg = <0x100 0x20>;
  37. interrupt-parent = <&intc>;
  38. interrupts = <1>;
  39. };
  40. watchdog: watchdog@120 {
  41. compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
  42. reg = <0x120 0x10>;
  43. resets = <&rstctrl 8>;
  44. reset-names = "wdt";
  45. interrupt-parent = <&intc>;
  46. interrupts = <1>;
  47. };
  48. intc: intc@200 {
  49. compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
  50. reg = <0x200 0x100>;
  51. resets = <&rstctrl 19>;
  52. reset-names = "intc";
  53. interrupt-controller;
  54. #interrupt-cells = <1>;
  55. interrupt-parent = <&cpuintc>;
  56. interrupts = <2>;
  57. };
  58. memc: memc@300 {
  59. compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
  60. reg = <0x300 0x100>;
  61. resets = <&rstctrl 20>;
  62. reset-names = "mc";
  63. interrupt-parent = <&intc>;
  64. interrupts = <3>;
  65. };
  66. uart: uart@500 {
  67. compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
  68. reg = <0x500 0x100>;
  69. resets = <&rstctrl 12>;
  70. reset-names = "uart";
  71. interrupt-parent = <&intc>;
  72. interrupts = <5>;
  73. reg-shift = <2>;
  74. status = "disabled";
  75. };
  76. gpio0: gpio@600 {
  77. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  78. reg = <0x600 0x34>;
  79. resets = <&rstctrl 13>;
  80. reset-names = "pio";
  81. interrupt-parent = <&intc>;
  82. interrupts = <6>;
  83. gpio-controller;
  84. #gpio-cells = <2>;
  85. ralink,gpio-base = <0>;
  86. ralink,num-gpios = <24>;
  87. ralink,register-map = [ 00 04 08 0c
  88. 20 24 28 2c
  89. 30 34 ];
  90. };
  91. gpio1: gpio@638 {
  92. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  93. reg = <0x638 0x24>;
  94. interrupt-parent = <&intc>;
  95. interrupts = <6>;
  96. gpio-controller;
  97. #gpio-cells = <2>;
  98. ralink,gpio-base = <24>;
  99. ralink,num-gpios = <16>;
  100. ralink,register-map = [ 00 04 08 0c
  101. 10 14 18 1c
  102. 20 24 ];
  103. status = "disabled";
  104. };
  105. gpio2: gpio@660 {
  106. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  107. reg = <0x660 0x24>;
  108. interrupt-parent = <&intc>;
  109. interrupts = <6>;
  110. gpio-controller;
  111. #gpio-cells = <2>;
  112. ralink,gpio-base = <40>;
  113. ralink,num-gpios = <32>;
  114. ralink,register-map = [ 00 04 08 0c
  115. 10 14 18 1c
  116. 20 24 ];
  117. status = "disabled";
  118. };
  119. gpio3: gpio@688 {
  120. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  121. reg = <0x688 0x24>;
  122. interrupt-parent = <&intc>;
  123. interrupts = <6>;
  124. gpio-controller;
  125. #gpio-cells = <2>;
  126. ralink,gpio-base = <72>;
  127. ralink,num-gpios = <1>;
  128. ralink,register-map = [ 00 04 08 0c
  129. 10 14 18 1c
  130. 20 24 ];
  131. status = "disabled";
  132. };
  133. i2c: i2c@900 {
  134. compatible = "ralink,rt2880-i2c";
  135. reg = <0x900 0x100>;
  136. resets = <&rstctrl 16>;
  137. reset-names = "i2c";
  138. #address-cells = <1>;
  139. #size-cells = <0>;
  140. status = "disabled";
  141. pinctrl-names = "default";
  142. pinctrl-0 = <&i2c_pins>;
  143. };
  144. i2s: i2s@a00 {
  145. compatible = "mediatek,mt7620-i2s";
  146. reg = <0xa00 0x100>;
  147. resets = <&rstctrl 17>;
  148. reset-names = "i2s";
  149. interrupt-parent = <&intc>;
  150. interrupts = <10>;
  151. txdma-req = <2>;
  152. rxdma-req = <3>;
  153. dmas = <&gdma 4>,
  154. <&gdma 6>;
  155. dma-names = "tx", "rx";
  156. status = "disabled";
  157. };
  158. spi0: spi@b00 {
  159. compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
  160. reg = <0xb00 0x40>;
  161. resets = <&rstctrl 18>;
  162. reset-names = "spi";
  163. #address-cells = <1>;
  164. #size-cells = <0>;
  165. status = "disabled";
  166. pinctrl-names = "default";
  167. pinctrl-0 = <&spi_pins>;
  168. };
  169. spi1: spi@b40 {
  170. compatible = "ralink,rt2880-spi";
  171. reg = <0xb40 0x60>;
  172. resets = <&rstctrl 18>;
  173. reset-names = "spi";
  174. #address-cells = <1>;
  175. #size-cells = <0>;
  176. status = "disabled";
  177. pinctrl-names = "default";
  178. pinctrl-0 = <&spi_cs1>;
  179. };
  180. uartlite: uartlite@c00 {
  181. compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
  182. reg = <0xc00 0x100>;
  183. resets = <&rstctrl 19>;
  184. reset-names = "uartl";
  185. interrupt-parent = <&intc>;
  186. interrupts = <12>;
  187. reg-shift = <2>;
  188. pinctrl-names = "default";
  189. pinctrl-0 = <&uartlite_pins>;
  190. };
  191. systick: systick@d00 {
  192. compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
  193. reg = <0xd00 0x10>;
  194. resets = <&rstctrl 28>;
  195. reset-names = "intc";
  196. interrupt-parent = <&cpuintc>;
  197. interrupts = <7>;
  198. };
  199. pcm: pcm@2000 {
  200. compatible = "ralink,mt7620a-pcm";
  201. reg = <0x2000 0x800>;
  202. resets = <&rstctrl 11>;
  203. reset-names = "pcm";
  204. interrupt-parent = <&intc>;
  205. interrupts = <4>;
  206. status = "disabled";
  207. };
  208. gdma: gdma@2800 {
  209. compatible = "ralink,mt7620a-gdma", "ralink,rt3883-gdma";
  210. reg = <0x2800 0x800>;
  211. resets = <&rstctrl 14>;
  212. reset-names = "dma";
  213. interrupt-parent = <&intc>;
  214. interrupts = <7>;
  215. #dma-cells = <1>;
  216. #dma-channels = <16>;
  217. #dma-requests = <16>;
  218. status = "disabled";
  219. };
  220. };
  221. pinctrl: pinctrl {
  222. compatible = "ralink,rt2880-pinmux";
  223. pinctrl-names = "default";
  224. pinctrl-0 = <&state_default>;
  225. state_default: pinctrl0 {
  226. };
  227. pcm_i2s_pins: pcm_i2s {
  228. pcm_i2s {
  229. ralink,group = "uartf";
  230. ralink,function = "pcm i2s";
  231. };
  232. };
  233. uartf_gpio_pins: uartf_gpio {
  234. uartf_gpio {
  235. ralink,group = "uartf";
  236. ralink,function = "gpio uartf";
  237. };
  238. };
  239. gpio_i2s_pins: gpio_i2s {
  240. gpio_i2s {
  241. ralink,group = "uartf";
  242. ralink,function = "gpio i2s";
  243. };
  244. };
  245. spi_pins: spi {
  246. spi {
  247. ralink,group = "spi";
  248. ralink,function = "spi";
  249. };
  250. };
  251. spi_cs1: spi1 {
  252. spi1 {
  253. ralink,group = "spi_cs1";
  254. ralink,function = "spi_cs1";
  255. };
  256. };
  257. i2c_pins: i2c {
  258. i2c {
  259. ralink,group = "i2c";
  260. ralink,function = "i2c";
  261. };
  262. };
  263. uartlite_pins: uartlite {
  264. uart {
  265. ralink,group = "uartlite";
  266. ralink,function = "uartlite";
  267. };
  268. };
  269. mdio_pins: mdio {
  270. mdio {
  271. ralink,group = "mdio";
  272. ralink,function = "mdio";
  273. };
  274. };
  275. ephy_pins: ephy {
  276. ephy {
  277. ralink,group = "ephy";
  278. ralink,function = "ephy";
  279. };
  280. };
  281. wled_pins: wled {
  282. wled {
  283. ralink,group = "wled";
  284. ralink,function = "wled";
  285. };
  286. };
  287. rgmii1_pins: rgmii1 {
  288. rgmii1 {
  289. ralink,group = "rgmii1";
  290. ralink,function = "rgmii1";
  291. };
  292. };
  293. rgmii2_pins: rgmii2 {
  294. rgmii2 {
  295. ralink,group = "rgmii2";
  296. ralink,function = "rgmii2";
  297. };
  298. };
  299. pcie_pins: pcie {
  300. pcie {
  301. ralink,group = "pcie";
  302. ralink,function = "pcie rst";
  303. };
  304. };
  305. };
  306. rstctrl: rstctrl {
  307. compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
  308. #reset-cells = <1>;
  309. };
  310. clkctrl: clkctrl {
  311. compatible = "ralink,rt2880-clock";
  312. #clock-cells = <1>;
  313. };
  314. usbphy: usbphy {
  315. compatible = "mediatek,mt7620-usbphy";
  316. #phy-cells = <1>;
  317. resets = <&rstctrl 22 &rstctrl 25>;
  318. reset-names = "host", "device";
  319. clocks = <&clkctrl 22 &clkctrl 25>;
  320. clock-names = "host", "device";
  321. };
  322. ethernet: ethernet@10100000 {
  323. compatible = "mediatek,mt7620-eth";
  324. reg = <0x10100000 0x10000>;
  325. #address-cells = <1>;
  326. #size-cells = <0>;
  327. interrupt-parent = <&cpuintc>;
  328. interrupts = <5>;
  329. resets = <&rstctrl 21 &rstctrl 23>;
  330. reset-names = "fe", "esw";
  331. mediatek,switch = <&gsw>;
  332. port@4 {
  333. compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
  334. reg = <4>;
  335. status = "disabled";
  336. };
  337. port@5 {
  338. compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
  339. reg = <5>;
  340. status = "disabled";
  341. };
  342. mdio-bus {
  343. #address-cells = <1>;
  344. #size-cells = <0>;
  345. status = "disabled";
  346. };
  347. };
  348. gsw: gsw@10110000 {
  349. compatible = "mediatek,mt7620-gsw";
  350. reg = <0x10110000 0x8000>;
  351. resets = <&rstctrl 23>;
  352. reset-names = "esw";
  353. interrupt-parent = <&intc>;
  354. interrupts = <17>;
  355. };
  356. sdhci: sdhci@10130000 {
  357. compatible = "ralink,mt7620-sdhci";
  358. reg = <0x10130000 0x4000>;
  359. interrupt-parent = <&intc>;
  360. interrupts = <14>;
  361. status = "disabled";
  362. };
  363. ehci: ehci@101c0000 {
  364. compatible = "generic-ehci";
  365. reg = <0x101c0000 0x1000>;
  366. interrupt-parent = <&intc>;
  367. interrupts = <18>;
  368. phys = <&usbphy 1>;
  369. phy-names = "usb";
  370. status = "disabled";
  371. };
  372. ohci: ohci@101c1000 {
  373. compatible = "generic-ohci";
  374. reg = <0x101c1000 0x1000>;
  375. interrupt-parent = <&intc>;
  376. interrupts = <18>;
  377. phys = <&usbphy 1>;
  378. phy-names = "usb";
  379. status = "disabled";
  380. };
  381. pcie: pcie@10140000 {
  382. compatible = "mediatek,mt7620-pci";
  383. reg = <0x10140000 0x100
  384. 0x10142000 0x100>;
  385. #address-cells = <3>;
  386. #size-cells = <2>;
  387. resets = <&rstctrl 26>;
  388. reset-names = "pcie0";
  389. clocks = <&clkctrl 26>;
  390. clock-names = "pcie0";
  391. interrupt-parent = <&cpuintc>;
  392. interrupts = <4>;
  393. pinctrl-names = "default";
  394. pinctrl-0 = <&pcie_pins>;
  395. device_type = "pci";
  396. bus-range = <0 255>;
  397. ranges = <
  398. 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
  399. 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
  400. >;
  401. status = "disabled";
  402. pcie-bridge {
  403. reg = <0x0000 0 0 0 0>;
  404. #address-cells = <3>;
  405. #size-cells = <2>;
  406. device_type = "pci";
  407. };
  408. };
  409. wmac: wmac@10180000 {
  410. compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
  411. reg = <0x10180000 0x40000>;
  412. interrupt-parent = <&cpuintc>;
  413. interrupts = <6>;
  414. ralink,eeprom = "soc_wmac.eeprom";
  415. };
  416. };