Rebase from upstream commit : 3bb9dcf44627ffdd313fe92c563ae454b6ff8aa6

config/Config-build.in

@@ -68,6 +68,14 @@ menu "Global build settings"
 		  This removes all ipkg/opkg status data files from the target directory
 		  before building the root filesystem.
 
+	config IPK_FILES_CHECKSUMS
+		bool
+		prompt "Record files checksums in package metadata"
+		default n
+		help
+		  This makes file checksums part of package metadata. It increases size
+		  but provides you with pkg_check command to check for flash coruptions.
+
 	config INCLUDE_CONFIG
 		bool "Include build configuration in firmware" if DEVEL
 		default n

config/Config-images.in

@@ -197,14 +197,12 @@ menu "Target Images"
 	config GRUB_CONSOLE
 		bool "Use Console Terminal (in addition to Serial)"
 		depends on GRUB_IMAGES
-		default n if (TARGET_x86_generic_Soekris45xx || TARGET_x86_generic_Soekris48xx || TARGET_x86_net5501 || TARGET_x86_geos || TARGET_x86_alix2)
 		default y
 
 	config GRUB_SERIAL
 		string "Serial port device"
 		depends on GRUB_IMAGES
-		default "hvc0" if TARGET_x86_xen_domu
-		default "ttyS0" if ! TARGET_x86_xen_domu
+		default "ttyS0"
 
 	config GRUB_BAUDRATE
 		int "Serial port baud rate"
@@ -220,7 +218,6 @@ menu "Target Images"
 	config GRUB_BOOTOPTS
 		string "Extra kernel boot options"
 		depends on GRUB_IMAGES
-		default "xencons=hvc" if TARGET_x86_xen_domu
 		help
 		  If you don't know, just leave it blank.
 
@@ -241,14 +238,14 @@ menu "Target Images"
 
 	config VDI_IMAGES
 		bool "Build VirtualBox image files (VDI)"
-		depends on TARGET_x86 || TARGET_x86_64
+		depends on TARGET_x86
 		select GRUB_IMAGES
 		select TARGET_IMAGES_PAD
 		select PACKAGE_kmod-e1000
 
 	config VMDK_IMAGES
 		bool "Build VMware image files (VMDK)"
-		depends on TARGET_x86 || TARGET_x86_64
+		depends on TARGET_x86
 		select GRUB_IMAGES
 		select TARGET_IMAGES_PAD
 		select PACKAGE_kmod-e1000
@@ -270,11 +267,12 @@ menu "Target Images"
 		int "Kernel partition size (in MB)"
 		depends on GRUB_IMAGES || USES_BOOT_PART
 		default 8 if TARGET_apm821xx_sata
+		default 20 if TARGET_brcm2708
 		default 16
 
 	config TARGET_ROOTFS_PARTSIZE
 		int "Root filesystem partition size (in MB)"
-		depends on GRUB_IMAGES || USES_ROOTFS_PART || TARGET_ROOTFS_EXT4FS || TARGET_mvebu || TARGET_rb532 || TARGET_sunxi || TARGET_uml
+		depends on GRUB_IMAGES || USES_ROOTFS_PART || TARGET_ROOTFS_EXT4FS || TARGET_mvebu || TARGET_omap || TARGET_rb532 || TARGET_sunxi || TARGET_uml
 		default 256
 		help
 		  Select the root filesystem partition size.

config/Config-kernel.in

@@ -519,6 +519,20 @@ if KERNEL_CGROUPS
 		  CONFIG_CFQ_GROUP_IOSCHED=y; for enabling throttling policy, set
 		  CONFIG_BLK_DEV_THROTTLING=y.
 
+	if KERNEL_BLK_CGROUP
+
+		config KERNEL_CFQ_GROUP_IOSCHED
+			bool "Proportional weight of disk bandwidth in CFQ"
+
+		config KERNEL_BLK_DEV_THROTTLING
+			bool "Enable throttling policy"
+			default y if TARGET_brcm2708
+
+		config KERNEL_BLK_DEV_THROTTLING_LOW
+			bool "Block throttling .low limit interface support (EXPERIMENTAL)"
+			depends on KERNEL_BLK_DEV_THROTTLING
+	endif
+
 	config KERNEL_DEBUG_BLK_CGROUP
 		bool "Enable Block IO controller debugging"
 		default n

docs/Supported_Hardware.md

@@ -1,5 +1,10 @@
 # libreCMC supported Hardware
 
+Officially supported devices generally fall into three categories : can easily
+be flashed from the stock firmware's web-ui, requires a tFTP flash or opening up
+the router. When choosing a router to use with libreCMC, please keep in mind the
+method which is required for the initial install of libreCMC.
+
 ### Buffalo
 * [WZR-HP-G300NH](/WZR_HP_G300NH.md)
 * WHR-HP-G300NH
@@ -35,3 +40,9 @@
 * DGL-5500 a1 : Ships with non-free wifi card, but can be replaced with a free one. Has a mini-pci-e card slot.
 
 #####Please note that other targets may work; we are **NOT** responsible for **ANY** _bricked_ devices.
+
+## Notes:
+
+[2] requires a tFTP server for flashing.
+
+[3] requires opening up the router / external hardware for initial install (serial cable, SPI flasher or both).

docs/ccs.md

@@ -1,42 +0,0 @@
-# CCS (Complete Corresponding Source) Requirements
-
-As a Free Software project, libreCMC works to go above and beyond its license
-obligations to be a good neighbor and to promote the ideals of Free
-Software. The project was founded on the idea that everyone should have the
-*freedom* to control the hardware they own, which means being able to fully
-control what it does and what runs on it. To ensure that everyone who uses
-libreCMC continues to have this freedom, a mechanism was added to the build
-system [1] to generate a CCS disk which OEMs and others would be able to
-distribute with devices shipping libreCMC. This was done to ease compliance and
-to push the idea that sources should be provided with a device at the time of
-sale. Shipping a CCS disk ensures that second hand sales of the device can be
-compliant if the disk is handed off with the device.
-
-
-## `make ccsdisk`
-
-A new target was created to build a CCS disk based upon the option of using an
-external repository or to use a local checkout. As it stands, this includes
-everything except for u-boot sources for a given target. In the near future, the
-libreCMC project will start including versions of u-boot for all officially
-supported targets and, going forward, make this a requirement for official
-hardware in libreCMC.
-
-
-## How to use
-
-There are two ways to use CCS disk : enable "Build the libreCMC CCS Disk" during
-image configuration or run `make ccsdisk` after all desired firmware images have
-been built. Since u-boot for a given target most likely is missing, it's
-important that the sources for u-boot be packaged and included on the disk. To
-do this, make sure they are included in `target/ccsdisk/files` with proper
-documentation. To make things a little bit easier, enabling the toolchain option
-during image configuration and using the toolchain to build u-boot will make
-things go much easier if it can be done.
-
-
-
-[1] libreCMC is a fork of OpenWrt, which both use a fork of
-[Buildroot](https://buildroot.org). Buildroot is a build system which helps to
-make it easier to create firmware images for "embedded" devices.
-

include/download.mk

@@ -6,7 +6,7 @@
 # See /LICENSE for more information.
 #
 
-PROJECT_GIT = https://git.openwrt.org
+PROJECT_GIT = https://gogs.librecmc.org/OWEALs
 
 LIBRECMC_GIT = $(PROJECT_GIT)
 LEDE_GIT = $(PROJECT_GIT)
@@ -28,7 +28,7 @@ define dl_method
 $(strip \
   $(if $(filter git,$(2)),$(call dl_method_git,$(1),$(2)),
     $(if $(2),$(2), \
-      $(if $(filter @APACHE/% @GNOME/% @GNU/% @KERNEL_LIBRE/% @KERNEL/% @SAVANNAH/% ftp://% http://% https://% file://%,$(1)),default, \
+      $(if $(filter @APACHE/% @GNOME/% @GNU/% @KERNEL_LIBRE/% @KERNEL/% @SF/% @SAVANNAH/% ftp://% http://% https://% file://%,$(1)),default, \
         $(if $(filter git://%,$(1)),$(call dl_method_git,$(1),$(2)), \
           $(if $(filter svn://%,$(1)),svn, \
             $(if $(filter cvs://%,$(1)),cvs, \

include/feeds.mk

@@ -6,7 +6,7 @@
 # See /LICENSE for more information.
 #
 
--include $(TMP_DIR)/.packagesubdirs
+-include $(TMP_DIR)/.packageauxvars
 
 FEEDS_INSTALLED:=$(notdir $(wildcard $(TOPDIR)/package/feeds/*))
 FEEDS_AVAILABLE:=$(sort $(FEEDS_INSTALLED) $(shell $(SCRIPT_DIR)/feeds list -n))
@@ -41,3 +41,8 @@ define FeedSourcesAppend
 			echo '$(if $(filter m,$(CONFIG_FEED_$(feed))),# )src/gz %d_$(feed) %U/packages/%A/$(feed)';)))) \
 ) >> $(1)
 endef
+
+# 1: package name
+define GetABISuffix
+$(if $(filter-out kmod-%,$(1)),$(if $(Package/$(1)/abiversion),$(if $(filter %0 %1 %2 %3 %4 %5 %6 %7 %8 %9,$(1)),-)$(Package/$(1)/abiversion)))
+endef

include/image-commands.mk

@@ -274,6 +274,13 @@ define Build/combined-image
 	@mv $@.new $@
 endef
 
+define Build/linksys-image
+	$(TOPDIR)/scripts/linksys-image.sh \
+		"$(call param_get_default,type,$(1),$(DEVICE_NAME))" \
+		$@ $@.new
+		mv $@.new $@
+endef
+
 define Build/openmesh-image
 	$(TOPDIR)/scripts/om-fwupgradecfg-gen.sh \
 		"$(call param_get_default,ce_type,$(1),$(DEVICE_NAME))" \
@@ -287,6 +294,20 @@ define Build/openmesh-image
 		"$(call param_get_default,rootfs,$(1),$@)" "rootfs"
 endef
 
+define Build/qsdk-ipq-factory-nand
+	$(TOPDIR)/scripts/mkits-qsdk-ipq-image.sh \
+		$@.its ubi $@
+	PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@.new
+	@mv $@.new $@
+endef
+
+define Build/qsdk-ipq-factory-nor
+	$(TOPDIR)/scripts/mkits-qsdk-ipq-image.sh \
+		$@.its hlos $(IMAGE_KERNEL) rootfs $(IMAGE_ROOTFS)
+	PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@.new
+	@mv $@.new $@
+endef
+
 define Build/senao-header
 	$(STAGING_DIR_HOST)/bin/mksenaofw $(1) -e $@ -o $@.new
 	mv $@.new $@

include/image.mk

@@ -152,6 +152,32 @@ ifdef CONFIG_TARGET_IMAGES_GZIP
   endef
 endif
 
+
+# Disable noisy checks by default as in upstream
+ifeq ($(strip $(call kernel_patchver_ge,4.6.0)),1)
+  DTC_FLAGS += -Wno-unit_address_vs_reg
+endif
+ifeq ($(strip $(call kernel_patchver_ge,4.11.0)),1)
+  DTC_FLAGS += \
+	-Wno-unit_address_vs_reg \
+	-Wno-simple_bus_reg \
+	-Wno-unit_address_format \
+	-Wno-pci_bridge \
+	-Wno-pci_device_bus_num \
+	-Wno-pci_device_reg
+endif
+ifeq ($(strip $(call kernel_patchver_ge,4.16.0)),1)
+  DTC_FLAGS += \
+	-Wno-avoid_unnecessary_addr_size \
+	-Wno-alias_paths
+endif
+ifeq ($(strip $(call kernel_patchver_ge,4.17.0)),1)
+  DTC_FLAGS += \
+	-Wno-graph_child_address \
+	-Wno-graph_port \
+	-Wno-unique_unit_address
+endif
+
 # $(1) source dts file
 # $(2) target dtb file
 # $(3) extra CPP flags
@@ -164,7 +190,7 @@ define Image/BuildDTB
 		-undef -D__DTS__ $(3) \
 		-o $(2).tmp $(1)
 	$(LINUX_DIR)/scripts/dtc/dtc -O dtb \
-		-i$(dir $(1)) $(4) \
+		-i$(dir $(1)) $(DTC_FLAGS) $(4) \
 		-o $(2) $(2).tmp
 	$(RM) $(2).tmp
 endef
@@ -203,8 +229,7 @@ define Image/mkfs/squashfs
 	$(STAGING_DIR_HOST)/bin/mksquashfs4 $(call mkfs_target_dir,$(1)) $@ \
 		-nopad -noappend -root-owned \
 		-comp $(SQUASHFSCOMP) $(SQUASHFSOPT) \
-		-processors 1 \
-		$(if $(SOURCE_DATE_EPOCH),-fixed-time $(SOURCE_DATE_EPOCH))
+		-processors 1
 endef
 
 # $(1): board name
@@ -279,8 +304,8 @@ ifdef CONFIG_TARGET_ROOTFS_CPIOGZ
 endif
 
 mkfs_packages = $(filter-out @%,$(PACKAGES_$(call param_get,pkg,pkg=$(target_params))))
-mkfs_packages_add = $(filter-out -%,$(mkfs_packages))
-mkfs_packages_remove = $(patsubst -%,%,$(filter -%,$(mkfs_packages)))
+mkfs_packages_add = $(foreach pkg,$(filter-out -%,$(mkfs_packages)),$(pkg)$(call GetABISuffix,$(pkg)))
+mkfs_packages_remove = $(foreach pkg,$(patsubst -%,%,$(filter -%,$(mkfs_packages))),$(pkg)$(call GetABISuffix,$(pkg)))
 mkfs_cur_target_dir = $(call mkfs_target_dir,pkg=$(target_params))
 
 opkg_target = \
@@ -361,12 +386,11 @@ define Device/Init
 endef
 
 DEFAULT_DEVICE_VARS := \
-  DEVICE_NAME KERNEL KERNEL_INITRAMFS KERNEL_SIZE KERNEL_INITRAMFS_IMAGE \
-  KERNEL_LOADADDR DEVICE_DTS DEVICE_DTS_CONFIG DEVICE_DTS_DIR BOARD_NAME \
-  CMDLINE UBOOTENV_IN_UBI KERNEL_IN_UBI \
-  BLOCKSIZE PAGESIZE SUBPAGESIZE VID_HDR_OFFSET \
-  UBINIZE_OPTS UIMAGE_NAME UBINIZE_PARTS \
-  SUPPORTED_DEVICES IMAGE_METADATA
+  DEVICE_NAME KERNEL KERNEL_INITRAMFS KERNEL_INITRAMFS_IMAGE KERNEL_SIZE \
+  CMDLINE UBOOTENV_IN_UBI KERNEL_IN_UBI BLOCKSIZE PAGESIZE SUBPAGESIZE \
+  VID_HDR_OFFSET UBINIZE_OPTS UBINIZE_PARTS MKUBIFS_OPTS DEVICE_DTS \
+  DEVICE_DTS_CONFIG DEVICE_DTS_DIR BOARD_NAME UIMAGE_NAME SUPPORTED_DEVICES \
+  IMAGE_METADATA KERNEL_ENTRY KERNEL_LOADADDR
 
 define Device/ExportVar
   $(1) : $(2):=$$($(2))
@@ -501,6 +525,7 @@ endef
 
 define Device/Build/artifact
   $$(_TARGET): $(BIN_DIR)/$(IMAGE_PREFIX)-$(1)
+  $(eval $(call Device/Export,$(KDIR)/tmp/$(IMAGE_PREFIX)-$(1)))
   $(KDIR)/tmp/$(IMAGE_PREFIX)-$(1): $$(KDIR_KERNEL_IMAGE)
 	@rm -f $$@
 	$$(call concat_cmd,$(ARTIFACT/$(1)))
@@ -581,7 +606,7 @@ define BuildImage
 		$(call Image/Prepare)
 
     legacy-images-prepare-make: image_prepare
-		$(MAKE) legacy-images-prepare
+		$(MAKE) legacy-images-prepare BIN_DIR="$(BIN_DIR)"
 
   else
     image_prepare:
@@ -605,7 +630,7 @@ define BuildImage
 
   legacy-images-make: install-images
 	$(call Image/mkfs/ubifs/legacy)
-	$(MAKE) legacy-images
+	$(MAKE) legacy-images BIN_DIR="$(BIN_DIR)"
 
   install: install-images
 	$(call Image/Manifest)

include/kernel-version.mk

@@ -2,15 +2,15 @@
 
 LINUX_RELEASE?=1
 
-LINUX_VERSION-3.18 = .132
-LINUX_VERSION-4.9 = .150
-LINUX_VERSION-4.14 = .93
-LINUX_VERSION-4.19 = .16
+LINUX_VERSION-3.18 = .136
+LINUX_VERSION-4.9 = .160
+LINUX_VERSION-4.14 = .103
+LINUX_VERSION-4.19 = .25
 
-LINUX_KERNEL_HASH-3.18.132 =
-LINUX_KERNEL_HASH-4.9.150 =
-LINUX_KERNEL_HASH-4.14.93 = 5a61c1b681d74216c0547da1bc3d530152fae8c92af118feff94002c39943114
-LINUX_KERNEL_HASH-4.19.16 = d3bbf6b90e3e47cc2b37f855f6cbd6cceff90a4802ae0d713439ebf91da5eeb6
+LINUX_KERNEL_HASH-3.18.136 =
+LINUX_KERNEL_HASH-4.9.160 =
+LINUX_KERNEL_HASH-4.14.103 = efebd67ba78b7c99eb9a1d2e3ceb30997e9c39f70d030d36899619a9e659ec17
+LINUX_KERNEL_HASH-4.19.25 =
 
 remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))
 sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1)))))))

include/kernel.mk

@@ -243,7 +243,7 @@ $(call KernelPackage/$(1)/config)
 				exit 1; \
 			fi; \
 		  done;
-		  $(call ModuleAutoLoad,$(1),$$(1),$(filter-out 0-,$(word 1,$(AUTOLOAD))-),$(filter-out 0,$(word 2,$(AUTOLOAD))),$(wordlist 3,99,$(AUTOLOAD)))
+		  $(call ModuleAutoLoad,$(1),$$(1),$(filter-out 0-,$(word 1,$(AUTOLOAD))-),$(filter-out 0,$(word 2,$(AUTOLOAD))),$(sort $(wordlist 3,99,$(AUTOLOAD))))
 		  $(call KernelPackage/$(1)/install,$$(1))
     endef
   $(if $(CONFIG_PACKAGE_kmod-$(1)),

include/package-dumpinfo.mk

@@ -24,7 +24,8 @@ $(if $(MENU),Menu: $(MENU)
 )$(if $(DEFAULT),Default: $(DEFAULT)
 )$(if $(findstring $(PREREQ_CHECK),1),Prereq-Check: 1
 )Version: $(VERSION)
-Depends: $(call PKG_FIXUP_DEPENDS,$(1),$(DEPENDS))
+$(if $(ABI_VERSION),ABIVersion: $(ABI_VERSION)
+)Depends: $(call PKG_FIXUP_DEPENDS,$(1),$(DEPENDS))
 Conflicts: $(CONFLICTS)
 Menu-Depends: $(MDEPENDS)
 Provides: $(PROVIDES)

include/package-ipkg.mk

@@ -13,6 +13,9 @@ endif
 IPKG_BUILD:= \
   $(SCRIPT_DIR)/ipkg-build -c -o 0 -g 0
 
+IPKG_REMOVE:= \
+  $(SCRIPT_DIR)/ipkg-remove
+
 IPKG_STATE_DIR:=$(TARGET_DIR)/usr/lib/opkg
 
 # 1: package name
@@ -90,8 +93,9 @@ _endef=endef
 
 ifeq ($(DUMP),)
   define BuildTarget/ipkg
+    ABIV_$(1):=$(call GetABISuffix,$(1))
     PDIR_$(1):=$(call FeedPackageDir,$(1))
-    IPKG_$(1):=$$(PDIR_$(1))/$(1)_$(VERSION)_$(PKGARCH).ipk
+    IPKG_$(1):=$$(PDIR_$(1))/$(1)$$(ABIV_$(1))_$(VERSION)_$(PKGARCH).ipk
     IDIR_$(1):=$(PKG_BUILD_DIR)/ipkg-$(PKGARCH)/$(1)
     KEEP_$(1):=$(strip $(call Package/$(1)/conffiles))
 
@@ -148,19 +152,20 @@ ifeq ($(DUMP),)
 	$(call locked,$(CP) $(PKG_BUILD_DIR)/.pkgdir/$(1)/. $(STAGING_DIR_ROOT)/,root-copy)
 	touch $$@
 
-    Package/$(1)/DEPENDS := $$(call mergelist,$$(filter-out @%,$$(IDEPEND_$(1))))
+    Package/$(1)/DEPENDS := $$(call mergelist,$$(foreach dep,$$(filter-out @%,$$(IDEPEND_$(1))),$$(dep)$$(call GetABISuffix,$$(dep))))
     ifneq ($$(EXTRA_DEPENDS),)
       Package/$(1)/DEPENDS := $$(EXTRA_DEPENDS)$$(if $$(Package/$(1)/DEPENDS),$$(comma) $$(Package/$(1)/DEPENDS))
     endif
 
 $(_define) Package/$(1)/CONTROL
-Package: $(1)
+Package: $(1)$$(ABIV_$(1))
 Version: $(VERSION)
 $$(call addfield,Depends,$$(Package/$(1)/DEPENDS)
 )$$(call addfield,Conflicts,$$(call mergelist,$(CONFLICTS))
-)$$(call addfield,Provides,$$(call mergelist,$(PROVIDES))
+)$$(call addfield,Provides,$$(call mergelist,$$(filter-out $(1)$$(ABIV_$(1)),$(PROVIDES)$$(if $$(ABIV_$(1)), $(1) $(foreach provide,$(PROVIDES),$(provide)$$(call GetABISuffix,$(provide))))))
 )$$(call addfield,Alternatives,$$(call mergelist,$(ALTERNATIVES))
 )$$(call addfield,Source,$(SOURCE)
+)$$(call addfield,SourceName,$(1)
 )$$(call addfield,License,$(LICENSE)
 )$$(call addfield,LicenseFiles,$(LICENSE_FILES)
 )$$(call addfield,Section,$(SECTION)
@@ -176,7 +181,7 @@ $(_endef)
     $$(IPKG_$(1)) : export DESCRIPTION=$$(Package/$(1)/description)
     $$(IPKG_$(1)) : export PATH=$$(TARGET_PATH_PKG)
     $(PKG_INFO_DIR)/$(1).provides $$(IPKG_$(1)): $(STAMP_BUILT) $(INCLUDE_DIR)/package-ipkg.mk
-	@rm -rf $$(IDIR_$(1)) $$(call opkg_package_files,$(1))
+	@rm -rf $$(IDIR_$(1)) $$(if $$(call opkg_package_files,$(1)*),; $$(IPKG_REMOVE) $(1) $$(call opkg_package_files,$(1)*))
 	mkdir -p $(PACKAGE_DIR) $$(IDIR_$(1))/CONTROL $(PKG_INFO_DIR)
 	$(call Package/$(1)/install,$$(IDIR_$(1)))
 	$(if $(Package/$(1)/install-overlay),mkdir -p $(PACKAGE_DIR) $$(IDIR_$(1))/rootfs-overlay)
@@ -194,6 +199,15 @@ $(_endef)
 	$(CheckDependencies)
 
 	$(RSTRIP) $$(IDIR_$(1))
+
+    ifneq ($$(CONFIG_IPK_FILES_CHECKSUMS),)
+	(cd $$(IDIR_$(1)); \
+		( \
+			find . -type f \! -path ./CONTROL/\* -exec sha256sum \{\} \; 2> /dev/null | \
+			sed 's|\([[:blank:]]\)\./|\1/|' > $$(IDIR_$(1))/CONTROL/files-sha256 \
+		) || true \
+	)
+    endif
 	(cd $$(IDIR_$(1))/CONTROL; \
 		( \
 			echo "$$$$CONTROL"; \
@@ -235,7 +249,7 @@ $(_endef)
 	@[ -f $$(IPKG_$(1)) ]
 
     $(1)-clean:
-	$$(if $$(call opkg_package_files,$(1)),rm -f $$(call opkg_package_files,$(1)))
+	$$(if $$(call opkg_package_files,$(1)*),$$(IPKG_REMOVE) $(1) $$(call opkg_package_files,$(1)*))
 
     clean: $(1)-clean
 

include/package.mk

@@ -81,9 +81,10 @@ STAGING_FILES_LIST:=$(PKG_DIR_NAME)$(if $(BUILD_VARIANT),.$(BUILD_VARIANT),).lis
 define CleanStaging
 	rm -f $(STAMP_INSTALLED)
 	@-(\
-		cd "$(STAGING_DIR)"; \
-		if [ -f packages/$(STAGING_FILES_LIST) ]; then \
-			cat packages/$(STAGING_FILES_LIST) | xargs -r rm -f 2>/dev/null; \
+		if [ -f $(STAGING_DIR)/packages/$(STAGING_FILES_LIST) ]; then \
+			$(SCRIPT_DIR)/clean-package.sh \
+				"$(STAGING_DIR)/packages/$(STAGING_FILES_LIST)" \
+				"$(STAGING_DIR)"; \
 		fi; \
 	)
 endef

include/prereq-build.mk

@@ -24,7 +24,7 @@ $(eval $(call TestHostCommand,case-sensitive-fs, \
 
 $(eval $(call TestHostCommand,proper-umask, \
 	Please build with umask 022 - other values produce broken packages, \
-	umask | grep -xE 00[012][012]))
+	umask | grep -xE 0?0[012][012]))
 
 $(eval $(call SetupHostCommand,gcc, \
 	Please install the GNU C Compiler (gcc) 4.8 or later, \

include/quilt.mk

@@ -94,17 +94,17 @@ endef
 
 kernel_files=$(foreach fdir,$(GENERIC_FILES_DIR) $(FILES_DIR),$(fdir)/.)
 define Kernel/Patch/Default
-	$(if $(QUILT),rm -rf $(PKG_BUILD_DIR)/patches; mkdir -p $(PKG_BUILD_DIR)/patches)
+	$(if $(QUILT),rm -rf $(LINUX_DIR)/patches; mkdir -p $(LINUX_DIR)/patches)
 	$(if $(kernel_files),$(CP) $(kernel_files) $(LINUX_DIR)/)
 	find $(LINUX_DIR)/ -name \*.rej -or -name \*.orig | $(XARGS) rm -f
 	if [ -d $(GENERIC_PLATFORM_DIR)/patches$(if $(wildcard $(GENERIC_PLATFORM_DIR)/patches-$(KERNEL_PATCHVER)),-$(KERNEL_PATCHVER)) ]; then \
 		echo "generic patches directory is present. please move your patches to the pending directory" ; \
 		exit 1; \
 	fi
-	$(call PatchDir,$(PKG_BUILD_DIR),$(GENERIC_BACKPORT_DIR),generic-backport/)
-	$(call PatchDir,$(PKG_BUILD_DIR),$(GENERIC_PATCH_DIR),generic/)
-	$(call PatchDir,$(PKG_BUILD_DIR),$(GENERIC_HACK_DIR),generic-hack/)
-	$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR),platform/)
+	$(call PatchDir,$(LINUX_DIR),$(GENERIC_BACKPORT_DIR),generic-backport/)
+	$(call PatchDir,$(LINUX_DIR),$(GENERIC_PATCH_DIR),generic/)
+	$(call PatchDir,$(LINUX_DIR),$(GENERIC_HACK_DIR),generic-hack/)
+	$(call PatchDir,$(LINUX_DIR),$(PATCH_DIR),platform/)
 endef
 
 define Quilt/RefreshDir

include/scan.mk

@@ -19,9 +19,15 @@ else
 endif
 
 ifeq ($(IS_TTY),1)
-  define progress
+  ifneq ($(strip $(NO_COLOR)),1)
+    define progress
 	printf "\033[M\r$(1)" >&2;
-  endef
+    endef
+  else
+    define progress
+	printf "\r$(1)" >&2;
+    endef
+  endif
 else
   define progress
 	:;

include/target.mk

@@ -17,7 +17,7 @@ DEFAULT_PACKAGES:=base-files libc libgcc busybox dropbear mtd uci opkg netifd fs
 # For nas targets
 DEFAULT_PACKAGES.nas:=block-mount fdisk lsblk mdadm
 # For router targets
-DEFAULT_PACKAGES.router:=dnsmasq iptables ip6tables ppp ppp-mod-pppoe firewall odhcpd-ipv6only odhcp6c kmod-ipt-offload
+DEFAULT_PACKAGES.router:=dnsmasq iptables ip6tables ppp ppp-mod-pppoa ppp-mod-pppoe firewall odhcpd-ipv6only odhcp6c kmod-ipt-offload
 DEFAULT_PACKAGES.bootloader:=
 
 ifneq ($(DUMP),)

include/toolchain-build.mk

@@ -12,6 +12,7 @@ HOST_BUILD_PREFIX:=$(TOOLCHAIN_DIR)
 BUILD_DIR_HOST:=$(BUILD_DIR_TOOLCHAIN)
 
 include $(INCLUDE_DIR)/host-build.mk
+include $(INCLUDE_DIR)/hardening.mk
 
 HOST_STAMP_PREPARED=$(HOST_BUILD_DIR)/.prepared
 

include/toplevel.mk

@@ -88,9 +88,9 @@ prepare-tmpinfo: FORCE
 		f=tmp/.$${type}info; t=tmp/.config-$${type}.in; \
 		[ "$$t" -nt "$$f" ] || ./scripts/$${type}-metadata.pl $(_ignore) config "$$f" > "$$t" || { rm -f "$$t"; echo "Failed to build $$t"; false; break; }; \
 	done
-	[ tmp/.config-feeds.in -nt tmp/.packagesubdirs ] || ./scripts/feeds feed_config > tmp/.config-feeds.in
+	[ tmp/.config-feeds.in -nt tmp/.packageauxvars ] || ./scripts/feeds feed_config > tmp/.config-feeds.in
 	./scripts/package-metadata.pl mk tmp/.packageinfo > tmp/.packagedeps || { rm -f tmp/.packagedeps; false; }
-	./scripts/package-metadata.pl subdirs tmp/.packageinfo > tmp/.packagesubdirs || { rm -f tmp/.packagesubdirs; false; }
+	./scripts/package-metadata.pl pkgaux tmp/.packageinfo > tmp/.packageauxvars || { rm -f tmp/.packageauxvars; false; }
 	touch $(TOPDIR)/tmp/.build
 
 .config: ./scripts/config/conf $(if $(CONFIG_HAVE_DOT_CONFIG),,prepare-tmpinfo)

include/u-boot.mk

@@ -42,7 +42,7 @@ TARGET_DEP = TARGET_$(BUILD_TARGET)$(if $(BUILD_SUBTARGET),_$(BUILD_SUBTARGET))
 
 UBOOT_MAKE_FLAGS = \
 	HOSTCC="$(HOSTCC)" \
-	HOSTCFLAGS="$(HOST_CFLAGS) $(HOST_CPPFLAGS)" \
+	HOSTCFLAGS="$(HOST_CFLAGS) $(HOST_CPPFLAGS) -std=gnu11" \
 	HOSTLDFLAGS="$(HOST_LDFLAGS)"
 
 define Build/U-Boot/Target

include/upstream.mk

@@ -1,19 +0,0 @@
-#
-# Copyright (c) libreCMC Project <info@librecmc.org>
-# Copyright (c) Robert Call <bob@bobcall.me>
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-
-EXCLUDE_DIRS:=target/linux/ath79/* \
-	target/linux/ar71xx/* \
-	target/linux/x86/* \
-	target/linux/xburst/* \
-	target/linux/Makefile \
-
-
-find ./ $(foreach exclude,$(EXCLUDE_DIRS),! --path"$(exclude)")
-
-
-clean_src:
-	

include/version.mk

@@ -42,16 +42,16 @@ VERSION_MANUFACTURER:=$(call qstrip,$(CONFIG_VERSION_MANUFACTURER))
 VERSION_MANUFACTURER:=$(if $(VERSION_MANUFACTURER),$(VERSION_MANUFACTURER),libreCMC)
 
 VERSION_MANUFACTURER_URL:=$(call qstrip,$(CONFIG_VERSION_MANUFACTURER_URL))
-VERSION_MANUFACTURER_URL:=$(if $(VERSION_MANUFACTURER_URL),$(VERSION_MANUFACTURER_URL),https://librecmc.org)
+VERSION_MANUFACTURER_URL:=$(if $(VERSION_MANUFACTURER_URL),$(VERSION_MANUFACTURER_URL),https://librecmc.org/)
 
 VERSION_BUG_URL:=$(call qstrip,$(CONFIG_VERSION_BUG_URL))
-VERSION_BUG_URL:=$(if $(VERSION_BUG_URL),$(VERSION_BUG_URL),https://gogs.librecmc.org/librecmc/librecmc/issues)
+VERSION_BUG_URL:=$(if $(VERSION_BUG_URL),$(VERSION_BUG_URL),https://gogs.librecmc.org/libreCMC/libreCMC/issues)
 
 VERSION_HOME_URL:=$(call qstrip,$(CONFIG_VERSION_HOME_URL))
-VERSION_HOME_URL:=$(if $(VERSION_HOME_URL),$(VERSION_HOME_URL),https://librecmc.org)
+VERSION_HOME_URL:=$(if $(VERSION_HOME_URL),$(VERSION_HOME_URL),https://librecmc.org/)
 
 VERSION_SUPPORT_URL:=$(call qstrip,$(CONFIG_VERSION_SUPPORT_URL))
-VERSION_SUPPORT_URL:=$(if $(VERSION_SUPPORT_URL),$(VERSION_SUPPORT_URL))
+VERSION_SUPPORT_URL:=$(if $(VERSION_SUPPORT_URL),$(VERSION_SUPPORT_URL),http://forum.lede-project.org/)
 
 VERSION_PRODUCT:=$(call qstrip,$(CONFIG_VERSION_PRODUCT))
 VERSION_PRODUCT:=$(if $(VERSION_PRODUCT),$(VERSION_PRODUCT),Generic)

package/Makefile

@@ -66,7 +66,7 @@ $(curdir)/install: $(TMP_DIR)/.build $(curdir)/merge $(if $(CONFIG_TARGET_PER_DE
 	rm -rf $(TARGET_DIR) $(TARGET_DIR_ORIG)
 	mkdir -p $(TARGET_DIR)/tmp
 	$(call opkg,$(TARGET_DIR)) install \
-		$(call opkg_package_files,$(shell cat $(PACKAGE_INSTALL_FILES) 2>/dev/null))
+		$(call opkg_package_files,$(foreach pkg,$(shell cat $(PACKAGE_INSTALL_FILES) 2>/dev/null),$(pkg)$(call GetABISuffix,$(pkg))))
 	@for file in $(PACKAGE_INSTALL_FILES); do \
 		[ -s $$file.flags ] || continue; \
 		for flag in `cat $$file.flags`; do \
@@ -84,7 +84,7 @@ $(curdir)/index: FORCE
 		mkdir -p $$d; \
 		cd $$d || continue; \
 		$(SCRIPT_DIR)/ipkg-make-index.sh . 2>&1 > Packages.manifest; \
-		grep -vE '^(Maintainer|LicenseFiles|Source|Require)' Packages.manifest > Packages && \
+		grep -vE '^(Maintainer|LicenseFiles|Source|SourceName|Require)' Packages.manifest > Packages && \
 			gzip -9nc Packages > Packages.gz; \
 	); done
 ifdef CONFIG_SIGNED_PACKAGES

package/base-files/Makefile

@@ -12,7 +12,7 @@ include $(INCLUDE_DIR)/version.mk
 include $(INCLUDE_DIR)/feeds.mk
 
 PKG_NAME:=base-files
-PKG_RELEASE:=196
+PKG_RELEASE:=197
 PKG_FLAGS:=nonshared
 
 PKG_FILE_DEPENDS:=$(PLATFORM_DIR)/ $(GENERIC_PLATFORM_DIR)/base-files/
@@ -195,6 +195,8 @@ define Package/base-files/install
 		mkdir -p $(1)/etc/opkg; \
 		$(call FeedSourcesAppend,$(1)/etc/opkg/distfeeds.conf); \
 		$(VERSION_SED_SCRIPT) $(1)/etc/opkg/distfeeds.conf)
+	$(if $(CONFIG_IPK_FILES_CHECKSUMS), \
+		rm -f $(1)/sbin/pkg_check,)
 endef
 
 ifneq ($(DUMP),1)

package/base-files/files/bin/config_generate

@@ -244,10 +244,10 @@ generate_static_system() {
 		set system.ntp='timeserver'
 		set system.ntp.enabled='1'
 		set system.ntp.enable_server='0'
-		add_list system.ntp.server='0.openwrt.pool.ntp.org'
-		add_list system.ntp.server='1.openwrt.pool.ntp.org'
-		add_list system.ntp.server='2.openwrt.pool.ntp.org'
-		add_list system.ntp.server='3.openwrt.pool.ntp.org'
+		add_list system.ntp.server='0.librecmc.pool.ntp.org'
+		add_list system.ntp.server='1.librecmc.pool.ntp.org'
+		add_list system.ntp.server='2.librecmc.pool.ntp.org'
+		add_list system.ntp.server='3.librecmc.pool.ntp.org'
 	EOF
 
 	if json_is_a system object; then

package/base-files/files/etc/init.d/system

@@ -6,7 +6,7 @@ USE_PROCD=1
 
 validate_system_section()
 {
-	uci_validate_section system system "${1}" \
+	uci_load_validate system system "$1" "$2" \
 		'hostname:string:libreCMC' \
 		'conloglevel:uinteger' \
 		'buffersize:uinteger' \
@@ -15,11 +15,7 @@ validate_system_section()
 }
 
 system_config() {
-	local cfg="$1"
-
-	local hostname conloglevel buffersize timezone zonename
-
-	validate_system_section "${1}" || {
+	[ "$2" = 0 ] || {
 		echo "validation failed"
 		return 1
 	}
@@ -36,7 +32,7 @@ system_config() {
 
 reload_service() {
 	config_load system
-	config_foreach system_config system
+	config_foreach validate_system_section system system_config
 }
 
 service_triggers()

package/base-files/files/etc/sysctl.d/10-default.conf

@@ -8,6 +8,8 @@ fs.suid_dumpable=2
 fs.protected_hardlinks=1
 fs.protected_symlinks=1
 
+net.core.bpf_jit_enable=1
+
 net.ipv4.conf.default.arp_ignore=1
 net.ipv4.conf.all.arp_ignore=1
 net.ipv4.ip_forward=1

package/base-files/files/lib/functions.sh

@@ -92,7 +92,7 @@ config_unset() {
 # config_get <section> <option>
 config_get() {
 	case "$3" in
-		"") eval echo "\${CONFIG_${1}_${2}:-\${4}}";;
+		"") eval echo "\"\${CONFIG_${1}_${2}:-\${4}}\"";;
 		*)  eval export ${NO_EXPORT:+-n} -- "${1}=\${CONFIG_${2}_${3}:-\${4}}";;
 	esac
 }

package/base-files/files/lib/upgrade/common.sh

@@ -223,9 +223,9 @@ indicate_upgrade() {
 default_do_upgrade() {
 	sync
 	if [ "$SAVE_CONFIG" -eq 1 ]; then
-		get_image "$1" "$2" | mtd $MTD_CONFIG_ARGS -j "$CONF_TAR" write - "${PART_NAME:-image}"
+		get_image "$1" "$2" | mtd $MTD_ARGS $MTD_CONFIG_ARGS -j "$CONF_TAR" write - "${PART_NAME:-image}"
 	else
-		get_image "$1" "$2" | mtd write - "${PART_NAME:-image}"
+		get_image "$1" "$2" | mtd $MTD_ARGS write - "${PART_NAME:-image}"
 	fi
 	[ $? -ne 0 ] && exit 1
 }

package/base-files/files/lib/upgrade/fwtool.sh

@@ -9,7 +9,7 @@ fwtool_check_signature() {
 		fi
 	}
 
-	if ! fwtool -q -t -s /tmp/sysupgrade.ucert "$1"; then
+	if ! fwtool -q -s /tmp/sysupgrade.ucert "$1"; then
 		echo "Image signature not found"
 		[ "$REQUIRE_IMAGE_SIGNATURE" = 1 -a "$FORCE" != 1 ] && {
 			echo "Use sysupgrade -F to override this check when downgrading or flashing to vendor firmware"
@@ -18,7 +18,8 @@ fwtool_check_signature() {
 		return 0
 	fi
 
-	ucert -V -m "$1" -c "/tmp/sysupgrade.ucert" -P /etc/opkg/keys
+	fwtool -q -T -s /dev/null "$1" | \
+		ucert -V -m - -c "/tmp/sysupgrade.ucert" -P /etc/opkg/keys
 
 	return $?
 }

package/base-files/files/sbin/pkg_check

@@ -0,0 +1,130 @@
+#!/bin/sh
+#
+# Package checksums checking script
+# (C) 2018 CZ.NIC, z.s.p.o.
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+
+ERRFATAL="no"
+QUIET="yes"
+MISSING=""
+SUMMARY=""
+NL="
+"
+
+# Arguments parsing
+while expr "x$1" : "x-" > /dev/null; do
+	if [ "x$1" = "x-s" ]; then
+		ERRFATAL="yes"
+		shift
+	elif [ "x$1" = "x-v" ]; then
+		QUIET="	no"
+		shift
+	else
+		echo "Usage: $(basename $0) [-s] [-v] [pkg1 pkg2 ...]"
+		echo
+		echo "   -s   Stop on first change"
+		echo "   -v   Verbose"
+		if [ "x$1" = "x-h" ]; then
+			exit 0
+		else
+			echo
+			echo "ERROR: Unknown option '$1'"
+			exit 1
+		fi
+	fi
+done
+
+# Check all packages by default
+if [ -z "$1" ]; then
+	set $(cd /usr/lib/opkg/info/; for i in *.files-sha256sum; do basename $i .files-sha256sum; done)
+fi
+
+# Iterate over packages
+while [ "$1" ]; do
+	if [ \! -f "/usr/lib/opkg/info/$1.files-sha256sum" ]; then
+		if [ "$ERRFATAL" = no ]; then
+			echo " * No checksums for $1 - skipping"
+			echo
+		else
+			echo " * No checksums for $1 - exiting"
+			exit 1
+		fi
+		if [ -z "$MISSING" ]; then
+			MISSING="$1"
+		else
+			MISSING="$MISSING, $1"
+		fi
+		shift
+		continue
+	fi
+	[ $QUIET = yes ] || echo " * Checking package $1:"
+	ERR=""
+	CHECK="`sha256sum -c /usr/lib/opkg/info/$1.files-sha256sum 2> /dev/null`"
+
+	# Are the changed files config files?
+	if [ $? -ne 0 ] && [ "`cat "/usr/lib/opkg/info/$1.files-sha256sum"`" ]; then
+		NEWCHECK="`echo "$CHECK" | grep '^.*: OK$'`"
+		for i in `echo "$CHECK" | sed -n 's|^\(.*\): FAILED$|\1|p'`; do
+			if [ "`grep "^$i\$" "/usr/lib/opkg/info/$1.conffiles" 2> /dev/null`" ] || \
+			   [ "`echo "$i" | grep "^/etc/uci-defaults/"`" ]; then
+				NEWCHECK="${NEWCHECK}${NL}${i}: CONFIGURED"
+			else
+				NEWCHECK="${NEWCHECK}${NL}${i}: FAILED"
+				ERR="y"
+			fi
+		done
+		CHECK="$NEWCHECK"
+	fi
+
+	# Do we have changed files or not?
+	if [ -z "$ERR" ]; then
+		[ $QUIET = yes ] || [ -z "`cat "/usr/lib/opkg/info/$1.files-sha256sum"`" ] || echo "$CHECK" | sed 's|^|   - |'
+		[ $QUIET = yes ] || echo " * Package $1 is ok"
+		[ $QUIET = yes ] || echo
+	else
+		if [ $QUIET = yes ]; then
+			echo " * Changes found in package $1:"
+			echo "$CHECK" | sed -n 's|^\(.*:[[:blank:]]*FAILED\)$|   - \1|p'
+		else
+			echo "$CHECK" | sed 's|^|   - |'
+			echo " * Changes found in package $1!"
+		fi
+		if [ "$ERRFATAL" = yes ]; then
+			echo
+			echo "Exiting on first change found!"
+			exit 1
+		fi
+		for i in `echo "$CHECK" | sed -n 's|^\(.*\): FAILED$|\1|p'`; do
+			SUMMARY="${SUMMARY}${NL} - $1: $i"
+		done
+		echo
+	fi
+	shift
+done
+
+# If there are changed files, report them
+if [ "$SUMMARY" ]; then
+	echo "Some packages contain changed files!"
+	echo "Maybe something worth looking into?"
+	echo "Here is the list of packages and changed files:"
+	echo "$SUMMARY"
+fi
+if [ "$MISSING" ]; then
+	echo "Following packages are missing checksums: $MISSING"
+fi
+if [ "$MISSING" ] || [ "$SUMMARY" ]; then
+	exit 1
+fi

package/base-files/files/sbin/sysupgrade

@@ -4,6 +4,7 @@
 . /lib/functions/system.sh
 
 # initialize defaults
+export MTD_ARGS=""
 export MTD_CONFIG_ARGS=""
 export INTERACTIVE=0
 export VERBOSE=1

package/boot/fconfig/Makefile

@@ -1,45 +0,0 @@
-#
-# Copyright (C) 2006-2008 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-
-PKG_NAME:=fconfig
-PKG_VERSION:=20080329
-PKG_RELEASE:=1
-
-PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
-PKG_SOURCE_URL:=https://downloads.openwrt.org/sources
-PKG_HASH:=4ff0e8f07e35e46b705c0dbe9d9544ede01ea092a69e3f7db03e55a3f2bb8eb7
-
-PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)
-
-include $(INCLUDE_DIR)/package.mk
-
-define Package/fconfig
-  SECTION:=utils
-  CATEGORY:=Utilities
-  SUBMENU:=Boot Loaders
-  TITLE:=RedBoot configuration editor
-endef
-
-define Package/fconfig/description
-	displays and (if writable) also edits the RedBoot configuration.
-endef
-
-define Build/Configure
-endef
-
-define Build/Compile
-	$(call Build/Compile/Default)
-endef
-
-define Package/fconfig/install
-	$(INSTALL_DIR) $(1)/usr/sbin
-	$(INSTALL_BIN) $(PKG_BUILD_DIR)/fconfig $(1)/usr/sbin/
-endef
-
-$(eval $(call BuildPackage,fconfig))

package/boot/grub2/Makefile

@@ -33,7 +33,7 @@ define Package/grub2
   SECTION:=boot
   TITLE:=GRand Unified Bootloader
   URL:=http://www.gnu.org/software/grub/
-  DEPENDS:=@TARGET_x86||TARGET_x86_64
+  DEPENDS:=@TARGET_x86
 endef
 
 define Package/grub2-editenv
@@ -42,7 +42,7 @@ define Package/grub2-editenv
   SUBMENU:=Boot Loaders
   TITLE:=Grub2 Environment editor
   URL:=http://www.gnu.org/software/grub/
-  DEPENDS:=@TARGET_x86||TARGET_x86_64
+  DEPENDS:=@TARGET_x86
 endef
 
 define Package/grub2-editenv/description

package/boot/uboot-ar71xx/Makefile

@@ -1,33 +0,0 @@
-#
-# Copyright (C) 2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-
-PKG_VERSION:=2010.03
-PKG_RELEASE:=1
-
-PKG_HASH:=902d1b2c15787df55186fae4033685fb0c5a5a12755a08383e97c4a3e255925b
-
-include $(INCLUDE_DIR)/u-boot.mk
-include $(INCLUDE_DIR)/package.mk
-
-define U-Boot/Default
-  BUILD_TARGET:=ar71xx
-  BUILD_SUBTARGET:=generic
-endef
-
-define U-Boot/nbg460n_550n_550nh
-  TITLE:=NBG460N/550N/550NH routers
-  BUILD_DEVICES:=NBG_460N_550N_550NH
-  HIDDEN:=y
-endef
-
-UBOOT_MAKE_FLAGS :=
-
-UBOOT_TARGETS:=nbg460n_550n_550nh
-
-$(eval $(call BuildPackage/U-Boot))

package/boot/uboot-ar71xx/patches/0001-upstream-Reproducible-U-Boot-build-support-using-SOURCE_DATE_.patch

@@ -1,82 +0,0 @@
-From f3f431a712729a1af94d01bd1bfde17a252ff02c Mon Sep 17 00:00:00 2001
-From: Paul Kocialkowski <contact@paulk.fr>
-Date: Sun, 26 Jul 2015 18:48:15 +0200
-Subject: [PATCH] Reproducible U-Boot build support, using SOURCE_DATE_EPOCH
-
-In order to achieve reproducible builds in U-Boot, timestamps that are defined
-at build-time have to be somewhat eliminated. The SOURCE_DATE_EPOCH environment
-variable allows setting a fixed value for those timestamps.
-
-Simply by setting SOURCE_DATE_EPOCH to a fixed value, a number of targets can be
-built reproducibly. This is the case for e.g. sunxi devices.
-
-However, some other devices might need some more tweaks, especially regarding
-the image generation tools.
-
-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
----
- Makefile              |  7 ++++---
- README                | 12 ++++++++++++
- tools/default_image.c | 21 ++++++++++++++++++++-
- 3 files changed, 36 insertions(+), 4 deletions(-)
-
---- a/README
-+++ b/README
-@@ -2785,6 +2785,18 @@ Low Level (hardware related) configurati
- 		that is executed before the actual U-Boot. E.g. when
- 		compiling a NAND SPL.
- 
-+Reproducible builds
-+-------------------
-+
-+In order to achieve reproducible builds, timestamps used in the U-Boot build
-+process have to be set to a fixed value.
-+
-+This is done using the SOURCE_DATE_EPOCH environment variable.
-+SOURCE_DATE_EPOCH is to be set on the build host's shell, not as a configuration
-+option for U-Boot or an environment variable in U-Boot.
-+
-+SOURCE_DATE_EPOCH should be set to a number of seconds since the epoch, in UTC.
-+
- Building the Software:
- ======================
- 
---- a/tools/default_image.c
-+++ b/tools/default_image.c
-@@ -101,6 +101,9 @@ static void image_set_header (void *ptr,
- 				struct mkimage_params *params)
- {
- 	uint32_t checksum;
-+	char *source_date_epoch;
-+	struct tm *time_universal;
-+	time_t time;
- 
- 	image_header_t * hdr = (image_header_t *)ptr;
- 
-@@ -109,9 +112,25 @@ static void image_set_header (void *ptr,
- 				sizeof(image_header_t)),
- 			sbuf->st_size - sizeof(image_header_t));
- 
-+source_date_epoch = getenv("SOURCE_DATE_EPOCH");
-+	if (source_date_epoch != NULL) {
-+		time = (time_t) strtol(source_date_epoch, NULL, 10);
-+
-+		time_universal = gmtime(&time);
-+		if (time_universal == NULL) {
-+			fprintf(stderr, "%s: SOURCE_DATE_EPOCH is not valid\n",
-+				__func__);
-+			time = 0;
-+		} else {
-+			time = mktime(time_universal);
-+		}
-+	} else {
-+		time = sbuf->st_mtime;
-+	}
-+
- 	/* Build new header */
- 	image_set_magic (hdr, IH_MAGIC);
--	image_set_time (hdr, sbuf->st_mtime);
-+	image_set_time(hdr, time);
- 	image_set_size (hdr, sbuf->st_size - sizeof(image_header_t));
- 	image_set_load (hdr, params->addr);
- 	image_set_ep (hdr, params->ep);

package/boot/uboot-ar71xx/patches/0002-upstream-Makefile-Reproducible-U-Boot-build-support.patch

@@ -1,31 +0,0 @@
---- a/Makefile
-+++ b/Makefile
-@@ -389,8 +389,26 @@ $(VERSION_FILE):
- 		@cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
- 
- $(TIMESTAMP_FILE):
--		@date +'#define U_BOOT_DATE "%b %d %C%y"' > $@
--		@date +'#define U_BOOT_TIME "%T"' >> $@
-+	(if test -n "$${SOURCE_DATE_EPOCH}"; then \
-+                SOURCE_DATE="@$${SOURCE_DATE_EPOCH}"; \
-+                DATE=""; \
-+                for date in gdate date.gnu date; do \
-+                        $${date} -u -d "$${SOURCE_DATE}" >/dev/null 2>&1 && DATE="$${date}"; \
-+                done; \
-+                if test -n "$${DATE}"; then \
-+                        LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE "%b %d %C%y"' > $@; \
-+                        LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"' >> $@; \
-+                        LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"' >> $@; \
-+                        LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"' >> $@; \
-+                else \
-+                        return 42; \
-+                fi; \
-+        else \
-+                LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \
-+                LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
-+                LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \
-+                LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
-+        fi)
- 
- gdbtools:
- 		$(MAKE) -C tools/gdb all || exit 1

package/boot/uboot-ar71xx/patches/001-ar71xx.patch

@@ -1,26 +0,0 @@
---- a/cpu/mips/Makefile
-+++ b/cpu/mips/Makefile
-@@ -33,6 +33,7 @@ SOBJS-$(CONFIG_INCA_IP)	+= incaip_wdt.o
- COBJS-$(CONFIG_INCA_IP)	+= asc_serial.o incaip_clock.o
- COBJS-$(CONFIG_PURPLE)	+= asc_serial.o
- COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
-+COBJS-$(CONFIG_AR71XX)	+= ar71xx_serial.o
- 
- SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
- OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
---- a/Makefile
-+++ b/Makefile
-@@ -3474,6 +3474,13 @@ qemu_mips_config	: unconfig
- 	@$(MKCONFIG) -a qemu-mips mips mips qemu-mips
- 
- #########################################################################
-+## MIPS32 AR71XX (24K)
-+#########################################################################
-+
-+nbg460n_550n_550nh_config : 	unconfig
-+	@$(MKCONFIG) -a nbg460n mips mips nbg460n zyxel
-+
-+#########################################################################
- ## MIPS64 5Kc
- #########################################################################
- 

package/boot/uboot-ar71xx/patches/002-ar71xx-spi.patch

@@ -1,11 +0,0 @@
-diff -ur u-boot-2010.03/drivers/spi/Makefile u-boot-nbg/drivers/spi/Makefile
---- u-boot-2010.03/drivers/spi/Makefile	2010-03-31 23:54:39.000000000 +0200
-+++ u-boot-nbg/drivers/spi/Makefile	2010-04-15 19:31:27.000000000 +0200
-@@ -25,6 +25,7 @@
- 
- LIB	:= $(obj)libspi.a
- 
-+COBJS-$(CONFIG_AR71XX_SPI) += ar71xx_spi.o
- COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
- COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
- COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o

package/boot/uboot-ar71xx/patches/010-enet-ag71xx.patch

@@ -1,22 +0,0 @@
-diff -ur u-boot-2010.03/drivers/net/Makefile u-boot-nbg/drivers/net/Makefile
---- u-boot-2010.03/drivers/net/Makefile	2010-03-31 23:54:39.000000000 +0200
-+++ u-boot-nbg/drivers/net/Makefile	2010-04-19 23:30:01.000000000 +0200
-@@ -27,6 +27,7 @@
- 
- COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
- COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
-+COBJS-$(CONFIG_AG71XX) += ag71xx.o
- COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
- COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
- COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o
-diff -ur u-boot-2010.03/include/netdev.h u-boot-nbg/include/netdev.h
---- u-boot-2010.03/include/netdev.h	2010-03-31 23:54:39.000000000 +0200
-+++ u-boot-nbg/include/netdev.h	2010-05-02 11:30:58.000000000 +0200
-@@ -42,6 +42,7 @@
- 
- /* Driver initialization prototypes */
- int au1x00_enet_initialize(bd_t*);
-+int ag71xx_register(bd_t * bis, char *phyname[], u16 phyid[], u16 phyfixed[]);
- int at91emac_register(bd_t *bis, unsigned long iobase);
- int bfin_EMAC_initialize(bd_t *bis);
- int cs8900_initialize(u8 dev_num, int base_addr);

package/boot/uboot-ar71xx/patches/011-switch-rtl8366sr.patch

@@ -1,28 +0,0 @@
-diff -ur u-boot-2010.03/drivers/net/Makefile u-boot-nbg/drivers/net/Makefile
---- u-boot-2010.03/drivers/net/Makefile	2010-03-31 23:54:39.000000000 +0200
-+++ u-boot-nbg/drivers/net/Makefile	2010-04-19 23:30:01.000000000 +0200
-@@ -65,6 +65,7 @@
- COBJS-$(CONFIG_DRIVER_RTL8019) += rtl8019.o
- COBJS-$(CONFIG_RTL8139) += rtl8139.o
- COBJS-$(CONFIG_RTL8169) += rtl8169.o
-+COBJS-$(CONFIG_RTL8366_MII) += phy/rtl8366_mii.o
- COBJS-$(CONFIG_DRIVER_S3C4510_ETH) += s3c4510b_eth.o
- COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
- COBJS-$(CONFIG_SMC91111) += smc91111.o
-diff -ur u-boot-2010.03/include/netdev.h u-boot-nbg/include/netdev.h
---- u-boot-2010.03/include/netdev.h	2010-03-31 23:54:39.000000000 +0200
-+++ u-boot-nbg/include/netdev.h	2010-05-02 11:30:58.000000000 +0200
-@@ -175,5 +175,13 @@
- 
- int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
- #endif /* CONFIG_MV88E61XX_SWITCH */
-+
-+#if defined(CONFIG_RTL8366_MII)
-+#define RTL8366_DEVNAME         "rtl8366"
-+#define RTL8366_WANPHY_ID       4
-+#define RTL8366_LANPHY_ID       -1
-+int rtl8366_mii_register(bd_t *bis);
-+int rtl8366s_initialize(void);
-+#endif
- 
- #endif /* _NETDEV_H_ */

package/boot/uboot-ar71xx/patches/020-freebsd-compat.patch

@@ -1,11 +0,0 @@
---- a/include/compiler.h
-+++ b/include/compiler.h
-@@ -46,7 +46,7 @@ extern int errno;
- #ifdef __linux__
- # include <endian.h>
- # include <byteswap.h>
--#elif defined(__MACH__)
-+#elif defined(__MACH__) || defined(__FreeBSD__)
- # include <machine/endian.h>
- typedef unsigned long ulong;
- typedef unsigned int  uint;

package/boot/uboot-ar71xx/patches/021-darwin_compat.patch

@@ -1,23 +0,0 @@
---- a/config.mk
-+++ b/config.mk
-@@ -64,9 +64,17 @@ HOSTSTRIP	= strip
- #
- 
- ifeq ($(HOSTOS),darwin)
--HOSTCC		= cc
--HOSTCFLAGS	+= -traditional-cpp
--HOSTLDFLAGS	+= -multiply_defined suppress
-+#get the major and minor product version (e.g. '10' and '6' for Snow Leopard)
-+DARWIN_MAJOR_VERSION   = $(shell sw_vers -productVersion | cut -f 1 -d '.')
-+DARWIN_MINOR_VERSION   = $(shell sw_vers -productVersion | cut -f 2 -d '.')
-+
-+before-snow-leopard    = $(shell if [ $(DARWIN_MAJOR_VERSION) -le 10 -a \
-+   $(DARWIN_MINOR_VERSION) -le 5 ] ; then echo "$(1)"; else echo "$(2)"; fi ;)
-+
-+# Snow Leopards build environment has no longer restrictions as described above
-+HOSTCC  = $(call before-snow-leopard, "cc", "gcc")
-+HOSTCFLAGS += $(call before-snow-leopard, "-traditional-cpp")
-+HOSTLDFLAGS    += $(call before-snow-leopard, "-multiply_defined suppress")
- else
- HOSTCC		= gcc
- endif

package/boot/uboot-ar71xx/patches/022-getline_backport.patch

@@ -1,21 +0,0 @@
---- a/tools/os_support.c
-+++ b/tools/os_support.c
-@@ -23,6 +23,6 @@
- #ifdef __MINGW32__
- #include "mingw_support.c"
- #endif
--#ifdef __APPLE__
-+#if defined(__APPLE__) && __DARWIN_C_LEVEL < 200809L
- #include "getline.c"
- #endif
---- a/tools/os_support.h
-+++ b/tools/os_support.h
-@@ -28,7 +28,7 @@
- #include "mingw_support.h"
- #endif
- 
--#ifdef __APPLE__
-+#if defined(__APPLE__) && __DARWIN_C_LEVEL < 200809L
- #include "getline.h"
- #endif
- 

package/boot/uboot-ar71xx/patches/030-no_examples.patch

@@ -1,13 +0,0 @@
---- a/Makefile
-+++ b/Makefile
-@@ -139,9 +139,7 @@ endif
- 
- # The "tools" are needed early, so put this first
- # Don't include stuff already done in $(LIBS)
--SUBDIRS	= tools \
--	  examples/standalone \
--	  examples/api
-+SUBDIRS	= tools
- 
- .PHONY : $(SUBDIRS)
- 

package/boot/uboot-ar71xx/patches/040-no_extern_inline.patch

@@ -1,112 +0,0 @@
---- a/include/asm-mips/io.h
-+++ b/include/asm-mips/io.h
-@@ -118,12 +118,12 @@ static inline void set_io_port_base(unsi
-  * Change virtual addresses to physical addresses and vv.
-  * These are trivial on the 1:1 Linux/MIPS mapping
-  */
--extern inline phys_addr_t virt_to_phys(volatile void * address)
-+static inline phys_addr_t virt_to_phys(volatile void * address)
- {
- 	return CPHYSADDR(address);
- }
- 
--extern inline void * phys_to_virt(unsigned long address)
-+static inline void * phys_to_virt(unsigned long address)
- {
- 	return (void *)KSEG0ADDR(address);
- }
-@@ -131,12 +131,12 @@ extern inline void * phys_to_virt(unsign
- /*
-  * IO bus memory addresses are also 1:1 with the physical address
-  */
--extern inline unsigned long virt_to_bus(volatile void * address)
-+static inline unsigned long virt_to_bus(volatile void * address)
- {
- 	return CPHYSADDR(address);
- }
- 
--extern inline void * bus_to_virt(unsigned long address)
-+static inline void * bus_to_virt(unsigned long address)
- {
- 	return (void *)KSEG0ADDR(address);
- }
-@@ -150,12 +150,12 @@ extern unsigned long isa_slot_offset;
- extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
- 
- #if 0
--extern inline void *ioremap(unsigned long offset, unsigned long size)
-+static inline void *ioremap(unsigned long offset, unsigned long size)
- {
- 	return __ioremap(offset, size, _CACHE_UNCACHED);
- }
- 
--extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)
-+static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
- {
- 	return __ioremap(offset, size, _CACHE_UNCACHED);
- }
-@@ -238,7 +238,7 @@ out:
-  */
- 
- #define __OUT1(s) \
--extern inline void __out##s(unsigned int value, unsigned int port) {
-+static inline void __out##s(unsigned int value, unsigned int port) {
- 
- #define __OUT2(m) \
- __asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
-@@ -252,7 +252,7 @@ __OUT1(s##c_p) __OUT2(m) : : "r" (__iosw
- 	SLOW_DOWN_IO; }
- 
- #define __IN1(t,s) \
--extern __inline__ t __in##s(unsigned int port) { t _v;
-+static inline t __in##s(unsigned int port) { t _v;
- 
- /*
-  * Required nops will be inserted by the assembler
-@@ -267,7 +267,7 @@ __IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i
- __IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); }
- 
- #define __INS1(s) \
--extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
-+static inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
- 
- #define __INS2(m) \
- if (count) \
-@@ -295,7 +295,7 @@ __INS1(s##c) __INS2(m) \
- 	: "$1");}
- 
- #define __OUTS1(s) \
--extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
-+static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
- 
- #define __OUTS2(m) \
- if (count) \
---- a/include/asm-mips/system.h
-+++ b/include/asm-mips/system.h
-@@ -23,7 +23,7 @@
- #include <linux/kernel.h>
- #endif
- 
--extern __inline__ void
-+static inline void
- __sti(void)
- {
- 	__asm__ __volatile__(
-@@ -47,7 +47,7 @@ __sti(void)
-  * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
-  * no nops at all.
-  */
--extern __inline__ void
-+static inline void
- __cli(void)
- {
- 	__asm__ __volatile__(
-@@ -208,7 +208,7 @@ do { \
-  * For 32 and 64 bit operands we can take advantage of ll and sc.
-  * FIXME: This doesn't work for R3000 machines.
-  */
--extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
-+static inline unsigned long xchg_u32(volatile int * m, unsigned long val)
- {
- #ifdef CONFIG_CPU_HAS_LLSC
- 	unsigned long dummy;

package/boot/uboot-ar71xx/patches/041-no_weak_alias.patch

@@ -1,12 +0,0 @@
---- a/common/main.c
-+++ b/common/main.c
-@@ -47,8 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
- /*
-  * Board-specific Platform code can reimplement show_boot_progress () if needed
-  */
--void inline __show_boot_progress (int val) {}
--void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress")));
-+void __attribute__((weak)) show_boot_progress(int val) {}
- 
- #if defined(CONFIG_BOOT_RETRY_TIME) && defined(CONFIG_RESET_TO_RETRY)
- extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);		/* for do_reset() prototype */

package/boot/uboot-ar71xx/src/board/zyxel/nbg460n/Makefile

@@ -1,46 +0,0 @@
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-
-COBJS-y += $(BOARD).o
-SOBJS-y += lowlevel_init.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

package/boot/uboot-ar71xx/src/board/zyxel/nbg460n/config.mk

@@ -1 +0,0 @@
-TEXT_BASE = 0x81E00000

package/boot/uboot-ar71xx/src/board/zyxel/nbg460n/lowlevel_init.S

@@ -1,39 +0,0 @@
-/*
- * (C) Copyright 2010
- * Michael Kurz <michi.kurz@googlemail.com>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-
-
-
-.globl lowlevel_init
-/*
-	All done by Bootbase, nothing to do
-*/
-lowlevel_init:
-    jr ra
-    nop
-

package/boot/uboot-ar71xx/src/board/zyxel/nbg460n/nbg460n.c

@@ -1,96 +0,0 @@
-/*
- * (C) Copyright 2010
- * Michael Kurz <michi.kurz@googlemail.com>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <asm/reboot.h>
-#include <asm/ar71xx.h>
-#include <asm/ar71xx_gpio.h>
-
-#define NBG460N_WAN_LED			19
-
-phys_size_t initdram(int board_type)
-{
-    return (32*1024*1024);
-}
-
-int checkboard(void)
-{
-	// Set pin 19 to 1, to stop WAN LED blinking
-    ar71xx_setpindir(NBG460N_WAN_LED, 1);
-    ar71xx_setpin(NBG460N_WAN_LED, 1);
-
-    printf("U-boot on Zyxel NBG460N\n");
-    return 0;
-}
-
-void _machine_restart(void)
-{
-	for (;;) {
-		writel((RESET_MODULE_FULL_CHIP | RESET_MODULE_DDR),
-			KSEG1ADDR(AR71XX_RESET_BASE + AR91XX_RESET_REG_RESET_MODULE));
-        readl(KSEG1ADDR(AR71XX_RESET_BASE + AR91XX_RESET_REG_RESET_MODULE));
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-    char *phynames[] = {RTL8366_DEVNAME, RTL8366_DEVNAME};
-    u16 phyids[] = {RTL8366_LANPHY_ID, RTL8366_WANPHY_ID};
-    u16 phyfixed[] = {1, 0};
-
-    if (ag71xx_register(bis, phynames, phyids, phyfixed) <= 0)
-        return -1;
-
-	if (rtl8366s_initialize())
-        return -1;
-
-    if (rtl8366_mii_register(bis))
-        return -1;
-		
-    return 0;
-}
-
-int misc_init_r(void) {
-    uint8_t macaddr[6];
-    uint8_t enetaddr[6];
-
-	debug("Testing mac addresses\n");
-	
-    memcpy(macaddr, (uint8_t *) CONFIG_ETHADDR_ADDR, 6);
-
-    if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-        debug("Setting eth0 mac addr to %pM\n", macaddr);
-        eth_setenv_enetaddr("ethaddr", macaddr);
-    }
-
-    if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
-		macaddr[5] += 1;
-        debug("Setting eth1 mac addr to %pM\n", macaddr);
-        eth_setenv_enetaddr("eth1addr", macaddr);
-    }
-
-    return 0;
-}

package/boot/uboot-ar71xx/src/board/zyxel/nbg460n/u-boot.lds

@@ -1,42 +0,0 @@
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = ALIGN(4);
-	.sdata  : { *(.sdata) }
-
-	_gp = ALIGN(16);
-
-	__got_start = .;
-	.got  : { *(.got) }
-	__got_end = .;
-
-	.sdata  : { *(.sdata) }
-
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss  : { *(.sbss) }
-	.bss  : { *(.bss) }
-	uboot_end = .;
-}

package/boot/uboot-ar71xx/src/cpu/mips/ar71xx_serial.c

@@ -1,177 +0,0 @@
-/*
- * (C) Copyright 2010
- * Michael Kurz <michi.kurz@googlemail.com>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/addrspace.h>
-#include <asm/types.h>
-#include <config.h>
-#include <asm/ar71xx.h>
-
-#define		REG_SIZE		4
-
-/* === END OF CONFIG === */
-
-/* register offset */
-#define         OFS_RCV_BUFFER          (0*REG_SIZE)
-#define         OFS_TRANS_HOLD          (0*REG_SIZE)
-#define         OFS_SEND_BUFFER         (0*REG_SIZE)
-#define         OFS_INTR_ENABLE         (1*REG_SIZE)
-#define         OFS_INTR_ID             (2*REG_SIZE)
-#define         OFS_DATA_FORMAT         (3*REG_SIZE)
-#define         OFS_LINE_CONTROL        (3*REG_SIZE)
-#define         OFS_MODEM_CONTROL       (4*REG_SIZE)
-#define         OFS_RS232_OUTPUT        (4*REG_SIZE)
-#define         OFS_LINE_STATUS         (5*REG_SIZE)
-#define         OFS_MODEM_STATUS        (6*REG_SIZE)
-#define         OFS_RS232_INPUT         (6*REG_SIZE)
-#define         OFS_SCRATCH_PAD         (7*REG_SIZE)
-
-#define         OFS_DIVISOR_LSB         (0*REG_SIZE)
-#define         OFS_DIVISOR_MSB         (1*REG_SIZE)
-
-#define         UART16550_READ(y)   readl(KSEG1ADDR(AR71XX_UART_BASE+y))
-#define         UART16550_WRITE(x, z)  writel(z, KSEG1ADDR((AR71XX_UART_BASE+x)))
-
-void 
-ar71xx_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq)
-{
-#ifndef CONFIG_AR91XX
-    u32 pll, pll_div, cpu_div, ahb_div, ddr_div, freq;
-
-    pll = readl(KSEG1ADDR(AR71XX_PLL_REG_CPU_CONFIG + AR71XX_PLL_BASE));
-
-    pll_div = 
-        ((pll & AR71XX_PLL_DIV_MASK) >> AR71XX_PLL_DIV_SHIFT) + 1;
-
-    cpu_div = 
-        ((pll & AR71XX_CPU_DIV_MASK) >> AR71XX_CPU_DIV_SHIFT) + 1;
-
-    ddr_div = 
-        ((pll & AR71XX_DDR_DIV_MASK) >> AR71XX_DDR_DIV_SHIFT) + 1;
-
-    ahb_div = 
-       (((pll & AR71XX_AHB_DIV_MASK) >> AR71XX_AHB_DIV_SHIFT) + 1)*2;
-
-    freq = pll_div * 40000000; 
-
-    if (cpu_freq)
-        *cpu_freq = freq/cpu_div;
-
-    if (ddr_freq)
-        *ddr_freq = freq/ddr_div;
-
-    if (ahb_freq)
-        *ahb_freq = (freq/cpu_div)/ahb_div;
-
-#else
-    u32 pll, pll_div, ahb_div, ddr_div, freq;
-
-    pll = readl(KSEG1ADDR(AR91XX_PLL_REG_CPU_CONFIG + AR71XX_PLL_BASE));
-
-    pll_div = 
-        ((pll & AR91XX_PLL_DIV_MASK) >> AR91XX_PLL_DIV_SHIFT);
-
-    ddr_div = 
-        ((pll & AR91XX_DDR_DIV_MASK) >> AR91XX_DDR_DIV_SHIFT) + 1;
-
-    ahb_div = 
-       (((pll & AR91XX_AHB_DIV_MASK) >> AR91XX_AHB_DIV_SHIFT) + 1)*2;
-
-    freq = pll_div * 5000000; 
-
-    if (cpu_freq)
-        *cpu_freq = freq;
-
-    if (ddr_freq)
-        *ddr_freq = freq/ddr_div;
-
-    if (ahb_freq)
-        *ahb_freq = freq/ahb_div;
-#endif
-}
-
-
-int serial_init(void)
-{
-    u32 div;
-    u32 ahb_freq = 100000000;
-
-    ar71xx_sys_frequency  (0, 0, &ahb_freq);  
-    div  = ahb_freq/(16 * CONFIG_BAUDRATE);  
-
-	// enable uart pins
-#ifndef CONFIG_AR91XX
-    writel(AR71XX_GPIO_FUNC_UART_EN, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_FUNC));
-#else
-	writel(AR91XX_GPIO_FUNC_UART_EN, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_FUNC));
-#endif
-
-    /* set DIAB bit */
-    UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
-
-    /* set divisor */
-    UART16550_WRITE(OFS_DIVISOR_LSB, (div & 0xff));
-    UART16550_WRITE(OFS_DIVISOR_MSB, ((div >> 8) & 0xff));
-
-    /* clear DIAB bit*/ 
-    UART16550_WRITE(OFS_LINE_CONTROL, 0x00);
-
-    /* set data format */
-    UART16550_WRITE(OFS_DATA_FORMAT, 0x3);
-
-    UART16550_WRITE(OFS_INTR_ENABLE, 0);
-
-	return 0;
-}
-
-int serial_tstc (void)
-{
-    return(UART16550_READ(OFS_LINE_STATUS) & 0x1);
-}
-
-int serial_getc(void)
-{
-    while(!serial_tstc());
-
-    return UART16550_READ(OFS_RCV_BUFFER);
-}
-
-
-void serial_putc(const char byte)
-{
-    if (byte == '\n') serial_putc ('\r');
-
-    while (((UART16550_READ(OFS_LINE_STATUS)) & 0x20) == 0x0);
-    UART16550_WRITE(OFS_SEND_BUFFER, byte);
-}
-
-void serial_setbrg (void)
-{
-}
-
-void serial_puts (const char *s)
-{
-	while (*s)
-	{
-		serial_putc (*s++);
-	}
-}

package/boot/uboot-ar71xx/src/drivers/net/ag71xx.c

@@ -1,809 +0,0 @@
-/*
- *  Atheros AR71xx built-in ethernet mac driver
- *
- *  Copyright (C) 2010 Michael Kurz <michi.kurz@googlemail.com>
- *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- *  Based on Atheros' AG7100 driver
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- */
- 
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <miiphy.h>
-
-#include <asm/ar71xx.h>
-
-#include "ag71xx.h"
-
-#ifdef AG71XX_DEBUG
-#define DBG(fmt,args...)		printf(fmt ,##args)
-#else
-#define DBG(fmt,args...)
-#endif
-
-
-static struct ag71xx agtable[] = {
-	{
-		.mac_base = KSEG1ADDR(AR71XX_GE0_BASE),
-		.mii_ctrl = KSEG1ADDR(AR71XX_MII_BASE + MII_REG_MII0_CTRL),
-		.mii_if = CONFIG_AG71XX_MII0_IIF,
-	} , {
-		.mac_base = KSEG1ADDR(AR71XX_GE1_BASE),
-		.mii_ctrl = KSEG1ADDR(AR71XX_MII_BASE + MII_REG_MII1_CTRL),
-		.mii_if = CONFIG_AG71XX_MII1_IIF,
-	}
-};
-
-static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
-{
-	int err;
-	int i;
-	int rsize;
-
-	ring->desc_size = sizeof(struct ag71xx_desc);
-	if (ring->desc_size % (CONFIG_SYS_CACHELINE_SIZE)) {
-		rsize = roundup(ring->desc_size, CONFIG_SYS_CACHELINE_SIZE);
-		DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
-			ring, ring->desc_size,
-			rsize);
-		ring->desc_size = rsize;
-	}
-
-	ring->descs_cpu = (u8 *) malloc((size * ring->desc_size)
-		+ CONFIG_SYS_CACHELINE_SIZE - 1);
-	if (!ring->descs_cpu) {
-		err = -1;
-		goto err;
-	}
-	ring->descs_cpu = (u8 *) UNCACHED_SDRAM((((u32) ring->descs_cpu + 
-		CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1)));
-    ring->descs_dma = (u8 *) virt_to_phys(ring->descs_cpu);
-
-	ring->size = size;
-
-	ring->buf = malloc(size * sizeof(*ring->buf));
-	if (!ring->buf) {
-		err = -1;
-		goto err;
-	}
-    memset(ring->buf, 0, size * sizeof(*ring->buf));
-
-	for (i = 0; i < size; i++) {
-		ring->buf[i].desc =
-			(struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
-		DBG("ag71xx: ring %p, desc %d at %p\n",
-			ring, i, ring->buf[i].desc);
-	}
-
-	flush_cache( (u32) ring->buf, size * sizeof(*ring->buf));
-	
-	return 0;
-
- err:
-	return err;
-}
-
-static void ag71xx_ring_tx_init(struct ag71xx *ag)
-{
-	struct ag71xx_ring *ring = &ag->tx_ring;
-	int i;
-
-	for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
-		ring->buf[i].desc->next = (u32) virt_to_phys((ring->descs_dma +
-			ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE)));
-
-		ring->buf[i].desc->ctrl = DESC_EMPTY;
-		ring->buf[i].skb = NULL;
-	}
-
-	ring->curr = 0;
-}
-
-static void ag71xx_ring_rx_clean(struct ag71xx *ag)
-{
-	struct ag71xx_ring *ring = &ag->rx_ring;
-	int i;
-
-	if (!ring->buf)
-		return;
-
-	for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
-	    ring->buf[i].desc->data = (u32) virt_to_phys(NetRxPackets[i]);
-	    flush_cache((u32) NetRxPackets[i], PKTSIZE_ALIGN);
-        ring->buf[i].desc->ctrl = DESC_EMPTY;
-    }
-
-	ring->curr = 0;
-}
-
-static int ag71xx_ring_rx_init(struct ag71xx *ag)
-{
-	struct ag71xx_ring *ring = &ag->rx_ring;
-	unsigned int i;
-
-	for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
-		ring->buf[i].desc->next = (u32) virt_to_phys((ring->descs_dma +
-			ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE)));
-
-		DBG("ag71xx: RX desc at %p, next is %08x\n",
-			ring->buf[i].desc,
-			ring->buf[i].desc->next);
-	}
-
-	for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
-		ring->buf[i].desc->data = (u32) virt_to_phys(NetRxPackets[i]);
-		ring->buf[i].desc->ctrl = DESC_EMPTY;
-	}
-
-	ring->curr = 0;
-
-	return 0;
-}
-
-static int ag71xx_rings_init(struct ag71xx *ag)
-{
-	int ret;
-
-	ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
-	if (ret)
-		return ret;
-
-	ag71xx_ring_tx_init(ag);
-
-	ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
-	if (ret)
-		return ret;
-
-	ret = ag71xx_ring_rx_init(ag);
-	return ret;
-}
-
-static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
-{
-	uint32_t base = KSEG1ADDR(AR71XX_PLL_BASE);
-	u32 t;
-
-	t = readl(base + cfg_reg);
-	t &= ~(3 << shift);
-	t |=  (2 << shift);
-	writel(t, base + cfg_reg);
-	udelay(100);
-
-	writel(pll_val, base + pll_reg);
-
-	t |= (3 << shift);
-	writel(t, base + cfg_reg);
-	udelay(100);
-
-	t &= ~(3 << shift);
-	writel(t, base + cfg_reg);
-	udelay(100);
-
-	debug("ar71xx: pll_reg %#x: %#x\n", (unsigned int)(base + pll_reg),
-       readl(base + pll_reg));
-}
-
-static void ar91xx_set_pll_ge0(int speed)
-{
-	//u32 val = ar71xx_get_eth_pll(0, speed);
-	u32 pll_val;
-
-	switch (speed) {
-	case SPEED_10:
-		pll_val = 0x00441099;
-		break;
-	case SPEED_100:
-		pll_val = 0x13000a44;
-		break;
-	case SPEED_1000:
-		pll_val = 0x1a000000;
-		break;
-	default:
-		BUG();
-	}
-
-	ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
-			 pll_val, AR91XX_ETH0_PLL_SHIFT);
-}
-
-static void ar91xx_set_pll_ge1(int speed)
-{
-	//u32 val = ar71xx_get_eth_pll(1, speed);
-    u32 pll_val;
-
-	switch (speed) {
-	case SPEED_10:
-		pll_val = 0x00441099;
-		break;
-	case SPEED_100:
-		pll_val = 0x13000a44;
-		break;
-	case SPEED_1000:
-		pll_val = 0x1a000000;
-		break;
-	default:
-		BUG();
-	}
-
-	ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
-			 pll_val, AR91XX_ETH1_PLL_SHIFT);
-}
-
-static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
-{
-	u32 t;
-
-	t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
-	  | (((u32) mac[3]) << 8) | ((u32) mac[2]);
-
-	ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
-
-	t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
-	ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
-}
-
-static void ag71xx_dma_reset(struct ag71xx *ag)
-{
-	u32 val;
-	int i;
-
-	DBG("%s: txdesc reg: 0x%08x rxdesc reg: 0x%08x\n",
-			ag->dev->name,
-			ag71xx_rr(ag, AG71XX_REG_TX_DESC),
-			ag71xx_rr(ag, AG71XX_REG_RX_DESC));
-	
-	/* stop RX and TX */
-	ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
-	ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
-
-	/* clear descriptor addresses */
-	ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
-	ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
-
-	/* clear pending RX/TX interrupts */
-	for (i = 0; i < 256; i++) {
-		ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
-		ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
-	}
-
-	/* clear pending errors */
-	ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
-	ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
-
-	val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
-	if (val)
-		printf("%s: unable to clear DMA Rx status: %08x\n",
-			ag->dev->name, val);
-
-	val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
-
-	/* mask out reserved bits */
-	val &= ~0xff000000;
-
-	if (val)
-		printf("%s: unable to clear DMA Tx status: %08x\n",
-			ag->dev->name, val);
-}
-
-static void ag71xx_halt(struct eth_device *dev)
-{
-    struct ag71xx *ag = (struct ag71xx *) dev->priv;
-
-    /* stop RX engine */
-	ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
-
-	ag71xx_dma_reset(ag);
-}
-
-#define MAX_WAIT        1000
-
-static int ag71xx_send(struct eth_device *dev, volatile void *packet,
-                       int length)
-{
-    struct ag71xx *ag = (struct ag71xx *) dev->priv;
-	struct ag71xx_ring *ring = &ag->tx_ring;
-	struct ag71xx_desc *desc;
-	int i;
-
-	i = ring->curr % AG71XX_TX_RING_SIZE;
-	desc = ring->buf[i].desc;
-
-	if (!ag71xx_desc_empty(desc)) {
-		printf("%s: tx buffer full\n", ag->dev->name);
-		return 1;
-	}
-
-	flush_cache((u32) packet, length);
-    desc->data = (u32) virt_to_phys(packet);
-    desc->ctrl = (length & DESC_PKTLEN_M);
-	
-	DBG("%s: sending %#08x length %#08x\n",
-		ag->dev->name, desc->data, desc->ctrl);
-	
-	ring->curr++;
-	if (ring->curr >= AG71XX_TX_RING_SIZE){
-		ring->curr = 0;
-	}
-	
-	/* enable TX engine */
-	ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
-
-    for (i = 0; i < MAX_WAIT; i++)
-    {
-        if (ag71xx_desc_empty(desc))
-            break;
-        udelay(10);
-    }
-    if (i == MAX_WAIT) {
-        printf("%s: tx timed out!\n", ag->dev->name);
-		return -1;
-	}
-	
-	/* disable TX engine */
-	ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
-	desc->data = 0;
-	desc->ctrl = DESC_EMPTY;
-	
-	return 0;
-}
-
-static int ag71xx_recv(struct eth_device *dev)
-{
-    struct ag71xx *ag = (struct ag71xx *) dev->priv;
-	struct ag71xx_ring *ring = &ag->rx_ring;
-
-    for (;;) {
-		unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
-		struct ag71xx_desc *desc = ring->buf[i].desc;
-		int pktlen;
-		
-		if (ag71xx_desc_empty(desc))
-			break;
-
-		DBG("%s: rx packets, curr=%u\n", dev->name, ring->curr);
-
-        pktlen = ag71xx_desc_pktlen(desc);
-		pktlen -= ETH_FCS_LEN;
-
-
-		NetReceive(NetRxPackets[i] , pktlen);
-		flush_cache( (u32) NetRxPackets[i], PKTSIZE_ALIGN);
-
-        ring->buf[i].desc->ctrl = DESC_EMPTY;
-		ring->curr++;
-		if (ring->curr >= AG71XX_RX_RING_SIZE){
-			ring->curr = 0;
-		}
-
-    }
-
-	if ((ag71xx_rr(ag, AG71XX_REG_RX_CTRL) & RX_CTRL_RXE) == 0) {
-		/* start RX engine */
-		ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
-	}
-	
-	return 0;
-}
-
-#ifdef AG71XX_DEBUG
-static char *ag71xx_speed_str(struct ag71xx *ag)
-{
-	switch (ag->speed) {
-	case SPEED_1000:
-		return "1000";
-	case SPEED_100:
-		return "100";
-	case SPEED_10:
-		return "10";
-	}
-
-	return "?";
-}
-#endif
-
-void ag71xx_link_adjust(struct ag71xx *ag)
-{
-	u32 cfg2;
-	u32 ifctl;
-	u32 fifo5;
-	u32 mii_speed;
-
-	if (!ag->link) {
-		DBG("%s: link down\n", ag->dev->name);
-		return;
-	}
-
-	cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
-	cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
-	cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
-
-	ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
-	ifctl &= ~(MAC_IFCTL_SPEED);
-
-	fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
-	fifo5 &= ~FIFO_CFG5_BM;
-
-	switch (ag->speed) {
-	case SPEED_1000:
-		mii_speed =  MII_CTRL_SPEED_1000;
-		cfg2 |= MAC_CFG2_IF_1000;
-		fifo5 |= FIFO_CFG5_BM;
-		break;
-	case SPEED_100:
-		mii_speed = MII_CTRL_SPEED_100;
-		cfg2 |= MAC_CFG2_IF_10_100;
-		ifctl |= MAC_IFCTL_SPEED;
-		break;
-	case SPEED_10:
-		mii_speed = MII_CTRL_SPEED_10;
-		cfg2 |= MAC_CFG2_IF_10_100;
-		break;
-	default:
-		BUG();
-		return;
-	}
-
-    ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
-
-    if (ag->macNum == 0)
-        ar91xx_set_pll_ge0(ag->speed);
-    else
-        ar91xx_set_pll_ge1(ag->speed);
-
-	ag71xx_mii_ctrl_set_speed(ag, mii_speed);
-
-	ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
-	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
-	ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
-
-    DBG("%s: link up (%sMbps/%s duplex)\n",
-        ag->dev->name,
-        ag71xx_speed_str(ag),
-        (1 == ag->duplex) ? "Full" : "Half");
-
-	DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
-		ag->dev->name,
-		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
-		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
-		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
-
-	DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
-		ag->dev->name,
-		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
-		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
-		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
-
-	DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
-		ag->dev->name,
-		ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
-		ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
-		ag71xx_mii_ctrl_rr(ag));
-}
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-static int ag71xx_getMiiSpeed(struct ag71xx *ag) 
-{
-    uint16_t phyreg, cap;
-
-    if (miiphy_read(ag->phyname, ag->phyid,
-                    PHY_BMSR, &phyreg)) {
-        puts("PHY_BMSR read failed, assuming no link\n");
-        return -1;
-    }
-
-    if ((phyreg & PHY_BMSR_LS) == 0) {
-        return -1;
-    }
-
-    if (miiphy_read(ag->phyname, ag->phyid,
-                PHY_1000BTSR, &phyreg))
-        return -1;
-
-    if (phyreg & PHY_1000BTSR_1000FD) {
-        ag->speed = SPEED_1000;
-        ag->duplex = 1;
-    } else if (phyreg & PHY_1000BTSR_1000HD) {
-        ag->speed = SPEED_1000;
-        ag->duplex = 0;
-    } else {
-        if (miiphy_read(ag->phyname, ag->phyid,
-                PHY_ANAR, &cap))
-            return -1;
-
-        if (miiphy_read(ag->phyname, ag->phyid,
-                PHY_ANLPAR, &phyreg))
-            return -1;
-
-        cap &= phyreg;
-        if (cap & PHY_ANLPAR_TXFD) {
-            ag->speed = SPEED_100;
-            ag->duplex = 1;
-        } else if (cap & PHY_ANLPAR_TX) {
-            ag->speed = SPEED_100;
-            ag->duplex = 0;
-        } else if (cap & PHY_ANLPAR_10FD) {
-            ag->speed = SPEED_10;
-            ag->duplex = 1;
-        } else {
-            ag->speed = SPEED_10;
-            ag->duplex = 0;
-        }
-    }
-	
-	ag->link = 1;
-	
-	return 0;
-}
-#endif
-
-static int ag71xx_hw_start(struct eth_device *dev, bd_t * bd)
-{
-	struct ag71xx *ag = (struct ag71xx *) dev->priv;
-
-	ag71xx_dma_reset(ag);
-
-    ag71xx_ring_rx_clean(ag);
-	ag71xx_ring_tx_init(ag);
-	
-	ag71xx_wr(ag, AG71XX_REG_TX_DESC, 
-				(u32) virt_to_phys(ag->tx_ring.descs_dma));
-	ag71xx_wr(ag, AG71XX_REG_RX_DESC,
-				(u32) virt_to_phys(ag->rx_ring.descs_dma));
-
-	ag71xx_hw_set_macaddr(ag, ag->dev->enetaddr);
-
-    if (ag->phyfixed) {
-        ag->link = 1;
-        ag->duplex = 1;
-        ag->speed = SPEED_1000;
-    } else {
-
-#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
-		if (ag71xx_getMiiSpeed(ag))
-			return -1;
-#else
-		/* only fixed, without mii */
-		return -1;
-#endif
-
-    }
-    ag71xx_link_adjust(ag);
-	
-	DBG("%s: txdesc reg: %#08x rxdesc reg: %#08x\n",
-		ag->dev->name,
-		ag71xx_rr(ag, AG71XX_REG_TX_DESC),
-		ag71xx_rr(ag, AG71XX_REG_RX_DESC));
-	
-	/* start RX engine */
-	ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
-	
-	return 0;
-}
-
-#define FIFO_CFG0_INIT	(FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
-
-#define FIFO_CFG4_INIT	(FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
-			 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
-			 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
-			 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
-			 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
-			 FIFO_CFG4_VT)
-
-#define FIFO_CFG5_INIT	(FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
-			 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
-			 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
-			 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
-			 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
-			 FIFO_CFG5_17 | FIFO_CFG5_SF)
-
-static int ag71xx_hw_init(struct ag71xx *ag)
-{
-    int ret = 0;
-	uint32_t reg;
-	uint32_t mask, mii_type;
-
-    if (ag->macNum == 0) {
-        mask = (RESET_MODULE_GE0_MAC | RESET_MODULE_GE0_PHY);
-        mii_type = 0x13;
-    } else {
-        mask = (RESET_MODULE_GE1_MAC | RESET_MODULE_GE1_PHY);
-        mii_type = 0x11;
-    }
-
-    // mac soft reset
-    ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
-    udelay(20);
-	
-	// device stop
-	reg = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE);
-	ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, reg | mask);
-	udelay(100 * 1000);
-	
-    // device start
-    reg = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE);
-    ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask);
-    udelay(100 * 1000);
-
-    /* setup MAC configuration registers */
-    ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, (MAC_CFG1_RXE | MAC_CFG1_TXE));
-
-    ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
-          MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
-
-    /* setup FIFO configuration register 0 */
-    ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
-
-    /* setup MII interface type */
-    ag71xx_mii_ctrl_set_if(ag, ag->mii_if);
-
-    /* setup mdio clock divisor */
-    ag71xx_wr(ag, AG71XX_REG_MII_CFG, MII_CFG_CLK_DIV_20);
-	
-	/* setup FIFO configuration registers */
-	ag71xx_sb(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
-    ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
-    ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
-    ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
-
-    ag71xx_dma_reset(ag);
-
-    ret = ag71xx_rings_init(ag);
-    if (ret)
-        return -1;
-
-	ag71xx_wr(ag, AG71XX_REG_TX_DESC, 
-				(u32) virt_to_phys(ag->tx_ring.descs_dma));
-	ag71xx_wr(ag, AG71XX_REG_RX_DESC,
-				(u32) virt_to_phys(ag->rx_ring.descs_dma));
-		
-	ag71xx_hw_set_macaddr(ag, ag->dev->enetaddr);
-	
-    return 0;
-}
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-#define AG71XX_MDIO_RETRY	1000
-#define AG71XX_MDIO_DELAY	5
-
-static inline struct ag71xx *ag71xx_name2mac(char *devname)
-{
-    if (strcmp(devname, agtable[0].dev->name) == 0)
-        return &agtable[0];
-    else if (strcmp(devname, agtable[1].dev->name) == 0)
-        return &agtable[1];
-    else
-        return NULL;
-}
-
-static inline void ag71xx_mdio_wr(struct ag71xx *ag, unsigned reg,
-				  u32 value)
-{
-	uint32_t r;
-
-	r = ag->mac_base + reg;
-	writel(value, r);
-
-	/* flush write */
-	(void) readl(r);
-}
-
-static inline u32 ag71xx_mdio_rr(struct ag71xx *ag, unsigned reg)
-{
-	return readl(ag->mac_base + reg);
-}
-
-static int ag71xx_mdio_read(char *devname, unsigned char addr,
-                            unsigned char reg, unsigned short *val)
-{
-	struct ag71xx *ag = ag71xx_name2mac(devname);
-	uint16_t regData;
-	int i;
-
-	ag71xx_mdio_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
-	ag71xx_mdio_wr(ag, AG71XX_REG_MII_ADDR,
-			((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
-	ag71xx_mdio_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ);
-
-	i = AG71XX_MDIO_RETRY;
-	while (ag71xx_mdio_rr(ag, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
-		if (i-- == 0) {
-			printf("%s: mii_read timed out\n",
-				ag->dev->name);
-			return -1;
-		}
-		udelay(AG71XX_MDIO_DELAY);
-	}
-
-	regData = (uint16_t) ag71xx_mdio_rr(ag, AG71XX_REG_MII_STATUS) & 0xffff;
-	ag71xx_mdio_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
-
-	DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, regData);
-
-    if (val)
-        *val = regData;
-
-	return 0;
-}
-
-static int ag71xx_mdio_write(char *devname, unsigned char addr,
-                            unsigned char reg, unsigned short val)
-{
-	struct ag71xx *ag = ag71xx_name2mac(devname);
-	int i;
-
-    if (ag == NULL)
-        return 1;
-
-	DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val);
-
-	ag71xx_mdio_wr(ag, AG71XX_REG_MII_ADDR,
-			((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
-	ag71xx_mdio_wr(ag, AG71XX_REG_MII_CTRL, val);
-
-	i = AG71XX_MDIO_RETRY;
-	while (ag71xx_mdio_rr(ag, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
-		if (i-- == 0) {
-			printf("%s: mii_write timed out\n",
-				ag->dev->name);
-			break;
-		}
-		udelay(AG71XX_MDIO_DELAY);
-	}
-
-	return 0;
-}
-#endif
-
-int ag71xx_register(bd_t * bis, char *phyname[], uint16_t phyid[], uint16_t phyfixed[])
-{
-    int i, num = 0;
-    u8 used_ports[MAX_AG71XX_DEVS] = CONFIG_AG71XX_PORTS;
-
-	for (i = 0; i < MAX_AG71XX_DEVS; i++) {
-		/*skip if port is configured not to use */
-		if (used_ports[i] == 0)
-			continue;
-
-		agtable[i].dev = malloc(sizeof(struct eth_device));
-		if (agtable[i].dev == NULL) {
-			puts("malloc failed\n");
-			return 0;
-        }
-		memset(agtable[i].dev, 0, sizeof(struct eth_device));
-		sprintf(agtable[i].dev->name, "eth%d", i);
-
-		agtable[i].dev->iobase = 0;
-		agtable[i].dev->init = ag71xx_hw_start;
-		agtable[i].dev->halt = ag71xx_halt;
-		agtable[i].dev->send = ag71xx_send;
-		agtable[i].dev->recv = ag71xx_recv;
-		agtable[i].dev->priv = (void *) (&agtable[i]);
-		agtable[i].macNum = i;
-		eth_register(agtable[i].dev);
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-
-        if ((phyname == NULL) || (phyid == NULL) || (phyfixed == NULL))
-            return -1;
-
-        agtable[i].phyname = strdup(phyname[i]);
-        agtable[i].phyid = phyid[i];
-        agtable[i].phyfixed = phyfixed[i];
-
-        miiphy_register(agtable[i].dev->name, ag71xx_mdio_read,
-			ag71xx_mdio_write);
-#endif
-
-		if (ag71xx_hw_init(&agtable[i]))
-			continue;
-
-        num++;
-	}
-
-    return num;
-}

package/boot/uboot-ar71xx/src/drivers/net/ag71xx.h

@@ -1,374 +0,0 @@
-/*
- *  Atheros AR71xx built-in ethernet mac driver
- *
- *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- *  Based on Atheros' AG7100 driver
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- */
-
-#ifndef __AG71XX_H
-#define __AG71XX_H
-
-#include <linux/types.h>
-#include <linux/bitops.h>
-
-#include <asm/ar71xx.h>
-
-// controller has 2 ports
-#define MAX_AG71XX_DEVS 2
-
-#define ETH_FCS_LEN	4
-
-#define SPEED_10        10
-#define SPEED_100       100
-#define SPEED_1000      1000
-
-
-#define AG71XX_INT_ERR	(AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
-#define AG71XX_INT_TX	(AG71XX_INT_TX_PS)
-#define AG71XX_INT_RX	(AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
-
-#define AG71XX_INT_POLL	(AG71XX_INT_RX | AG71XX_INT_TX)
-#define AG71XX_INT_INIT	(AG71XX_INT_ERR | AG71XX_INT_POLL)
-
-#define AG71XX_TX_FIFO_LEN	2048
-#define AG71XX_TX_MTU_LEN	1536
-#define AG71XX_RX_PKT_RESERVE	64
-#define AG71XX_RX_PKT_SIZE	\
-	(AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
-
-#ifndef CONFIG_SYS_RX_ETH_BUFFER
-#define AG71XX_TX_RING_SIZE	4
-#define AG71XX_RX_RING_SIZE	4
-#else
-#define AG71XX_TX_RING_SIZE	CONFIG_SYS_RX_ETH_BUFFER
-#define AG71XX_RX_RING_SIZE	CONFIG_SYS_RX_ETH_BUFFER
-#endif
-
-#define AG71XX_TX_THRES_STOP	(AG71XX_TX_RING_SIZE - 4)
-#define AG71XX_TX_THRES_WAKEUP	\
-		(AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
-
-
-
-
-struct ag71xx_desc {
-	u32	data;
-	u32	ctrl;
-#define DESC_EMPTY	BIT(31)
-#define DESC_MORE	BIT(24)
-#define DESC_PKTLEN_M	0xfff
-	u32	next;
-	u32	pad;
-} __attribute__((aligned(4)));
-
-struct ag71xx_buf {
-	struct sk_buff		*skb;
-	struct ag71xx_desc 	*desc;
-	dma_addr_t		dma_addr;
-	u32			pad;
-};
-
-struct ag71xx_ring {
-	struct ag71xx_buf	*buf;
-	u8			*descs_cpu;
-	u8		    *descs_dma;
-	unsigned int		desc_size;
-	unsigned int		curr;
-	unsigned int		size;
-};
-
-struct ag71xx {
-	uint32_t		    mac_base;
-	uint32_t		    mii_ctrl;
-
-	struct eth_device	*dev;
-
-	struct ag71xx_ring	rx_ring;
-	struct ag71xx_ring	tx_ring;
-
-    char               *phyname;
-    u16                 phyid;
-    u16                 phyfixed;
-	uint32_t	    	link;
-	uint32_t	    	speed;
-	int32_t			    duplex;
-    uint32_t            macNum;
-    uint32_t            mii_if;
-};
-
-void ag71xx_link_adjust(struct ag71xx *ag);
-
-int ag71xx_phy_connect(struct ag71xx *ag);
-void ag71xx_phy_disconnect(struct ag71xx *ag);
-void ag71xx_phy_start(struct ag71xx *ag);
-void ag71xx_phy_stop(struct ag71xx *ag);
-
-static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
-{
-	return ((desc->ctrl & DESC_EMPTY) != 0);
-}
-
-static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
-{
-	return (desc->ctrl & DESC_PKTLEN_M);
-}
-
-/* Register offsets */
-#define AG71XX_REG_MAC_CFG1	0x0000
-#define AG71XX_REG_MAC_CFG2	0x0004
-#define AG71XX_REG_MAC_IPG	0x0008
-#define AG71XX_REG_MAC_HDX	0x000c
-#define AG71XX_REG_MAC_MFL	0x0010
-#define AG71XX_REG_MII_CFG	0x0020
-#define AG71XX_REG_MII_CMD	0x0024
-#define AG71XX_REG_MII_ADDR	0x0028
-#define AG71XX_REG_MII_CTRL	0x002c
-#define AG71XX_REG_MII_STATUS	0x0030
-#define AG71XX_REG_MII_IND	0x0034
-#define AG71XX_REG_MAC_IFCTL	0x0038
-#define AG71XX_REG_MAC_ADDR1	0x0040
-#define AG71XX_REG_MAC_ADDR2	0x0044
-#define AG71XX_REG_FIFO_CFG0	0x0048
-#define AG71XX_REG_FIFO_CFG1	0x004c
-#define AG71XX_REG_FIFO_CFG2	0x0050
-#define AG71XX_REG_FIFO_CFG3	0x0054
-#define AG71XX_REG_FIFO_CFG4	0x0058
-#define AG71XX_REG_FIFO_CFG5	0x005c
-#define AG71XX_REG_FIFO_RAM0	0x0060
-#define AG71XX_REG_FIFO_RAM1	0x0064
-#define AG71XX_REG_FIFO_RAM2	0x0068
-#define AG71XX_REG_FIFO_RAM3	0x006c
-#define AG71XX_REG_FIFO_RAM4	0x0070
-#define AG71XX_REG_FIFO_RAM5	0x0074
-#define AG71XX_REG_FIFO_RAM6	0x0078
-#define AG71XX_REG_FIFO_RAM7	0x007c
-
-#define AG71XX_REG_TX_CTRL	0x0180
-#define AG71XX_REG_TX_DESC	0x0184
-#define AG71XX_REG_TX_STATUS	0x0188
-#define AG71XX_REG_RX_CTRL	0x018c
-#define AG71XX_REG_RX_DESC	0x0190
-#define AG71XX_REG_RX_STATUS	0x0194
-#define AG71XX_REG_INT_ENABLE	0x0198
-#define AG71XX_REG_INT_STATUS	0x019c
-
-#define MAC_CFG1_TXE		BIT(0)	/* Tx Enable */
-#define MAC_CFG1_STX		BIT(1)	/* Synchronize Tx Enable */
-#define MAC_CFG1_RXE		BIT(2)	/* Rx Enable */
-#define MAC_CFG1_SRX		BIT(3)	/* Synchronize Rx Enable */
-#define MAC_CFG1_TFC		BIT(4)	/* Tx Flow Control Enable */
-#define MAC_CFG1_RFC		BIT(5)	/* Rx Flow Control Enable */
-#define MAC_CFG1_LB		BIT(8)	/* Loopback mode */
-#define MAC_CFG1_SR		BIT(31)	/* Soft Reset */
-
-#define MAC_CFG2_FDX		BIT(0)
-#define MAC_CFG2_CRC_EN		BIT(1)
-#define MAC_CFG2_PAD_CRC_EN	BIT(2)
-#define MAC_CFG2_LEN_CHECK	BIT(4)
-#define MAC_CFG2_HUGE_FRAME_EN	BIT(5)
-#define MAC_CFG2_IF_1000	BIT(9)
-#define MAC_CFG2_IF_10_100	BIT(8)
-
-#define FIFO_CFG0_WTM		BIT(0)	/* Watermark Module */
-#define FIFO_CFG0_RXS		BIT(1)	/* Rx System Module */
-#define FIFO_CFG0_RXF		BIT(2)	/* Rx Fabric Module */
-#define FIFO_CFG0_TXS		BIT(3)	/* Tx System Module */
-#define FIFO_CFG0_TXF		BIT(4)	/* Tx Fabric Module */
-#define FIFO_CFG0_ALL	(FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
-			| FIFO_CFG0_TXS | FIFO_CFG0_TXF)
-
-#define FIFO_CFG0_ENABLE_SHIFT	8
-
-#define FIFO_CFG4_DE		BIT(0)	/* Drop Event */
-#define FIFO_CFG4_DV		BIT(1)	/* RX_DV Event */
-#define FIFO_CFG4_FC		BIT(2)	/* False Carrier */
-#define FIFO_CFG4_CE		BIT(3)	/* Code Error */
-#define FIFO_CFG4_CR		BIT(4)	/* CRC error */
-#define FIFO_CFG4_LM		BIT(5)	/* Length Mismatch */
-#define FIFO_CFG4_LO		BIT(6)	/* Length out of range */
-#define FIFO_CFG4_OK		BIT(7)	/* Packet is OK */
-#define FIFO_CFG4_MC		BIT(8)	/* Multicast Packet */
-#define FIFO_CFG4_BC		BIT(9)	/* Broadcast Packet */
-#define FIFO_CFG4_DR		BIT(10)	/* Dribble */
-#define FIFO_CFG4_LE		BIT(11)	/* Long Event */
-#define FIFO_CFG4_CF		BIT(12)	/* Control Frame */
-#define FIFO_CFG4_PF		BIT(13)	/* Pause Frame */
-#define FIFO_CFG4_UO		BIT(14)	/* Unsupported Opcode */
-#define FIFO_CFG4_VT		BIT(15)	/* VLAN tag detected */
-#define FIFO_CFG4_FT		BIT(16)	/* Frame Truncated */
-#define FIFO_CFG4_UC		BIT(17)	/* Unicast Packet */
-
-#define FIFO_CFG5_DE		BIT(0)	/* Drop Event */
-#define FIFO_CFG5_DV		BIT(1)	/* RX_DV Event */
-#define FIFO_CFG5_FC		BIT(2)	/* False Carrier */
-#define FIFO_CFG5_CE		BIT(3)	/* Code Error */
-#define FIFO_CFG5_LM		BIT(4)	/* Length Mismatch */
-#define FIFO_CFG5_LO		BIT(5)	/* Length Out of Range */
-#define FIFO_CFG5_OK		BIT(6)	/* Packet is OK */
-#define FIFO_CFG5_MC		BIT(7)	/* Multicast Packet */
-#define FIFO_CFG5_BC		BIT(8)	/* Broadcast Packet */
-#define FIFO_CFG5_DR		BIT(9)	/* Dribble */
-#define FIFO_CFG5_CF		BIT(10)	/* Control Frame */
-#define FIFO_CFG5_PF		BIT(11)	/* Pause Frame */
-#define FIFO_CFG5_UO		BIT(12)	/* Unsupported Opcode */
-#define FIFO_CFG5_VT		BIT(13)	/* VLAN tag detected */
-#define FIFO_CFG5_LE		BIT(14)	/* Long Event */
-#define FIFO_CFG5_FT		BIT(15)	/* Frame Truncated */
-#define FIFO_CFG5_16		BIT(16)	/* unknown */
-#define FIFO_CFG5_17		BIT(17)	/* unknown */
-#define FIFO_CFG5_SF		BIT(18)	/* Short Frame */
-#define FIFO_CFG5_BM		BIT(19)	/* Byte Mode */
-
-#define AG71XX_INT_TX_PS	BIT(0)
-#define AG71XX_INT_TX_UR	BIT(1)
-#define AG71XX_INT_TX_BE	BIT(3)
-#define AG71XX_INT_RX_PR	BIT(4)
-#define AG71XX_INT_RX_OF	BIT(6)
-#define AG71XX_INT_RX_BE	BIT(7)
-
-#define MAC_IFCTL_SPEED		BIT(16)
-
-#define MII_CFG_CLK_DIV_4	0
-#define MII_CFG_CLK_DIV_6	2
-#define MII_CFG_CLK_DIV_8	3
-#define MII_CFG_CLK_DIV_10	4
-#define MII_CFG_CLK_DIV_14	5
-#define MII_CFG_CLK_DIV_20	6
-#define MII_CFG_CLK_DIV_28	7
-#define MII_CFG_RESET		BIT(31)
-
-#define MII_CMD_WRITE		0x0
-#define MII_CMD_READ		0x1
-#define MII_ADDR_SHIFT		8
-#define MII_IND_BUSY		BIT(0)
-#define MII_IND_INVALID		BIT(2)
-
-#define TX_CTRL_TXE		BIT(0)	/* Tx Enable */
-
-#define TX_STATUS_PS		BIT(0)	/* Packet Sent */
-#define TX_STATUS_UR		BIT(1)	/* Tx Underrun */
-#define TX_STATUS_BE		BIT(3)	/* Bus Error */
-
-#define RX_CTRL_RXE		BIT(0)	/* Rx Enable */
-
-#define RX_STATUS_PR		BIT(0)	/* Packet Received */
-#define RX_STATUS_OF		BIT(2)	/* Rx Overflow */
-#define RX_STATUS_BE		BIT(3)	/* Bus Error */
-
-#define MII_CTRL_IF_MASK	3
-#define MII_CTRL_SPEED_SHIFT	4
-#define MII_CTRL_SPEED_MASK	3
-#define MII_CTRL_SPEED_10	0
-#define MII_CTRL_SPEED_100	1
-#define MII_CTRL_SPEED_1000	2
-
-static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
-{
-	__raw_writel(value, ag->mac_base + reg);
-	/* flush write */
-	(void) __raw_readl(ag->mac_base + reg);
-}
-
-static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
-{
-	return __raw_readl(ag->mac_base + reg);
-}
-
-static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
-{
-	uint32_t r;
-
-	r = ag->mac_base + reg;
-	__raw_writel(__raw_readl(r) | mask, r);
-	/* flush write */
-	(void)__raw_readl(r);
-}
-
-static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
-{
-	uint32_t r;
-
-	r = ag->mac_base + reg;
-	__raw_writel(__raw_readl(r) & ~mask, r);
-	/* flush write */
-	(void) __raw_readl(r);
-}
-
-static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
-{
-	ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
-}
-
-static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
-{
-	ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
-}
-
-static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
-{
-	__raw_writel(value, ag->mii_ctrl);
-
-	/* flush write */
-	__raw_readl(ag->mii_ctrl);
-}
-
-static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
-{
-	return __raw_readl(ag->mii_ctrl);
-}
-
-static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
-					  unsigned int mii_if)
-{
-	u32 t;
-
-	t = ag71xx_mii_ctrl_rr(ag);
-	t &= ~(MII_CTRL_IF_MASK);
-	t |= (mii_if & MII_CTRL_IF_MASK);
-	ag71xx_mii_ctrl_wr(ag, t);
-}
-
-static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
-					     unsigned int speed)
-{
-	u32 t;
-
-	t = ag71xx_mii_ctrl_rr(ag);
-	t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
-	t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
-	ag71xx_mii_ctrl_wr(ag, t);
-}
-
-#ifdef CONFIG_AG71XX_AR8216_SUPPORT
-void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
-int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
-				int pktlen);
-static inline int ag71xx_has_ar8216(struct ag71xx *ag)
-{
-	return ag71xx_get_pdata(ag)->has_ar8216;
-}
-#else
-static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
-					   struct sk_buff *skb)
-{
-}
-
-static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
-					      struct sk_buff *skb,
-					      int pktlen)
-{
-	return 0;
-}
-static inline int ag71xx_has_ar8216(struct ag71xx *ag)
-{
-	return 0;
-}
-#endif
-
-#endif /* _AG71XX_H */

package/boot/uboot-ar71xx/src/drivers/net/phy/rtl8366.h

@@ -1,188 +0,0 @@
-/*
- * (C) Copyright 2010
- * Michael Kurz <michi.kurz@googlemail.com>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef RTL8366_MII_H
-#define RTL8366_MII_H
-
-#define	MII_CONTROL_REG		    0
-#define	MII_STATUS_REG	    	1
-#define	MII_PHY_ID0		        2
-#define	MII_PHY_ID1		        3
-#define	MII_LOCAL_CAP	    	4
-#define	MII_REMOTE_CAP		    5
-#define	MII_EXT_AUTONEG		    6
-#define	MII_LOCAL_NEXT_PAGE	    7
-#define	MII_REMOTE_NEXT_PAGE	8
-#define	MII_GIGA_CONTROL	    9
-#define	MII_GIGA_STATUS		    10
-#define	MII_EXT_STATUS_REG	    15
-
-/* Control register */
-#define	MII_CONTROL_1000MBPS	6
-#define	MII_CONTROL_COLL_TEST	7
-#define	MII_CONTROL_FULLDUPLEX	8
-#define	MII_CONTROL_RENEG	    9
-#define	MII_CONTROL_ISOLATE	    10
-#define	MII_CONTROL_POWERDOWN	11
-#define	MII_CONTROL_AUTONEG	    12
-#define	MII_CONTROL_100MBPS	    13
-#define	MII_CONTROL_LOOPBACK	14
-#define	MII_CONTROL_RESET	    15
-
-/* Status/Extended status register */
-/* Basic status */
-#define	MII_STATUS_CAPABILITY	0
-#define	MII_STATUS_JABBER	    1
-#define	MII_STATUS_LINK_UP	    2
-#define	MII_STATUS_AUTONEG_ABLE	3
-#define	MII_STATUS_REMOTE_FAULT	4
-#define	MII_STATUS_AUTONEG_DONE	5
-#define	MII_STATUS_NO_PREAMBLE	6
-#define	MII_STATUS_RESERVED	    7
-#define	MII_STATUS_EXTENDED	    8
-#define	MII_STATUS_100_T2_HALF	9
-#define	MII_STATUS_100_T2_FULL	10
-#define	MII_STATUS_10_TX_HALF	11
-#define	MII_STATUS_10_TX_FULL	12
-#define	MII_STATUS_100_TX_HALF	13
-#define	MII_STATUS_100_TX_FULL	14
-#define	MII_STATUS_100_T4	    15
-
-#define	MII_GIGA_CONTROL_HALF	8
-#define	MII_GIGA_CONTROL_FULL	9
-#define	MII_GIGA_STATUS_HALF	10
-#define	MII_GIGA_STATUS_FULL	11
-
-/* Extended status */
-#define	MII_STATUS_1000_T_HALF	12
-#define	MII_STATUS_1000_T_FULL	13
-#define	MII_STATUS_1000_X_HALF	14
-#define	MII_STATUS_1000_X_FULL	15
-
-/* Local/Remmote capability register */
-#define	MII_CAP_10BASE_TX	    5
-#define	MII_CAP_10BASE_TX_FULL	6
-#define	MII_CAP_100BASE_TX	    7
-#define	MII_CAP_100BASE_TX_FULL	8
-#define	MII_CAP_100BASE_T4	    9
-#define	MII_CAP_SYMM_PAUSE	    10
-#define	MII_CAP_ASYMM_PAUSE	    11
-#define	MII_CAP_RESERVED	    12
-#define	MII_CAP_REMOTE_FAULT	13
-#define	MII_CAP_ACKNOWLEDGE	    14
-#define	MII_CAP_NEXT_PAGE	    15
-#define	MII_CAP_IEEE_802_3	    0x0001
-
-#define	MII_LINK_MODE_MASK	    0x1f
-
-#define REALTEK_RTL8366_CHIP_ID0    0x001C
-#define REALTEK_RTL8366_CHIP_ID1    0xC940
-#define REALTEK_RTL8366_CHIP_ID1_MP 0xC960
-
-#define REALTEK_MIN_PORT_ID     0
-#define REALTEK_MAX_PORT_ID     5
-#define REALTEK_MIN_PHY_ID      REALTEK_MIN_PORT_ID
-#define REALTEK_MAX_PHY_ID      4
-#define REALTEK_CPU_PORT_ID     REALTEK_MAX_PORT_ID
-#define REALTEK_PHY_PORT_MASK   ((1<<(REALTEK_MAX_PHY_ID+1)) - (1<<REALTEK_MIN_PHY_ID))
-#define REALTEK_CPU_PORT_MASK   (1<<REALTEK_CPU_PORT_ID)
-#define REALTEK_ALL_PORT_MASK   (REALTEK_PHY_PORT_MASK | REALTEK_CPU_PORT_MASK)
-
-/* port ability */
-#define RTL8366S_PORT_ABILITY_BASE			0x0011
-
-/* port vlan control register */
-#define RTL8366S_PORT_VLAN_CTRL_BASE			0x0058
-
-/* port linking status */
-#define RTL8366S_PORT_LINK_STATUS_BASE			0x0060
-#define RTL8366S_PORT_STATUS_SPEED_BIT			0
-#define RTL8366S_PORT_STATUS_SPEED_MSK			0x0003
-#define RTL8366S_PORT_STATUS_DUPLEX_BIT			2
-#define RTL8366S_PORT_STATUS_DUPLEX_MSK			0x0004
-#define RTL8366S_PORT_STATUS_LINK_BIT			4
-#define RTL8366S_PORT_STATUS_LINK_MSK			0x0010
-#define RTL8366S_PORT_STATUS_TXPAUSE_BIT		5
-#define RTL8366S_PORT_STATUS_TXPAUSE_MSK		0x0020
-#define RTL8366S_PORT_STATUS_RXPAUSE_BIT		6
-#define RTL8366S_PORT_STATUS_RXPAUSE_MSK		0x0040
-#define RTL8366S_PORT_STATUS_AN_BIT			7
-#define RTL8366S_PORT_STATUS_AN_MSK			0x0080
-
-/* internal control */
-#define RTL8366S_RESET_CONTROL_REG			0x0100
-#define RTL8366S_RESET_QUEUE_BIT			2
-
-#define RTL8366S_CHIP_ID_REG				0x0105
-
-/* MAC control */
-#define RTL8366S_MAC_FORCE_CTRL0_REG			0x0F04
-#define RTL8366S_MAC_FORCE_CTRL1_REG			0x0F05
-
-
-/* PHY registers control */
-#define RTL8366S_PHY_ACCESS_CTRL_REG			0x8028
-#define RTL8366S_PHY_ACCESS_DATA_REG			0x8029
-
-#define RTL8366S_PHY_CTRL_READ				1
-#define RTL8366S_PHY_CTRL_WRITE				0
-
-#define RTL8366S_PHY_REG_MASK				0x1F
-#define RTL8366S_PHY_PAGE_OFFSET			5
-#define RTL8366S_PHY_PAGE_MASK				(0x7<<5)
-#define RTL8366S_PHY_NO_OFFSET				9
-#define RTL8366S_PHY_NO_MASK				(0x1F<<9)
-
-#define RTL8366S_PHY_NO_MAX				4
-#define RTL8366S_PHY_PAGE_MAX				7
-#define RTL8366S_PHY_ADDR_MAX				31
-
-/* cpu port control reg */
-#define RTL8366S_CPU_CTRL_REG				0x004F
-#define RTL8366S_CPU_DRP_BIT				14
-#define RTL8366S_CPU_DRP_MSK				0x4000
-#define RTL8366S_CPU_INSTAG_BIT				15
-#define RTL8366S_CPU_INSTAG_MSK				0x8000
-
-/* LED registers*/
-#define RTL8366S_LED_BLINK_REG				0x420
-#define RTL8366S_LED_BLINKRATE_BIT			0
-#define RTL8366S_LED_BLINKRATE_MSK			0x0007
-#define RTL8366S_LED_INDICATED_CONF_REG			0x421
-#define RTL8366S_LED_0_1_FORCE_REG			0x422
-#define RTL8366S_LED_2_3_FORCE_REG			0x423
-#define RTL8366S_LEDCONF_LEDFORCE			0x1F
-#define RTL8366S_LED_GROUP_MAX				4
-
-#define RTL8366S_GREEN_FEATURE_REG			0x000A
-#define RTL8366S_GREEN_FEATURE_TX_BIT			3
-#define RTL8366S_GREEN_FEATURE_TX_MSK			0x0008
-#define RTL8366S_GREEN_FEATURE_RX_BIT			4
-#define RTL8366S_GREEN_FEATURE_RX_MSK			0x0010
-
-#define	RTL8366S_MODEL_ID_REG	0x5C
-#define	RTL8366S_REV_ID_REG	0x5D
-#define	RTL8366S_MODEL_8366SR	0x6027
-#define	RTL8366S_MODEL_8366RB	0x5937
-
-#endif

package/boot/uboot-ar71xx/src/drivers/net/phy/rtl8366_mii.c

@@ -1,786 +0,0 @@
-/*
- * (C) Copyright 2010
- * Michael Kurz <michi.kurz@googlemail.com>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include MII_GPIOINCLUDE
-
-#include "rtl8366.h"
-
-#ifdef DEBUG_RTL8366
-	#define DBG(fmt,args...)	printf (fmt ,##args)
-#else
-	#define DBG(fmt,args...)
-#endif
-
-
-//-------------------------------------------------------------------
-// Soft SMI functions
-//-------------------------------------------------------------------
-
-#define DELAY 2
-
-static void smi_init(void)
-{
-    MII_SDAINPUT;
-    MII_SCKINPUT;
-
-	MII_SETSDA(1);
-	MII_SETSCK(1);
-
-    udelay(20);
-}
-
-static void smi_start(void)
-{
-/*
- * rtl8366 chip needs a extra clock with
- * SDA high before start condition
- */
-
-    /* set gpio pins output */
-    MII_SDAOUTPUT;
-    MII_SCKOUTPUT;
-    udelay(DELAY);
-
-    /* set initial state: SCK:0, SDA:1 */
-    MII_SETSCK(0);
-    MII_SETSDA(1);
-    udelay(DELAY);
-
-    /* toggle clock */
-    MII_SETSCK(1);
-    udelay(DELAY);
-    MII_SETSCK(0);
-    udelay(DELAY);
-
-    /* start condition */
-    MII_SETSCK(1);
-    udelay(DELAY);
-    MII_SETSDA(0);
-    udelay(DELAY);
-    MII_SETSCK(0);
-    udelay(DELAY);
-    MII_SETSDA(1);
-}
-
-static void smi_stop(void)
-{
-/*
- * rtl8366 chip needs a extra clock with
- * SDA high after stop condition
- */
-
-    /* stop condition */
-	udelay(DELAY);
-    MII_SETSDA(0);
-    MII_SETSCK(1);
-    udelay(DELAY);
-    MII_SETSDA(1);
-    udelay(DELAY);
-    MII_SETSCK(1);
-    udelay(DELAY);
-    MII_SETSCK(0);
-    udelay(DELAY);
-
-    /* toggle clock */
-    MII_SETSCK(1);
-    udelay(DELAY);
-    MII_SETSCK(0);
-    udelay(DELAY);
-    MII_SETSCK(1);
-
-    /* set gpio pins input */
-    MII_SDAINPUT;
-    MII_SCKINPUT;
-}
-
-static void smi_writeBits(uint32_t data, uint8_t length)
-{
-    uint8_t test;
-
-    for( ; length > 0; length--) {
-        udelay(DELAY);
-
-        /* output data */
-        test = (((data & (1 << (length - 1))) != 0) ? 1 : 0);
-        MII_SETSDA(test);
-        udelay(DELAY);
-
-        /* toogle clock */
-        MII_SETSCK(1);
-        udelay(DELAY);
-        MII_SETSCK(0);
-    }
-}
-
-static uint32_t smi_readBits(uint8_t length)
-{
-    uint32_t ret;
-
-    MII_SDAINPUT;
-
-    for(ret = 0 ; length > 0; length--) {
-        udelay(DELAY);
-
-        ret <<= 1;
-
-        /* toogle clock */
-        MII_SETSCK(1);
-        udelay(DELAY);
-        ret |= MII_GETSDA;
-        MII_SETSCK(0);
-    }
-
-    MII_SDAOUTPUT;
-
-    return ret;
-}
-
-static int smi_waitAck(void)
-{
-    uint32_t retry = 0;
-
-	while (smi_readBits(1)) {
-		if (retry++ == 5)
-			return -1;
-	}
-
-	return 0;
-
-}
-
-static int smi_read(uint32_t reg, uint32_t *data)
-{
-    uint32_t rawData;
-
-    /* send start condition */
-    smi_start();
-    /* send CTRL1 code: 0b1010*/
-    smi_writeBits(0x0a, 4);
-    /* send CTRL2 code: 0b100 */
-    smi_writeBits(0x04, 3);
-    /* send READ command */
-    smi_writeBits(0x01, 1);
-
-    /* wait for ACK */
-    if (smi_waitAck())
-        return -1;
-
-    /* send address low */
-    smi_writeBits(reg & 0xFF, 8);
-    /* wait for ACK */
-    if (smi_waitAck())
-        return -1;
-    /* send address high */
-    smi_writeBits((reg & 0xFF00) >> 8, 8);
-    /* wait for ACK */
-    if (smi_waitAck())
-        return -1;
-
-    /* read data low */
-    rawData = (smi_readBits(8) & 0xFF);
-    /* send ACK */
-    smi_writeBits(0, 1);
-    /* read data high */
-    rawData |= (smi_readBits(8) & 0xFF) << 8;
-    /* send NACK */
-    smi_writeBits(1, 1);
-
-    /* send stop condition */
-    smi_stop();
-
-    if (data)
-        *data = rawData;
-
-    return 0;
-}
-
-static int smi_write(uint32_t reg, uint32_t data)
-{
-    /* send start condition */
-    smi_start();
-    /* send CTRL1 code: 0b1010*/
-    smi_writeBits(0x0a, 4);
-    /* send CTRL2 code: 0b100 */
-    smi_writeBits(0x04, 3);
-    /* send WRITE command */
-    smi_writeBits(0x00, 1);
-
-    /* wait for ACK */
-    if (smi_waitAck())
-        return -1;
-
-    /* send address low */
-    smi_writeBits(reg & 0xFF, 8);
-    /* wait for ACK */
-    if (smi_waitAck())
-        return -1;
-    /* send address high */
-    smi_writeBits((reg & 0xFF00) >> 8, 8);
-    /* wait for ACK */
-    if (smi_waitAck())
-        return -1;
-
-    /* send data low */
-    smi_writeBits(data & 0xFF, 8);
-    /* wait for ACK */
-    if (smi_waitAck())
-        return -1;
-    /* send data high */
-    smi_writeBits((data & 0xFF00) >> 8, 8);
-    /* wait for ACK */
-    if (smi_waitAck())
-        return -1;
-
-    /* send stop condition */
-    smi_stop();
-
-    return 0;
-}
-
-
-//-------------------------------------------------------------------
-// Switch register read / write functions
-//-------------------------------------------------------------------
-static int rtl8366_readRegister(uint32_t reg, uint16_t *data)
-{
-    uint32_t regData;
-
-    DBG("rtl8366: read register=%#04x, data=", reg);
-
-    if (smi_read(reg, &regData)) {
-        printf("\nrtl8366 smi read failed!\n");
-        return -1;
-    }
-
-    if (data)
-        *data = regData;
-
-    DBG("%#04x\n", regData);
-
-    return 0;
-}
-
-static int rtl8366_writeRegister(uint32_t reg, uint16_t data)
-{
-    DBG("rtl8366: write register=%#04x, data=%#04x\n", reg, data);
-
-    if (smi_write(reg, data)) {
-        printf("rtl8366 smi write failed!\n");
-        return -1;
-    }
-
-    return 0;
-}
-
-static int rtl8366_setRegisterBit(uint32_t reg, uint32_t bitNum, uint32_t value)
-{
-    uint16_t regData;
-
-    if (bitNum >= 16)
-        return -1;
-
-    if (rtl8366_readRegister(reg, &regData))
-        return -1;
-
-    if (value)
-        regData |= (1 << bitNum);
-    else
-        regData &= ~(1 << bitNum);
-
-    if (rtl8366_writeRegister(reg, regData))
-        return -1;
-
-    return 0;
-}
-
-//-------------------------------------------------------------------
-// MII PHY read / write functions
-//-------------------------------------------------------------------
-static int rtl8366_getPhyReg(uint32_t phyNum, uint32_t reg, uint16_t *data)
-{
-    uint16_t phyAddr, regData;
-
-    if (phyNum > RTL8366S_PHY_NO_MAX) {
-		printf("rtl8366s: invalid phy number!\n");
-		return -1;
-	}
-
-    if (phyNum > RTL8366S_PHY_ADDR_MAX) {
-		printf("rtl8366s: invalid phy register number!\n");
-		return -1;
-	}
-
-	if (rtl8366_writeRegister(RTL8366S_PHY_ACCESS_CTRL_REG,
-                           RTL8366S_PHY_CTRL_READ))
-        return -1;
-
-    phyAddr = 0x8000 | (1 << (phyNum + RTL8366S_PHY_NO_OFFSET))
-                     | (reg & RTL8366S_PHY_REG_MASK);
-    if (rtl8366_writeRegister(phyAddr, 0))
-        return -1;
-
-    if (rtl8366_readRegister(RTL8366S_PHY_ACCESS_DATA_REG, &regData))
-        return -1;
-
-    if (data)
-        *data = regData;
-
-    return 0;
-}
-
-static int rtl8366_setPhyReg(uint32_t phyNum, uint32_t reg, uint16_t data)
-{
-    uint16_t phyAddr;
-
-    if (phyNum > RTL8366S_PHY_NO_MAX) {
-		printf("rtl8366s: invalid phy number!\n");
-		return -1;
-	}
-
-    if (phyNum > RTL8366S_PHY_ADDR_MAX) {
-		printf("rtl8366s: invalid phy register number!\n");
-		return -1;
-	}
-
-	if (rtl8366_writeRegister(RTL8366S_PHY_ACCESS_CTRL_REG,
-                           RTL8366S_PHY_CTRL_WRITE))
-        return -1;
-
-    phyAddr = 0x8000 | (1 << (phyNum + RTL8366S_PHY_NO_OFFSET))
-                     | (reg & RTL8366S_PHY_REG_MASK);
-    if (rtl8366_writeRegister(phyAddr, data))
-        return -1;
-
-    return 0;
-}
-
-static int rtl8366_miiread(char *devname, uchar phy_adr, uchar reg, ushort *data)
-{
-    uint16_t regData;
-
-    DBG("rtl8366_miiread: devname=%s, addr=%#02x, reg=%#02x\n",
-          devname, phy_adr, reg);
-
-    if (strcmp(devname, RTL8366_DEVNAME) != 0)
-        return -1;
-
-    if (rtl8366_getPhyReg(phy_adr, reg, &regData)) {
-        printf("rtl8366_miiread: write failed!\n");
-        return -1;
-    }
-
-    if (data)
-        *data = regData;
-
-    return 0;
-}
-
-static int rtl8366_miiwrite(char *devname, uchar phy_adr, uchar reg, ushort data)
-{
-    DBG("rtl8366_miiwrite: devname=%s, addr=%#02x, reg=%#02x, data=%#04x\n",
-          devname, phy_adr, reg, data);
-
-    if (strcmp(devname, RTL8366_DEVNAME) != 0)
-        return -1;
-
-    if (rtl8366_setPhyReg(phy_adr, reg, data)) {
-        printf("rtl8366_miiwrite: write failed!\n");
-        return -1;
-    }
-
-    return 0;
-}
-
-int rtl8366_mii_register(bd_t *bis)
-{
-    miiphy_register(strdup(RTL8366_DEVNAME), rtl8366_miiread,
-			rtl8366_miiwrite);
-
-    return 0;
-}
-
-
-//-------------------------------------------------------------------
-// Switch management functions
-//-------------------------------------------------------------------
-
-int rtl8366s_setGreenFeature(uint32_t tx, uint32_t rx)
-{
-    if (rtl8366_setRegisterBit(RTL8366S_GREEN_FEATURE_REG,
-                               RTL8366S_GREEN_FEATURE_TX_BIT, tx))
-        return -1;
-
-    if (rtl8366_setRegisterBit(RTL8366S_GREEN_FEATURE_REG,
-                               RTL8366S_GREEN_FEATURE_RX_BIT, rx))
-        return -1;
-
-    return 0;
-}
-
-int rtl8366s_setPowerSaving(uint32_t phyNum, uint32_t enabled)
-{
-    uint16_t regData;
-
-    if (phyNum > RTL8366S_PHY_NO_MAX)
-        return -1;
-
-    if (rtl8366_getPhyReg(phyNum, 12, &regData))
-        return -1;
-
-    if (enabled)
-        regData |= (1 << 12);
-    else
-        regData &= ~(1 << 12);
-
-    if (rtl8366_setPhyReg(phyNum, 12, regData))
-        return -1;
-
-    return 0;
-}
-
-int rtl8366s_setGreenEthernet(uint32_t greenFeature, uint32_t powerSaving)
-{
-    uint32_t phyNum, i;
-    uint16_t regData;
-
-	const uint16_t greenSettings[][2] =
-	{
-		{0xBE5B,0x3500},
-		{0xBE5C,0xB975},
-		{0xBE5D,0xB9B9},
-		{0xBE77,0xA500},
-		{0xBE78,0x5A78},
-		{0xBE79,0x6478}
-	};
-
-    if (rtl8366_readRegister(RTL8366S_MODEL_ID_REG, &regData))
-        return -1;
-
-	switch (regData)
-	{
-		case 0x0000:
-			for (i = 0; i < 6; i++) {
-				if (rtl8366_writeRegister(RTL8366S_PHY_ACCESS_CTRL_REG, RTL8366S_PHY_CTRL_WRITE))
-					return -1;
-				if (rtl8366_writeRegister(greenSettings[i][0], greenSettings[i][1]))
-					return -1;
-			}
-			break;
-
-		case RTL8366S_MODEL_8366SR:
-			if (rtl8366_writeRegister(RTL8366S_PHY_ACCESS_CTRL_REG, RTL8366S_PHY_CTRL_WRITE))
-				return -1;
-			if (rtl8366_writeRegister(greenSettings[0][0], greenSettings[0][1]))
-				return -1;
-			break;
-
-		default:
-			printf("rtl8366s_initChip: unsupported chip found!\n");
-			return -1;
-	}
-
-    if (rtl8366s_setGreenFeature(greenFeature, powerSaving))
-        return -1;
-
-    for (phyNum = 0; phyNum <= RTL8366S_PHY_NO_MAX; phyNum++) {
-        if (rtl8366s_setPowerSaving(phyNum, powerSaving))
-            return -1;
-    }
-
-    return 0;
-}
-
-int rtl8366s_setCPUPortMask(uint8_t port, uint32_t enabled)
-{
-	if(port >= 6){
-		printf("rtl8366s_setCPUPortMask: invalid port number\n");
-		return -1;
-	}
-
-	return rtl8366_setRegisterBit(RTL8366S_CPU_CTRL_REG, port, enabled);
-}
-
-int rtl8366s_setCPUDisableInsTag(uint32_t enable)
-{
-	return rtl8366_setRegisterBit(RTL8366S_CPU_CTRL_REG,
-		RTL8366S_CPU_INSTAG_BIT, enable);
-}
-
-int rtl8366s_setCPUDropUnda(uint32_t enable)
-{
-	return rtl8366_setRegisterBit(RTL8366S_CPU_CTRL_REG,
-		RTL8366S_CPU_DRP_BIT, enable);
-}
-
-int rtl8366s_setCPUPort(uint8_t port, uint32_t noTag, uint32_t dropUnda)
-{
-	uint32_t i;
-
-	if(port >= 6){
-		printf("rtl8366s_setCPUPort: invalid port number\n");
-		return -1;
-	}
-
-	/* reset register */
-	for(i = 0; i < 6; i++)
-	{
-		if(rtl8366s_setCPUPortMask(i, 0)){
-			printf("rtl8366s_setCPUPort: rtl8366s_setCPUPortMask failed\n");
-			return -1;
-		}
-	}
-
-	if(rtl8366s_setCPUPortMask(port, 1)){
-		printf("rtl8366s_setCPUPort: rtl8366s_setCPUPortMask failed\n");
-		return -1;
-	}
-
-	if(rtl8366s_setCPUDisableInsTag(noTag)){
-		printf("rtl8366s_setCPUPort: rtl8366s_setCPUDisableInsTag fail\n");
-		return -1;
-	}
-
-	if(rtl8366s_setCPUDropUnda(dropUnda)){
-		printf("rtl8366s_setCPUPort: rtl8366s_setCPUDropUnda fail\n");
-		return -1;
-	}
-
-	return 0;
-}
-
-int rtl8366s_setLedConfig(uint32_t ledNum, uint8_t config)
-{
-    uint16_t regData;
-
-	if(ledNum >= RTL8366S_LED_GROUP_MAX) {
-		DBG("rtl8366s_setLedConfig: invalid led group\n");
-		return -1;
-	}
-
-    if(config > RTL8366S_LEDCONF_LEDFORCE) {
-		DBG("rtl8366s_setLedConfig: invalid led config\n");
-		return -1;
-	}
-
-	if (rtl8366_readRegister(RTL8366S_LED_INDICATED_CONF_REG, &regData)) {
-        printf("rtl8366s_setLedConfig: failed to get led register!\n");
-        return -1;
-	}
-
-	regData &= ~(0xF << (ledNum * 4));
-	regData |= config << (ledNum * 4);
-
-	if (rtl8366_writeRegister(RTL8366S_LED_INDICATED_CONF_REG, regData)) {
-        printf("rtl8366s_setLedConfig: failed to set led register!\n");
-        return -1;
-	}
-
-	return 0;
-}
-
-int rtl8366s_getLedConfig(uint32_t ledNum, uint8_t *config)
-{
-    uint16_t regData;
-
-	if(ledNum >= RTL8366S_LED_GROUP_MAX) {
-		DBG("rtl8366s_getLedConfig: invalid led group\n");
-		return -1;
-	}
-
-    if (rtl8366_readRegister(RTL8366S_LED_INDICATED_CONF_REG, &regData)) {
-        printf("rtl8366s_getLedConfig: failed to get led register!\n");
-        return -1;
-	}
-
-	if (config)
-        *config = (regData >> (ledNum * 4)) & 0xF;
-
-    return 0;
-}
-
-int rtl8366s_setLedForceValue(uint32_t group0, uint32_t group1,
-                              uint32_t group2, uint32_t group3)
-{
-    uint16_t regData;
-
-    regData = (group0 & 0x3F) | ((group1 & 0x3F) << 6);
-	if (rtl8366_writeRegister(RTL8366S_LED_0_1_FORCE_REG, regData)) {
-        printf("rtl8366s_setLedForceValue: failed to set led register!\n");
-        return -1;
-	}
-
-    regData = (group2 & 0x3F) | ((group3 & 0x3F) << 6);
-	if (rtl8366_writeRegister(RTL8366S_LED_2_3_FORCE_REG, regData)) {
-        printf("rtl8366s_setLedForceValue: failed to set led register!\n");
-        return -1;
-	}
-
-	return 0;
-}
-
-int rtl8366s_initChip(void)
-{
-    uint32_t ledGroup, i = 0;
-    uint16_t regData;
-    uint8_t ledData[RTL8366S_LED_GROUP_MAX];
-	const uint16_t (*chipData)[2];
-
-	const uint16_t chipB[][2] =
-	{
-		{0x0000,	0x0038},{0x8100,	0x1B37},{0xBE2E,	0x7B9F},{0xBE2B,	0xA4C8},
-		{0xBE74,	0xAD14},{0xBE2C,	0xDC00},{0xBE69,	0xD20F},{0xBE3B,	0xB414},
-		{0xBE24,	0x0000},{0xBE23,	0x00A1},{0xBE22,	0x0008},{0xBE21,	0x0120},
-		{0xBE20,	0x1000},{0xBE24,	0x0800},{0xBE24,	0x0000},{0xBE24,	0xF000},
-		{0xBE23,	0xDF01},{0xBE22,	0xDF20},{0xBE21,	0x101A},{0xBE20,	0xA0FF},
-		{0xBE24,	0xF800},{0xBE24,	0xF000},{0x0242,	0x02BF},{0x0245,	0x02BF},
-		{0x0248,	0x02BF},{0x024B,	0x02BF},{0x024E,	0x02BF},{0x0251,	0x02BF},
-		{0x0230,	0x0A32},{0x0233,	0x0A32},{0x0236,	0x0A32},{0x0239,	0x0A32},
-		{0x023C,	0x0A32},{0x023F,	0x0A32},{0x0254,	0x0A3F},{0x0255,	0x0064},
-		{0x0256,	0x0A3F},{0x0257,	0x0064},{0x0258,	0x0A3F},{0x0259,	0x0064},
-		{0x025A,	0x0A3F},{0x025B,	0x0064},{0x025C,	0x0A3F},{0x025D,	0x0064},
-		{0x025E,	0x0A3F},{0x025F,	0x0064},{0x0260,	0x0178},{0x0261,	0x01F4},
-		{0x0262,	0x0320},{0x0263,	0x0014},{0x021D,	0x9249},{0x021E,	0x0000},
-		{0x0100,	0x0004},{0xBE4A,	0xA0B4},{0xBE40,	0x9C00},{0xBE41,	0x501D},
-		{0xBE48,	0x3602},{0xBE47,	0x8051},{0xBE4C,	0x6465},{0x8000,	0x1F00},
-		{0x8001,	0x000C},{0x8008,	0x0000},{0x8007,	0x0000},{0x800C,	0x00A5},
-		{0x8101,	0x02BC},{0xBE53,	0x0005},{0x8E45,	0xAFE8},{0x8013,	0x0005},
-		{0xBE4B,	0x6700},{0x800B,	0x7000},{0xBE09,	0x0E00},
-		{0xFFFF, 0xABCD}
-	};
-
-    const uint16_t chipDefault[][2] =
-    {
-        {0x0242, 0x02BF},{0x0245, 0x02BF},{0x0248, 0x02BF},{0x024B, 0x02BF},
-		{0x024E, 0x02BF},{0x0251, 0x02BF},
-		{0x0254, 0x0A3F},{0x0256, 0x0A3F},{0x0258, 0x0A3F},{0x025A, 0x0A3F},
-		{0x025C, 0x0A3F},{0x025E, 0x0A3F},
-		{0x0263, 0x007C},{0x0100, 0x0004},
-		{0xBE5B, 0x3500},{0x800E, 0x200F},{0xBE1D, 0x0F00},{0x8001, 0x5011},
-		{0x800A, 0xA2F4},{0x800B, 0x17A3},{0xBE4B, 0x17A3},{0xBE41, 0x5011},
-		{0xBE17, 0x2100},{0x8000, 0x8304},{0xBE40, 0x8304},{0xBE4A, 0xA2F4},
-		{0x800C, 0xA8D5},{0x8014, 0x5500},{0x8015, 0x0004},{0xBE4C, 0xA8D5},
-		{0xBE59, 0x0008},{0xBE09, 0x0E00},{0xBE36, 0x1036},{0xBE37, 0x1036},
-		{0x800D, 0x00FF},{0xBE4D, 0x00FF},
-		{0xFFFF, 0xABCD}
-    };
-
-	DBG("rtl8366s_initChip\n");
-
-    /* save current led config and set to led force */
-    for (ledGroup = 0; ledGroup < RTL8366S_LED_GROUP_MAX; ledGroup++) {
-        if (rtl8366s_getLedConfig(ledGroup, &ledData[ledGroup]))
-            return -1;
-
-        if (rtl8366s_setLedConfig(ledGroup, RTL8366S_LEDCONF_LEDFORCE))
-            return -1;
-    }
-
-    if (rtl8366s_setLedForceValue(0,0,0,0))
-        return -1;
-
-    if (rtl8366_readRegister(RTL8366S_MODEL_ID_REG, &regData))
-        return -1;
-
-	switch (regData)
-	{
-		case 0x0000:
-			chipData = chipB;
-			break;
-
-		case RTL8366S_MODEL_8366SR:
-			chipData = chipDefault;
-			break;
-
-		default:
-			printf("rtl8366s_initChip: unsupported chip found!\n");
-			return -1;
-	}
-
-    DBG("rtl8366s_initChip: found %x chip\n", regData);
-
-    while ((chipData[i][0] != 0xFFFF) && (chipData[i][1] != 0xABCD)) {
-
-        /* phy settings*/
-        if ((chipData[i][0] & 0xBE00) == 0xBE00) {
-            if (rtl8366_writeRegister(RTL8366S_PHY_ACCESS_CTRL_REG,
-                                      RTL8366S_PHY_CTRL_WRITE))
-                return -1;
-        }
-
-        if (rtl8366_writeRegister(chipData[i][0], chipData[i][1]))
-            return -1;
-
-        i++;
-    }
-
-    /* chip needs some time */
-    udelay(100 * 1000);
-
-    /* restore led config */
-    for (ledGroup = 0; ledGroup < RTL8366S_LED_GROUP_MAX; ledGroup++) {
-        if (rtl8366s_setLedConfig(ledGroup, ledData[ledGroup]))
-            return -1;
-    }
-
-    return 0;
-}
-
-int rtl8366s_initialize(void)
-{
-	uint16_t regData;
-
-    DBG("rtl8366s_initialize: start setup\n");
-
-    smi_init();
-
-	rtl8366_readRegister(RTL8366S_CHIP_ID_REG, &regData);
-	DBG("Realtek 8366SR switch ID %#04x\n", regData);
-
-	if (regData != 0x8366) {
-		printf("rtl8366s_initialize: found unsupported switch\n");
-		return -1;
-	}
-
-    if (rtl8366s_initChip()) {
-        printf("rtl8366s_initialize: init chip failed\n");
-        return -1;
-    }
-
-	if (rtl8366s_setGreenEthernet(1, 1)) {
-       printf("rtl8366s_initialize: set green ethernet failed\n");
-       return -1;
-   }
-
-   	/* Set port 5 noTag and don't dropUnda */
-	if (rtl8366s_setCPUPort(5, 1, 0)) {
-		printf("rtl8366s_initialize: set CPU port failed\n");
-		return -1;
-	}
-
-    return 0;
-}

package/boot/uboot-ar71xx/src/drivers/spi/ar71xx_spi.c

@@ -1,191 +0,0 @@
-/*
- * (C) Copyright 2010
- * Michael Kurz <michi.kurz@googlemail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <spi.h>
-
-#include <asm/addrspace.h>
-#include <asm/types.h>
-#include <asm/ar71xx.h>
-
-/*-----------------------------------------------------------------------
- * Definitions
- */
-
-#ifdef DEBUG_SPI
-#define PRINTD(fmt,args...)	printf (fmt ,##args)
-#else
-#define PRINTD(fmt,args...)
-#endif
-
-struct ar71xx_spi_slave {
-	struct spi_slave slave;
-	unsigned int mode;
-};
-
-static inline struct ar71xx_spi_slave *to_ar71xx_spi(struct spi_slave *slave)
-{
-	return container_of(slave, struct ar71xx_spi_slave, slave);
-}
-
-/*=====================================================================*/
-/*                         Public Functions                            */
-/*=====================================================================*/
-
-/*-----------------------------------------------------------------------
- * Initialization
- */
- 
-void spi_init()
-{
-	PRINTD("ar71xx_spi: spi_init");
-
-	// Init SPI Hardware, disable remap, set clock
-	__raw_writel(0x43, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_CTRL));
-	
-	PRINTD(" ---> out\n");
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-		unsigned int max_hz, unsigned int mode)
-{
-	struct ar71xx_spi_slave *ss;
-
-	PRINTD("ar71xx_spi: spi_setup_slave");
-	
-	if ((bus != 0) || (cs > 2))
-		return NULL;
-
-	ss = malloc(sizeof(struct ar71xx_spi_slave));
-	if (!ss)
-		return NULL;
-
-	ss->slave.bus = bus;
-	ss->slave.cs = cs;
-	ss->mode = mode;
-
-	/* TODO: Use max_hz to limit the SCK rate */
-
-	PRINTD(" ---> out\n");
-	
-	return &ss->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-	struct ar71xx_spi_slave *ss = to_ar71xx_spi(slave);
-
-	free(ss);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-
-	return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
-		void *din, unsigned long flags)
-{
-	struct ar71xx_spi_slave *ss = to_ar71xx_spi(slave);
-	uint8_t *rx = din;
-	const uint8_t *tx = dout;
-	uint8_t curbyte, curbitlen, restbits;
-	uint32_t bytes = bitlen / 8;
-	uint32_t out;
-	uint32_t in;
-	
-	PRINTD("ar71xx_spi: spi_xfer: slave:%p bitlen:%08x dout:%p din:%p flags:%08x\n", slave, bitlen, dout, din, flags);
-	
-	if (flags & SPI_XFER_BEGIN) {
-		__raw_writel(SPI_FS_GPIO, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_FS));
-		__raw_writel(SPI_IOC_CS_ALL, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_IOC));
-	}
-	
-	restbits = (bitlen % 8);
-	if (restbits != 0)
-		bytes++;
-
-	// enable chip select
-	out = SPI_IOC_CS_ALL & ~(SPI_IOC_CS(slave->cs));
-
-	while (bytes--) {
-		
-		curbyte = 0;
-		if (tx) {
-			curbyte = *tx++;
-		}
-		
-		if (restbits != 0) {
-			curbitlen = restbits;
-			curbyte <<= 8 - restbits;
-		} else {
-			curbitlen = 8;
-		}
-		
-		PRINTD("ar71xx_spi: sending: data:%02x length:%d\n", curbyte, curbitlen);
-		
-		/* clock starts at inactive polarity */
-		for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
-
-			if (curbyte & (1 << 7))
-				out |= SPI_IOC_DO;
-			else
-				out &= ~(SPI_IOC_DO);
-
-			/* setup MSB (to slave) on trailing edge */
-			__raw_writel(out, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_IOC));
-
-			__raw_writel(out | SPI_IOC_CLK, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_IOC));
-
-			curbyte <<= 1;
-		}
-		
-		in = __raw_readl(KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_RDS));
-		PRINTD("ar71xx_spi: received:%02x\n", in);
-		
-		if (rx) {
-			if (restbits == 0) {
-				*rx++ = in;
-			} else {
-				*rx++ = (in << (8 - restbits));
-			}
-		}
-	}
-	
-	if (flags & SPI_XFER_END) {
-		__raw_writel(SPI_IOC_CS(slave->cs), KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_IOC));
-		__raw_writel(SPI_IOC_CS_ALL, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_IOC));
-		__raw_writel(0, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_FS));
-	}
-
-	PRINTD(" ---> out\n");
-	
-	return 0;
-}

package/boot/uboot-ar71xx/src/include/asm-mips/ar71xx.h

@@ -1,515 +0,0 @@
-/*
- *  Atheros AR71xx SoC specific definitions
- *
- *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
- *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- *  Parts of this file are based on Atheros' 2.6.15 BSP
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- */
-
-#ifndef __ASM_MACH_AR71XX_H
-#define __ASM_MACH_AR71XX_H
-
-#include <linux/types.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-
-#ifndef __ASSEMBLER__
-
-#define BIT(x)	(1<<(x))
-
-#define AR71XX_PCI_MEM_BASE	0x10000000
-#define AR71XX_PCI_MEM_SIZE	0x08000000
-#define AR71XX_APB_BASE		0x18000000
-#define AR71XX_GE0_BASE		0x19000000
-#define AR71XX_GE0_SIZE		0x01000000
-#define AR71XX_GE1_BASE		0x1a000000
-#define AR71XX_GE1_SIZE		0x01000000
-#define AR71XX_EHCI_BASE	0x1b000000
-#define AR71XX_EHCI_SIZE	0x01000000
-#define AR71XX_OHCI_BASE	0x1c000000
-#define AR71XX_OHCI_SIZE	0x01000000
-#define AR7240_OHCI_BASE	0x1b000000
-#define AR7240_OHCI_SIZE	0x01000000
-#define AR71XX_SPI_BASE		0x1f000000
-#define AR71XX_SPI_SIZE		0x01000000
-
-#define AR71XX_DDR_CTRL_BASE	(AR71XX_APB_BASE + 0x00000000)
-#define AR71XX_DDR_CTRL_SIZE	0x10000
-#define AR71XX_CPU_BASE		(AR71XX_APB_BASE + 0x00010000)
-#define AR71XX_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
-#define AR71XX_UART_SIZE	0x10000
-#define AR71XX_USB_CTRL_BASE	(AR71XX_APB_BASE + 0x00030000)
-#define AR71XX_USB_CTRL_SIZE	0x10000
-#define AR71XX_GPIO_BASE	(AR71XX_APB_BASE + 0x00040000)
-#define AR71XX_GPIO_SIZE	0x10000
-#define AR71XX_PLL_BASE		(AR71XX_APB_BASE + 0x00050000)
-#define AR71XX_PLL_SIZE		0x10000
-#define AR71XX_RESET_BASE	(AR71XX_APB_BASE + 0x00060000)
-#define AR71XX_RESET_SIZE	0x10000
-#define AR71XX_MII_BASE		(AR71XX_APB_BASE + 0x00070000)
-#define AR71XX_MII_SIZE		0x10000
-#define AR71XX_SLIC_BASE	(AR71XX_APB_BASE + 0x00090000)
-#define AR71XX_SLIC_SIZE	0x10000
-#define AR71XX_DMA_BASE		(AR71XX_APB_BASE + 0x000A0000)
-#define AR71XX_DMA_SIZE		0x10000
-#define AR71XX_STEREO_BASE	(AR71XX_APB_BASE + 0x000B0000)
-#define AR71XX_STEREO_SIZE	0x10000
-
-#define AR724X_PCI_CRP_BASE	(AR71XX_APB_BASE + 0x000C0000)
-#define AR724X_PCI_CRP_SIZE	0x100
-
-#define AR724X_PCI_CTRL_BASE	(AR71XX_APB_BASE + 0x000F0000)
-#define AR724X_PCI_CTRL_SIZE	0x100
-
-#define AR91XX_WMAC_BASE	(AR71XX_APB_BASE + 0x000C0000)
-#define AR91XX_WMAC_SIZE	0x30000
-
-#define AR71XX_MEM_SIZE_MIN	0x0200000
-#define AR71XX_MEM_SIZE_MAX	0x10000000
-
-#define AR71XX_CPU_IRQ_BASE	0
-#define AR71XX_MISC_IRQ_BASE	8
-#define AR71XX_MISC_IRQ_COUNT	8
-#define AR71XX_GPIO_IRQ_BASE	16
-#define AR71XX_GPIO_IRQ_COUNT	32
-#define AR71XX_PCI_IRQ_BASE     48
-#define AR71XX_PCI_IRQ_COUNT	8
-
-#define AR71XX_CPU_IRQ_IP2	(AR71XX_CPU_IRQ_BASE + 2)
-#define AR71XX_CPU_IRQ_USB	(AR71XX_CPU_IRQ_BASE + 3)
-#define AR71XX_CPU_IRQ_GE0	(AR71XX_CPU_IRQ_BASE + 4)
-#define AR71XX_CPU_IRQ_GE1	(AR71XX_CPU_IRQ_BASE + 5)
-#define AR71XX_CPU_IRQ_MISC	(AR71XX_CPU_IRQ_BASE + 6)
-#define AR71XX_CPU_IRQ_TIMER	(AR71XX_CPU_IRQ_BASE + 7)
-
-#define AR71XX_MISC_IRQ_TIMER	(AR71XX_MISC_IRQ_BASE + 0)
-#define AR71XX_MISC_IRQ_ERROR	(AR71XX_MISC_IRQ_BASE + 1)
-#define AR71XX_MISC_IRQ_GPIO	(AR71XX_MISC_IRQ_BASE + 2)
-#define AR71XX_MISC_IRQ_UART	(AR71XX_MISC_IRQ_BASE + 3)
-#define AR71XX_MISC_IRQ_WDOG	(AR71XX_MISC_IRQ_BASE + 4)
-#define AR71XX_MISC_IRQ_PERFC	(AR71XX_MISC_IRQ_BASE + 5)
-#define AR71XX_MISC_IRQ_OHCI	(AR71XX_MISC_IRQ_BASE + 6)
-#define AR71XX_MISC_IRQ_DMA	(AR71XX_MISC_IRQ_BASE + 7)
-
-#define AR71XX_GPIO_IRQ(_x)	(AR71XX_GPIO_IRQ_BASE + (_x))
-
-#define AR71XX_PCI_IRQ_DEV0	(AR71XX_PCI_IRQ_BASE + 0)
-#define AR71XX_PCI_IRQ_DEV1	(AR71XX_PCI_IRQ_BASE + 1)
-#define AR71XX_PCI_IRQ_DEV2	(AR71XX_PCI_IRQ_BASE + 2)
-#define AR71XX_PCI_IRQ_CORE	(AR71XX_PCI_IRQ_BASE + 4)
-
-extern u32 ar71xx_ahb_freq;
-extern u32 ar71xx_cpu_freq;
-extern u32 ar71xx_ddr_freq;
-
-enum ar71xx_soc_type {
-	AR71XX_SOC_UNKNOWN,
-	AR71XX_SOC_AR7130,
-	AR71XX_SOC_AR7141,
-	AR71XX_SOC_AR7161,
-	AR71XX_SOC_AR7240,
-	AR71XX_SOC_AR7241,
-	AR71XX_SOC_AR7242,
-	AR71XX_SOC_AR9130,
-	AR71XX_SOC_AR9132
-};
-
-extern enum ar71xx_soc_type ar71xx_soc;
-
-/*
- * PLL block
- */
-#define AR71XX_PLL_REG_CPU_CONFIG	0x00
-#define AR71XX_PLL_REG_SEC_CONFIG	0x04
-#define AR71XX_PLL_REG_ETH0_INT_CLOCK	0x10
-#define AR71XX_PLL_REG_ETH1_INT_CLOCK	0x14
-
-#define AR71XX_PLL_DIV_SHIFT		3
-#define AR71XX_PLL_DIV_MASK		0x1f
-#define AR71XX_CPU_DIV_SHIFT		16
-#define AR71XX_CPU_DIV_MASK		0x3
-#define AR71XX_DDR_DIV_SHIFT		18
-#define AR71XX_DDR_DIV_MASK		0x3
-#define AR71XX_AHB_DIV_SHIFT		20
-#define AR71XX_AHB_DIV_MASK		0x7
-
-#define AR71XX_ETH0_PLL_SHIFT		17
-#define AR71XX_ETH1_PLL_SHIFT		19
-
-#define AR724X_PLL_REG_CPU_CONFIG	0x00
-#define AR724X_PLL_REG_PCIE_CONFIG	0x18
-
-#define AR724X_PLL_DIV_SHIFT		0
-#define AR724X_PLL_DIV_MASK		0x3ff
-#define AR724X_PLL_REF_DIV_SHIFT	10
-#define AR724X_PLL_REF_DIV_MASK		0xf
-#define AR724X_AHB_DIV_SHIFT		19
-#define AR724X_AHB_DIV_MASK		0x1
-#define AR724X_DDR_DIV_SHIFT		22
-#define AR724X_DDR_DIV_MASK		0x3
-
-#define AR91XX_PLL_REG_CPU_CONFIG	0x00
-#define AR91XX_PLL_REG_ETH_CONFIG	0x04
-#define AR91XX_PLL_REG_ETH0_INT_CLOCK	0x14
-#define AR91XX_PLL_REG_ETH1_INT_CLOCK	0x18
-
-#define AR91XX_PLL_DIV_SHIFT		0
-#define AR91XX_PLL_DIV_MASK		0x3ff
-#define AR91XX_DDR_DIV_SHIFT		22
-#define AR91XX_DDR_DIV_MASK		0x3
-#define AR91XX_AHB_DIV_SHIFT		19
-#define AR91XX_AHB_DIV_MASK		0x1
-
-#define AR91XX_ETH0_PLL_SHIFT		20
-#define AR91XX_ETH1_PLL_SHIFT		22
-
-// extern void __iomem *ar71xx_pll_base;
-
-// static inline void ar71xx_pll_wr(unsigned reg, u32 val)
-// {
-	// __raw_writel(val, ar71xx_pll_base + reg);
-// }
-
-// static inline u32 ar71xx_pll_rr(unsigned reg)
-// {
-	// return __raw_readl(ar71xx_pll_base + reg);
-// }
-
-/*
- * USB_CONFIG block
- */
-#define USB_CTRL_REG_FLADJ	0x00
-#define USB_CTRL_REG_CONFIG	0x04
-
-// extern void __iomem *ar71xx_usb_ctrl_base;
-
-// static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
-// {
-	// __raw_writel(val, ar71xx_usb_ctrl_base + reg);
-// }
-
-// static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
-// {
-	// return __raw_readl(ar71xx_usb_ctrl_base + reg);
-// }
-
-/*
- * GPIO block
- */
-#define GPIO_REG_OE		0x00
-#define GPIO_REG_IN		0x04
-#define GPIO_REG_OUT		0x08
-#define GPIO_REG_SET		0x0c
-#define GPIO_REG_CLEAR		0x10
-#define GPIO_REG_INT_MODE	0x14
-#define GPIO_REG_INT_TYPE	0x18
-#define GPIO_REG_INT_POLARITY	0x1c
-#define GPIO_REG_INT_PENDING	0x20
-#define GPIO_REG_INT_ENABLE	0x24
-#define GPIO_REG_FUNC		0x28
-
-#define AR71XX_GPIO_FUNC_STEREO_EN	BIT(17)
-#define AR71XX_GPIO_FUNC_SLIC_EN	BIT(16)
-#define AR71XX_GPIO_FUNC_SPI_CS2_EN	BIT(13)
-#define AR71XX_GPIO_FUNC_SPI_CS1_EN	BIT(12)
-#define AR71XX_GPIO_FUNC_UART_EN	BIT(8)
-#define AR71XX_GPIO_FUNC_USB_OC_EN	BIT(4)
-#define AR71XX_GPIO_FUNC_USB_CLK_EN	BIT(0)
-
-#define AR71XX_GPIO_COUNT	16
-
-#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN		BIT(19)
-#define AR724X_GPIO_FUNC_SPI_EN			BIT(18)
-#define AR724X_GPIO_FUNC_SPI_CS_EN2		BIT(14)
-#define AR724X_GPIO_FUNC_SPI_CS_EN1		BIT(13)
-#define AR724X_GPIO_FUNC_CLK_OBS5_EN		BIT(12)
-#define AR724X_GPIO_FUNC_CLK_OBS4_EN		BIT(11)
-#define AR724X_GPIO_FUNC_CLK_OBS3_EN		BIT(10)
-#define AR724X_GPIO_FUNC_CLK_OBS2_EN		BIT(9)
-#define AR724X_GPIO_FUNC_CLK_OBS1_EN		BIT(8)
-#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN	BIT(7)
-#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN	BIT(6)
-#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN	BIT(5)
-#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN	BIT(4)
-#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN	BIT(3)
-#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN	BIT(2)
-#define AR724X_GPIO_FUNC_UART_EN		BIT(1)
-#define AR724X_GPIO_FUNC_JTAG_DISABLE		BIT(0)
-
-#define AR724X_GPIO_COUNT	18
-
-#define AR91XX_GPIO_FUNC_WMAC_LED_EN	BIT(22)
-#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN	BIT(21)
-#define AR91XX_GPIO_FUNC_I2S_REFCLKEN	BIT(20)
-#define AR91XX_GPIO_FUNC_I2S_MCKEN	BIT(19)
-#define AR91XX_GPIO_FUNC_I2S1_EN	BIT(18)
-#define AR91XX_GPIO_FUNC_I2S0_EN	BIT(17)
-#define AR91XX_GPIO_FUNC_SLIC_EN	BIT(16)
-#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN	BIT(9)
-#define AR91XX_GPIO_FUNC_UART_EN	BIT(8)
-#define AR91XX_GPIO_FUNC_USB_CLK_EN	BIT(4)
-
-#define AR91XX_GPIO_COUNT	22
-
-// extern void __iomem *ar71xx_gpio_base;
-
-// static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
-// {
-	// __raw_writel(value, ar71xx_gpio_base + reg);
-// }
-
-// static inline u32 ar71xx_gpio_rr(unsigned reg)
-// {
-	// return __raw_readl(ar71xx_gpio_base + reg);
-// }
-
-// void ar71xx_gpio_init(void) __init;
-// void ar71xx_gpio_function_enable(u32 mask);
-// void ar71xx_gpio_function_disable(u32 mask);
-// void ar71xx_gpio_function_setup(u32 set, u32 clear);
-
-/*
- * DDR_CTRL block
- */
-#define AR71XX_DDR_REG_PCI_WIN0		0x7c
-#define AR71XX_DDR_REG_PCI_WIN1		0x80
-#define AR71XX_DDR_REG_PCI_WIN2		0x84
-#define AR71XX_DDR_REG_PCI_WIN3		0x88
-#define AR71XX_DDR_REG_PCI_WIN4		0x8c
-#define AR71XX_DDR_REG_PCI_WIN5		0x90
-#define AR71XX_DDR_REG_PCI_WIN6		0x94
-#define AR71XX_DDR_REG_PCI_WIN7		0x98
-#define AR71XX_DDR_REG_FLUSH_GE0	0x9c
-#define AR71XX_DDR_REG_FLUSH_GE1	0xa0
-#define AR71XX_DDR_REG_FLUSH_USB	0xa4
-#define AR71XX_DDR_REG_FLUSH_PCI	0xa8
-
-#define AR724X_DDR_REG_FLUSH_GE0	0x7c
-#define AR724X_DDR_REG_FLUSH_GE1	0x80
-#define AR724X_DDR_REG_FLUSH_USB	0x84
-#define AR724X_DDR_REG_FLUSH_PCIE	0x88
-
-#define AR91XX_DDR_REG_FLUSH_GE0	0x7c
-#define AR91XX_DDR_REG_FLUSH_GE1	0x80
-#define AR91XX_DDR_REG_FLUSH_USB	0x84
-#define AR91XX_DDR_REG_FLUSH_WMAC	0x88
-
-#define PCI_WIN0_OFFS	0x10000000
-#define PCI_WIN1_OFFS	0x11000000
-#define PCI_WIN2_OFFS	0x12000000
-#define PCI_WIN3_OFFS	0x13000000
-#define PCI_WIN4_OFFS	0x14000000
-#define PCI_WIN5_OFFS	0x15000000
-#define PCI_WIN6_OFFS	0x16000000
-#define PCI_WIN7_OFFS	0x07000000
-
-// extern void __iomem *ar71xx_ddr_base;
-
-// static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
-// {
-	// __raw_writel(val, ar71xx_ddr_base + reg);
-// }
-
-// static inline u32 ar71xx_ddr_rr(unsigned reg)
-// {
-	// return __raw_readl(ar71xx_ddr_base + reg);
-// }
-
-// void ar71xx_ddr_flush(u32 reg);
-
-/*
- * PCI block
- */
-#define AR71XX_PCI_CFG_BASE	(AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
-#define AR71XX_PCI_CFG_SIZE	0x100
-
-#define PCI_REG_CRP_AD_CBE	0x00
-#define PCI_REG_CRP_WRDATA	0x04
-#define PCI_REG_CRP_RDDATA	0x08
-#define PCI_REG_CFG_AD		0x0c
-#define PCI_REG_CFG_CBE		0x10
-#define PCI_REG_CFG_WRDATA	0x14
-#define PCI_REG_CFG_RDDATA	0x18
-#define PCI_REG_PCI_ERR		0x1c
-#define PCI_REG_PCI_ERR_ADDR	0x20
-#define PCI_REG_AHB_ERR		0x24
-#define PCI_REG_AHB_ERR_ADDR	0x28
-
-#define PCI_CRP_CMD_WRITE	0x00010000
-#define PCI_CRP_CMD_READ	0x00000000
-#define PCI_CFG_CMD_READ	0x0000000a
-#define PCI_CFG_CMD_WRITE	0x0000000b
-
-#define PCI_IDSEL_ADL_START	17
-
-#define AR724X_PCI_CFG_BASE	(AR71XX_PCI_MEM_BASE + 0x4000000)
-#define AR724X_PCI_CFG_SIZE	0x1000
-
-#define AR724X_PCI_REG_APP		0x00
-#define AR724X_PCI_REG_RESET		0x18
-#define AR724X_PCI_REG_INT_STATUS	0x4c
-#define AR724X_PCI_REG_INT_MASK		0x50
-
-#define AR724X_PCI_APP_LTSSM_ENABLE	BIT(0)
-#define AR724X_PCI_RESET_LINK_UP	BIT(0)
-
-#define AR724X_PCI_INT_DEV0		BIT(14)
-
-/*
- * RESET block
- */
-#define AR71XX_RESET_REG_TIMER			0x00
-#define AR71XX_RESET_REG_TIMER_RELOAD		0x04
-#define AR71XX_RESET_REG_WDOG_CTRL		0x08
-#define AR71XX_RESET_REG_WDOG			0x0c
-#define AR71XX_RESET_REG_MISC_INT_STATUS	0x10
-#define AR71XX_RESET_REG_MISC_INT_ENABLE	0x14
-#define AR71XX_RESET_REG_PCI_INT_STATUS		0x18
-#define AR71XX_RESET_REG_PCI_INT_ENABLE		0x1c
-#define AR71XX_RESET_REG_GLOBAL_INT_STATUS	0x20
-#define AR71XX_RESET_REG_RESET_MODULE		0x24
-#define AR71XX_RESET_REG_PERFC_CTRL		0x2c
-#define AR71XX_RESET_REG_PERFC0			0x30
-#define AR71XX_RESET_REG_PERFC1			0x34
-#define AR71XX_RESET_REG_REV_ID			0x90
-
-#define AR91XX_RESET_REG_GLOBAL_INT_STATUS	0x18
-#define AR91XX_RESET_REG_RESET_MODULE		0x1c
-#define AR91XX_RESET_REG_PERF_CTRL		0x20
-#define AR91XX_RESET_REG_PERFC0			0x24
-#define AR91XX_RESET_REG_PERFC1			0x28
-
-#define AR724X_RESET_REG_RESET_MODULE		0x1c
-
-#define WDOG_CTRL_LAST_RESET		BIT(31)
-#define WDOG_CTRL_ACTION_MASK		3
-#define WDOG_CTRL_ACTION_NONE		0	/* no action */
-#define WDOG_CTRL_ACTION_GPI		1	/* general purpose interrupt */
-#define WDOG_CTRL_ACTION_NMI		2	/* NMI */
-#define WDOG_CTRL_ACTION_FCR		3	/* full chip reset */
-
-#define MISC_INT_DMA			BIT(7)
-#define MISC_INT_OHCI			BIT(6)
-#define MISC_INT_PERFC			BIT(5)
-#define MISC_INT_WDOG			BIT(4)
-#define MISC_INT_UART			BIT(3)
-#define MISC_INT_GPIO			BIT(2)
-#define MISC_INT_ERROR			BIT(1)
-#define MISC_INT_TIMER			BIT(0)
-
-#define PCI_INT_CORE			BIT(4)
-#define PCI_INT_DEV2			BIT(2)
-#define PCI_INT_DEV1			BIT(1)
-#define PCI_INT_DEV0			BIT(0)
-
-#define RESET_MODULE_EXTERNAL		BIT(28)
-#define RESET_MODULE_FULL_CHIP		BIT(24)
-#define RESET_MODULE_AMBA2WMAC		BIT(22)
-#define RESET_MODULE_CPU_NMI		BIT(21)
-#define RESET_MODULE_CPU_COLD		BIT(20)
-#define RESET_MODULE_DMA		BIT(19)
-#define RESET_MODULE_SLIC		BIT(18)
-#define RESET_MODULE_STEREO		BIT(17)
-#define RESET_MODULE_DDR		BIT(16)
-#define RESET_MODULE_GE1_MAC		BIT(13)
-#define RESET_MODULE_GE1_PHY		BIT(12)
-#define RESET_MODULE_USBSUS_OVERRIDE	BIT(10)
-#define RESET_MODULE_GE0_MAC		BIT(9)
-#define RESET_MODULE_GE0_PHY		BIT(8)
-#define RESET_MODULE_USB_OHCI_DLL	BIT(6)
-#define RESET_MODULE_USB_HOST		BIT(5)
-#define RESET_MODULE_USB_PHY		BIT(4)
-#define RESET_MODULE_USB_OHCI_DLL_7240	BIT(3)
-#define RESET_MODULE_PCI_BUS		BIT(1)
-#define RESET_MODULE_PCI_CORE		BIT(0)
-
-#define AR724X_RESET_GE1_MDIO		BIT(23)
-#define AR724X_RESET_GE0_MDIO		BIT(22)
-#define AR724X_RESET_PCIE_PHY_SERIAL	BIT(10)
-#define AR724X_RESET_PCIE_PHY		BIT(7)
-#define AR724X_RESET_PCIE		BIT(6)
-
-#define REV_ID_MAJOR_MASK	0xfff0
-#define REV_ID_MAJOR_AR71XX	0x00a0
-#define REV_ID_MAJOR_AR913X	0x00b0
-#define REV_ID_MAJOR_AR7240	0x00c0
-#define REV_ID_MAJOR_AR7241	0x0100
-#define REV_ID_MAJOR_AR7242	0x1100
-
-#define AR71XX_REV_ID_MINOR_MASK	0x3
-#define AR71XX_REV_ID_MINOR_AR7130	0x0
-#define AR71XX_REV_ID_MINOR_AR7141	0x1
-#define AR71XX_REV_ID_MINOR_AR7161	0x2
-#define AR71XX_REV_ID_REVISION_MASK	0x3
-#define AR71XX_REV_ID_REVISION_SHIFT	2
-
-#define AR91XX_REV_ID_MINOR_MASK	0x3
-#define AR91XX_REV_ID_MINOR_AR9130	0x0
-#define AR91XX_REV_ID_MINOR_AR9132	0x1
-#define AR91XX_REV_ID_REVISION_MASK	0x3
-#define AR91XX_REV_ID_REVISION_SHIFT	2
-
-#define AR724X_REV_ID_REVISION_MASK	0x3
-
-// extern void __iomem *ar71xx_reset_base;
-
-static inline void ar71xx_reset_wr(unsigned reg, u32 val)
-{
-	__raw_writel(val, KSEG1ADDR(AR71XX_RESET_BASE) + reg);
-}
-
-static inline u32 ar71xx_reset_rr(unsigned reg)
-{
-	return __raw_readl(KSEG1ADDR(AR71XX_RESET_BASE) + reg);
-}
-
-// void ar71xx_device_stop(u32 mask);
-// void ar71xx_device_start(u32 mask);
-// int ar71xx_device_stopped(u32 mask);
-
-/*
- * SPI block
- */
-#define SPI_REG_FS		0x00	/* Function Select */
-#define SPI_REG_CTRL		0x04	/* SPI Control */
-#define SPI_REG_IOC		0x08	/* SPI I/O Control */
-#define SPI_REG_RDS		0x0c	/* Read Data Shift */
-
-#define SPI_FS_GPIO		BIT(0)	/* Enable GPIO mode */
-
-#define SPI_CTRL_RD		BIT(6)	/* Remap Disable */
-#define SPI_CTRL_DIV_MASK	0x3f
-
-#define SPI_IOC_DO		BIT(0)	/* Data Out pin */
-#define SPI_IOC_CLK		BIT(8)	/* CLK pin */
-#define SPI_IOC_CS(n)		BIT(16 + (n))
-#define SPI_IOC_CS0		SPI_IOC_CS(0)
-#define SPI_IOC_CS1		SPI_IOC_CS(1)
-#define SPI_IOC_CS2		SPI_IOC_CS(2)
-#define SPI_IOC_CS_ALL		(SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
-
-// void ar71xx_flash_acquire(void);
-// void ar71xx_flash_release(void);
-
-/*
- * MII_CTRL block
- */
-#define MII_REG_MII0_CTRL	0x00
-#define MII_REG_MII1_CTRL	0x04
-
-#define MII0_CTRL_IF_GMII	0
-#define MII0_CTRL_IF_MII	1
-#define MII0_CTRL_IF_RGMII	2
-#define MII0_CTRL_IF_RMII	3
-
-#define MII1_CTRL_IF_RGMII	0
-#define MII1_CTRL_IF_RMII	1
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* __ASM_MACH_AR71XX_H */

package/boot/uboot-ar71xx/src/include/asm-mips/ar71xx_gpio.h

@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2010
- * Michael Kurz <michi.kurz@googlemail.com>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _AR71XX_GPIO_H
-#define _AR71XX_GPIO_H
-
-#include <common.h>
-#include <asm/ar71xx.h>
-
-static inline void ar71xx_setpin(uint8_t pin, uint8_t state)
-{
-	uint32_t reg = readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OUT));
-
-	if (state != 0) {
-       reg |= (1 << pin);
-   } else {
-       reg &= ~(1 << pin);
-   }
-
-	writel(reg, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OUT));
-	readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OUT));
-}
-
-static inline uint32_t ar71xx_getpin(uint8_t pin)
-{
-    uint32_t reg = readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_IN));
-    return (((reg & (1 << pin)) != 0) ? 1 : 0);
-}
-
-static inline void ar71xx_setpindir(uint8_t pin, uint8_t direction)
-{
-	uint32_t reg = readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OE));
-
-	if (direction != 0) {
-        reg |= (1 << pin);
-    } else {
-        reg &= ~(1 << pin);
-    }
-
-	writel(reg, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OE));
-	readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OE));
-}
-
-
-#endif /* AR71XX_GPIO_H */

package/boot/uboot-ar71xx/src/include/configs/nbg460n.h

@@ -1,136 +0,0 @@
-/*
- * (C) Copyright 2010
- * Michael Kurz <michi.kurz@googlemail.com>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* This file contains the configuration parameters for the zyxel nbg460n board. */
-
-#ifndef _NBG460N_CONFIG_H
-#define _NBG460N_CONFIG_H
-
-#define CONFIG_MIPS32		1  /* MIPS32 CPU core */
-#define CONFIG_AR71XX		1
-#define CONFIG_AR91XX		1
-#define CONFIG_SYS_HZ		1000
-#define CONFIG_SYS_MIPS_TIMER_FREQ (400000000/2)
-
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE		32768
-#define CONFIG_SYS_ICACHE_SIZE		65536
-#define CONFIG_SYS_CACHELINE_SIZE	32
-/* Cache lock for stack */
-#define CONFIG_SYS_INIT_SP_OFFSET	0x1000
-
-#define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE)
-
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SYS_BAUDRATE_TABLE  {115200}
-
-#define CONFIG_MISC_INIT_R
-
-/* SPI-Flash support */
-#define CONFIG_SPI_FLASH
-#define CONFIG_AR71XX_SPI
-#define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SF_DEFAULT_HZ	25000000
-
-#define CONFIG_ENV_SPI_MAX_HZ	25000000
-#define CONFIG_ENV_SPI_BUS		0
-#define CONFIG_ENV_SPI_CS		0
-
-#define	CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_ADDR			0xbfc20000
-#define CONFIG_ENV_OFFSET		0x20000
-#define CONFIG_ENV_SIZE			0x01000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 64
-#define CONFIG_SYS_FLASH_BASE	0xbfc00000
-
-/* Net support */
-#define CONFIG_ETHADDR_ADDR     0xbfc0fff8
-#define CONFIG_SYS_RX_ETH_BUFFER  	16
-#define CONFIG_AG71XX
-#define CONFIG_AG71XX_PORTS     { 1, 1 }
-#define CONFIG_AG71XX_MII0_IIF  MII0_CTRL_IF_RGMII
-#define CONFIG_AG71XX_MII1_IIF  MII1_CTRL_IF_RGMII
-#define CONFIG_NET_MULTI
-#define CONFIG_IPADDR			192.168.1.254
-#define CONFIG_SERVERIP			192.168.1.42
-
-/* Switch support */
-#define CONFIG_MII
-#define CONFIG_RTL8366_MII
-#define RTL8366_PIN_SDA 16
-#define RTL8366_PIN_SCK 18
-#define MII_GPIOINCLUDE <asm/ar71xx_gpio.h>
-#define MII_SETSDA(x)   ar71xx_setpin(RTL8366_PIN_SDA, x)
-#define MII_GETSDA      ar71xx_getpin(RTL8366_PIN_SDA)
-#define MII_SETSCK(x)   ar71xx_setpin(RTL8366_PIN_SCK, x)
-#define MII_SDAINPUT    ar71xx_setpindir(RTL8366_PIN_SDA, 0)
-#define MII_SDAOUTPUT   ar71xx_setpindir(RTL8366_PIN_SDA, 1)
-#define MII_SCKINPUT    ar71xx_setpindir(RTL8366_PIN_SCK, 0)
-#define MII_SCKOUTPUT   ar71xx_setpindir(RTL8366_PIN_SCK, 1)
-
-#define CONFIG_BOOTDELAY	3
-#define	CONFIG_BOOTARGS		"console=ttyS0,115200 rootfstype==squashfs,jffs2 noinitrd machtype=NBG460N"
-#define CONFIG_BOOTCOMMAND	"bootm 0xbfc70000"
-#define CONFIG_LZMA
-
-
-/* Commands */
-#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SPI
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_PROMPT		"U-Boot> "
-#define CONFIG_SYS_CBSIZE		256
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP		1
-#define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * 0x10000 + 128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
-
-#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
-
-#define CONFIG_SYS_SDRAM_BASE		0x80000000     /* Cached addr */
-#define	CONFIG_SYS_LOAD_ADDR		0x80060000     /* default load address	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x80000800
-#define CONFIG_SYS_MEMTEST_END		0x81E00000
-
-#endif	/* _NBG460N_CONFIG_H */

package/boot/uboot-envtools/files/ipq40xx

@@ -31,11 +31,15 @@ ubootenv_mtdinfo () {
 }
 
 case "$board" in
+alfa-network,ap120c-ac |\
 glinet,gl-b1300 |\
 openmesh,a42 |\
 openmesh,a62)
 	ubootenv_add_uci_config "/dev/mtd5" "0x0" "0x10000" "0x10000"
 	;;
+linksys,ea6350v3)
+	ubootenv_add_uci_config "/dev/mtd7" "0x0" "0x20000" "0x20000"
+	;;
 zyxel,nbg6617)
 	ubootenv_add_uci_config "/dev/mtd6" "0x0" "0x10000" "0x10000"
 	;;

package/boot/uboot-envtools/files/mpc85xx

@@ -0,0 +1,22 @@
+#!/bin/sh
+
+[ -e /etc/config/ubootenv ] && exit 0
+
+touch /etc/config/ubootenv
+
+. /lib/uboot-envtools.sh
+. /lib/functions.sh
+
+board=$(board_name)
+
+case "$board" in
+ocedo,panda)
+	ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x20000"
+	ubootenv_add_uci_config "/dev/mtd2" "0x0" "0x20000" "0x20000"
+	;;
+esac
+
+config_load ubootenv
+config_foreach ubootenv_add_app_config ubootenv
+
+exit 0

package/boot/uboot-envtools/files/oxnas

@@ -13,11 +13,10 @@ touch /etc/config/ubootenv
 board=$(board_name)
 
 case "$board" in
-akitio|\
-kd20|\
-stg212)
-	ubootenv_add_uci_config "/dev/ubi0_0" "0x0" "0x4000" "0x1F000" "1"
-	ubootenv_add_uci_config "/dev/ubi0_1" "0x0" "0x4000" "0x1F000" "1"
+"cloudengines,pogoplug"* | \
+"mitrastar,stg-212" | \
+"shuttle,kd20")
+	ubootenv_add_uci_config "/dev/mtd2" "0x0" "0x2000" "0x2000" "1"
 	;;
 esac
 

package/boot/uboot-mvebu/Makefile

@@ -1,50 +0,0 @@
-#
-# Copyright (C) 2016 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_VERSION:=2018.03
-PKG_RELEASE:=1
-
-PKG_HASH:=7e7477534409d5368eb1371ffde6820f0f79780a1a1f676161c48442cb303dfd
-
-include $(INCLUDE_DIR)/u-boot.mk
-include $(INCLUDE_DIR)/package.mk
-include $(INCLUDE_DIR)/host-build.mk
-
-define U-Boot/Default
-  BUILD_TARGET:=mvebu
-  HIDDEN:=1
-endef
-
-define U-Boot/clearfog
-  NAME:=SolidRun ClearFog A1
-  BUILD_DEVICES:=armada-388-clearfog-base armada-388-clearfog-pro
-  BUILD_SUBTARGET:=cortexa9
-  UBOOT_IMAGE:=u-boot-spl.kwb
-endef
-
-UBOOT_TARGETS:= \
-	clearfog
-
-Build/Exports:=$(Host/Exports)
-
-define Build/Configure
-	# enable additional options beyond clearfog_defconfig
-	echo CONFIG_NET_RANDOM_ETHADDR=y >> $(PKG_BUILD_DIR)/configs/$(BUILD_VARIANT)_defconfig
-	echo CONFIG_CMD_SETEXPR=y >> $(PKG_BUILD_DIR)/configs/$(BUILD_VARIANT)_defconfig
-
-	+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) $(UBOOT_CONFIGURE_VARS) $(UBOOT_CONFIG)_config
-endef
-
-define Build/InstallDev
-	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
-	$(CP) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot-spl.kwb
-endef
-
-$(eval $(call BuildPackage/U-Boot))

package/boot/uboot-mvebu/patches/210-link-libcrypto-static.patch

@@ -1,14 +0,0 @@
-libreCMC links the libressl statically against mkimage, make sure all the 
-needed dependencies are added too.
-
---- a/tools/Makefile
-+++ b/tools/Makefile
-@@ -145,7 +145,7 @@ endif
- # MXSImage needs LibSSL
- ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE),)
- HOSTLOADLIBES_mkimage += \
--	$(shell pkg-config --libs libssl libcrypto 2> /dev/null || echo "-lssl -lcrypto")
-+	$(shell pkg-config --libs --static libssl libcrypto 2> /dev/null || echo "-lssl -lpthread -lcrypto")
- 
- # OS X deprecate openssl in favour of CommonCrypto, supress deprecation
- # warnings on those systems

package/boot/uboot-oxnas/Makefile

@@ -1,36 +0,0 @@
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_VERSION:=2014.10
-PKG_RELEASE:=1
-
-PKG_HASH:=d3b132a7a9b3f3182b7aad71c2dfbd4fc15bea83e12c76134eb3ffefc07d1c71
-
-include $(INCLUDE_DIR)/u-boot.mk
-include $(INCLUDE_DIR)/package.mk
-
-define U-Boot/Default
-  BUILD_TARGET:=oxnas
-  BUILD_DEVICES:=Default
-  HIDDEN:=y
-endef
-
-define U-Boot/ox820
-  NAME:=Oxford/PLX NAS7820
-endef
-
-UBOOT_TARGETS:=ox820
-
-define Build/InstallDev
-	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
-	$(CP) $(PKG_BUILD_DIR)/u-boot.bin $(STAGING_DIR_IMAGE)/u-boot.bin
-endef
-
-$(eval $(call BuildPackage/U-Boot))

package/boot/uboot-oxnas/patches/010-capacity-is-unsigned.patch

@@ -1,37 +0,0 @@
-From df9fb90120423c4c55b66a5dc09af23f605a406b Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 1 Dec 2014 21:37:25 +0100
-Subject: [PATCH] disk/part.c: use unsigned format when printing capacity
-To: u-boot@lists.denx.de
-
-Large disks otherwise produce highly unplausible output such as
-        Capacity: 1907729.0 MB = 1863.0 GB (-387938128 x 512)
-
-As supposedly all size-related decimals are unsigned, use unsigned
-format in printf statement, resulting in a correct capacity being
-displayed:
-        Capacity: 1907729.0 MB = 1863.0 GB (3907029168 x 512)
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- disk/part.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/disk/part.c
-+++ b/disk/part.c
-@@ -229,13 +229,13 @@ void dev_print (block_dev_desc_t *dev_de
- 			printf ("            Supports 48-bit addressing\n");
- #endif
- #if defined(CONFIG_SYS_64BIT_LBA)
--		printf ("            Capacity: %ld.%ld MB = %ld.%ld GB (%Ld x %ld)\n",
-+		printf ("            Capacity: %lu.%lu MB = %lu.%lu GB (%Lu x %lu)\n",
- 			mb_quot, mb_rem,
- 			gb_quot, gb_rem,
- 			lba,
- 			dev_desc->blksz);
- #else
--		printf ("            Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\n",
-+		printf ("            Capacity: %lu.%lu MB = %lu.%lu GB (%lu x %lu)\n",
- 			mb_quot, mb_rem,
- 			gb_quot, gb_rem,
- 			(ulong)lba,

package/boot/uboot-oxnas/patches/020-socfpgaimage_portability.patch

@@ -1,52 +0,0 @@
---- a/tools/socfpgaimage.c
-+++ b/tools/socfpgaimage.c
-@@ -74,12 +74,12 @@ static uint16_t hdr_checksum(struct socf
- static void build_header(uint8_t *buf, uint8_t version, uint8_t flags,
- 			 uint16_t length_bytes)
- {
--	header.validation = htole32(VALIDATION_WORD);
-+	header.validation = cpu_to_le32(VALIDATION_WORD);
- 	header.version = version;
- 	header.flags = flags;
--	header.length_u32 = htole16(length_bytes/4);
-+	header.length_u32 = cpu_to_le16(length_bytes/4);
- 	header.zero = 0;
--	header.checksum = htole16(hdr_checksum(&header));
-+	header.checksum = cpu_to_le16(hdr_checksum(&header));
- 
- 	memcpy(buf, &header, sizeof(header));
- }
-@@ -92,12 +92,12 @@ static int verify_header(const uint8_t *
- {
- 	memcpy(&header, buf, sizeof(header));
- 
--	if (le32toh(header.validation) != VALIDATION_WORD)
-+	if (le32_to_cpu(header.validation) != VALIDATION_WORD)
- 		return -1;
--	if (le16toh(header.checksum) != hdr_checksum(&header))
-+	if (le16_to_cpu(header.checksum) != hdr_checksum(&header))
- 		return -1;
- 
--	return le16toh(header.length_u32) * 4;
-+	return le16_to_cpu(header.length_u32) * 4;
- }
- 
- /* Sign the buffer and return the signed buffer size */
-@@ -116,7 +116,7 @@ static int sign_buffer(uint8_t *buf,
- 	/* Calculate and apply the CRC */
- 	calc_crc = ~pbl_crc32(0, (char *)buf, len);
- 
--	*((uint32_t *)(buf + len)) = htole32(calc_crc);
-+	*((uint32_t *)(buf + len)) = cpu_to_le32(calc_crc);
- 
- 	if (!pad_64k)
- 		return len + 4;
-@@ -150,7 +150,7 @@ static int verify_buffer(const uint8_t *
- 
- 	calc_crc = ~pbl_crc32(0, (const char *)buf, len);
- 
--	buf_crc = le32toh(*((uint32_t *)(buf + len)));
-+	buf_crc = le32_to_cpu(*((uint32_t *)(buf + len)));
- 
- 	if (buf_crc != calc_crc) {
- 		fprintf(stderr, "CRC32 does not match (%08x != %08x)\n",

package/boot/uboot-oxnas/patches/150-spl-block.patch

@@ -1,54 +0,0 @@
---- a/common/spl/Makefile
-+++ b/common/spl/Makefile
-@@ -19,4 +19,5 @@ obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc
- obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
- obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
- obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o
-+obj-$(CONFIG_SPL_BLOCK_SUPPORT) += spl_block.o
- endif
---- a/common/spl/spl.c
-+++ b/common/spl/spl.c
-@@ -191,6 +191,14 @@ void board_init_r(gd_t *dummy1, ulong du
- 		spl_spi_load_image();
- 		break;
- #endif
-+#ifdef CONFIG_SPL_BLOCK_SUPPORT
-+	case BOOT_DEVICE_BLOCK:
-+	{
-+		extern void spl_block_load_image(void);
-+		spl_block_load_image();
-+		break;
-+	}
-+#endif
- #ifdef CONFIG_SPL_ETH_SUPPORT
- 	case BOOT_DEVICE_CPGMAC:
- #ifdef CONFIG_SPL_ETH_DEVICE
---- a/common/cmd_nvedit.c
-+++ b/common/cmd_nvedit.c
-@@ -49,6 +49,7 @@ DECLARE_GLOBAL_DATA_PTR;
- 	!defined(CONFIG_ENV_IS_IN_SPI_FLASH)	&& \
- 	!defined(CONFIG_ENV_IS_IN_REMOTE)	&& \
- 	!defined(CONFIG_ENV_IS_IN_UBI)		&& \
-+	!defined(CONFIG_ENV_IS_IN_EXT4)		&& \
- 	!defined(CONFIG_ENV_IS_NOWHERE)
- # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\
- SPI_FLASH|NVRAM|MMC|FAT|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
---- a/common/Makefile
-+++ b/common/Makefile
-@@ -63,6 +63,7 @@ obj-$(CONFIG_ENV_IS_IN_ONENAND) += env_o
- obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
- obj-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
- obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
-+obj-$(CONFIG_ENV_IS_IN_EXT4) += env_ext4.o
- obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
- 
- # command
-@@ -213,6 +214,8 @@ obj-$(CONFIG_UPDATE_TFTP) += update.o
- obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
- obj-$(CONFIG_CMD_DFU) += cmd_dfu.o
- obj-$(CONFIG_CMD_GPT) += cmd_gpt.o
-+else
-+obj-$(CONFIG_SPL_BLOCK_SUPPORT) += cmd_ide.o
- endif
- 
- ifdef CONFIG_SPL_BUILD

package/boot/uboot-oxnas/patches/200-icplus-phy.patch

@@ -1,142 +0,0 @@
-From e719404ee1241af679a51879eaad291bc27e4817 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 2 Dec 2014 14:46:05 +0100
-Subject: [PATCH] net/phy: add back icplus driver
-
-IC+ phy driver was removed due to the lack of users some time ago.
-Add it back, so we can use it.
----
- drivers/net/phy/Makefile |  1 +
- drivers/net/phy/icplus.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++
- drivers/net/phy/phy.c    |  3 ++
- 3 files changed, 84 insertions(+)
- create mode 100644 drivers/net/phy/icplus.c
-
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_ATHEROS) += atheros.o
- obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
- obj-$(CONFIG_PHY_DAVICOM) += davicom.o
- obj-$(CONFIG_PHY_ET1011C) += et1011c.o
-+obj-$(CONFIG_PHY_ICPLUS) += icplus.o
- obj-$(CONFIG_PHY_LXT) += lxt.o
- obj-$(CONFIG_PHY_MARVELL) += marvell.o
- obj-$(CONFIG_PHY_MICREL) += micrel.o
---- /dev/null
-+++ b/drivers/net/phy/icplus.c
-@@ -0,0 +1,93 @@
-+/*
-+ * ICPlus PHY drivers
-+ *
-+ * SPDX-License-Identifier:	GPL-2.0+
-+ *
-+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
-+ */
-+#include <phy.h>
-+
-+/* IP101A/G - IP1001 */
-+#define IP10XX_SPEC_CTRL_STATUS         16      /* Spec. Control Register */
-+#define IP1001_SPEC_CTRL_STATUS_2       20      /* IP1001 Spec. Control Reg 2 */
-+#define IP1001_PHASE_SEL_MASK           3       /* IP1001 RX/TXPHASE_SEL */
-+#define IP1001_APS_ON                   11      /* IP1001 APS Mode  bit */
-+#define IP101A_G_APS_ON                 2       /* IP101A/G APS Mode bit */
-+#define IP101A_G_IRQ_CONF_STATUS        0x11    /* Conf Info IRQ & Status Reg */
-+#define IP101A_G_IRQ_PIN_USED           (1<<15) /* INTR pin used */
-+#define IP101A_G_IRQ_DEFAULT            IP101A_G_IRQ_PIN_USED
-+#define IP1001LF_DRIVE_MASK     (15 << 5)
-+#define IP1001LF_RXCLKDRIVE_HI  (2  << 5)
-+#define IP1001LF_RXDDRIVE_HI    (2  << 7)
-+#define IP1001LF_RXCLKDRIVE_M   (1  << 5)
-+#define IP1001LF_RXDDRIVE_M     (1  << 7)
-+#define IP1001LF_RXCLKDRIVE_L   (0  << 5)
-+#define IP1001LF_RXDDRIVE_L     (0  << 7)
-+#define IP1001LF_RXCLKDRIVE_VL  (3  << 5)
-+#define IP1001LF_RXDDRIVE_VL    (3  << 7)
-+
-+static int ip1001_config(struct phy_device *phydev)
-+{
-+	int c;
-+
-+	/* Enable Auto Power Saving mode */
-+	c = phy_read(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2);
-+	if (c < 0)
-+		return c;
-+	c |= IP1001_APS_ON;
-+	c = phy_write(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2, c);
-+	if (c < 0)
-+		return c;
-+
-+	/* INTR pin used: speed/link/duplex will cause an interrupt */
-+	c = phy_write(phydev, MDIO_DEVAD_NONE, IP101A_G_IRQ_CONF_STATUS,
-+		      IP101A_G_IRQ_DEFAULT);
-+	if (c < 0)
-+		return c;
-+
-+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
-+		/*
-+		 * Additional delay (2ns) used to adjust RX clock phase
-+		 * at RGMII interface
-+		 */
-+		c = phy_read(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS);
-+		if (c < 0)
-+			return c;
-+
-+		c |= IP1001_PHASE_SEL_MASK;
-+		/* adjust digtial drive strength */
-+		c &= ~IP1001LF_DRIVE_MASK;
-+		c |=  IP1001LF_RXCLKDRIVE_M;
-+		c |=  IP1001LF_RXDDRIVE_M;
-+		c = phy_write(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS,
-+			      c);
-+		if (c < 0)
-+			return c;
-+	}
-+
-+	return 0;
-+}
-+
-+static int ip1001_startup(struct phy_device *phydev)
-+{
-+	genphy_update_link(phydev);
-+	genphy_parse_link(phydev);
-+
-+	return 0;
-+}
-+static struct phy_driver IP1001_driver = {
-+	.name = "ICPlus IP1001",
-+	.uid = 0x02430d90,
-+	.mask = 0x0ffffff0,
-+	.features = PHY_GBIT_FEATURES,
-+	.config = &ip1001_config,
-+	.startup = &ip1001_startup,
-+	.shutdown = &genphy_shutdown,
-+};
-+
-+int phy_icplus_init(void)
-+{
-+	phy_register(&IP1001_driver);
-+
-+	return 0;
-+}
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -454,6 +454,9 @@ int phy_init(void)
- #ifdef CONFIG_PHY_ET1011C
- 	phy_et1011c_init();
- #endif
-+#ifdef CONFIG_PHY_ICPLUS
-+	phy_icplus_init();
-+#endif
- #ifdef CONFIG_PHY_LXT
- 	phy_lxt_init();
- #endif
---- a/include/phy.h
-+++ b/include/phy.h
-@@ -225,6 +225,7 @@ int phy_atheros_init(void);
- int phy_broadcom_init(void);
- int phy_davicom_init(void);
- int phy_et1011c_init(void);
-+int phy_icplus_init(void);
- int phy_lxt_init(void);
- int phy_marvell_init(void);
- int phy_micrel_init(void);

package/boot/uboot-oxnas/patches/300-oxnas-target.patch

@@ -1,101 +0,0 @@
---- a/arch/arm/include/asm/mach-types.h
-+++ b/arch/arm/include/asm/mach-types.h
-@@ -212,6 +212,7 @@ extern unsigned int __machine_arch_type;
- #define MACH_TYPE_EDB9307A             1128
- #define MACH_TYPE_OMAP_3430SDP         1138
- #define MACH_TYPE_VSTMS                1140
-+#define MACH_TYPE_OXNAS                1152
- #define MACH_TYPE_MICRO9M              1169
- #define MACH_TYPE_BUG                  1179
- #define MACH_TYPE_AT91SAM9263EK        1202
---- a/drivers/block/Makefile
-+++ b/drivers/block/Makefile
-@@ -21,3 +21,4 @@ obj-$(CONFIG_IDE_SIL680) += sil680.o
- obj-$(CONFIG_SANDBOX) += sandbox.o
- obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
- obj-$(CONFIG_SYSTEMACE) += systemace.o
-+obj-$(CONFIG_IDE_PLX) += plxsata_ide.o
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -33,6 +33,7 @@ obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
- obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
- obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
- obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
-+obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o
- obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
- obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
- obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
---- a/tools/.gitignore
-+++ b/tools/.gitignore
-@@ -9,6 +9,7 @@
- /mkenvimage
- /mkimage
- /mkexynosspl
-+/mkox820crc
- /mpc86x_clk
- /mxsboot
- /mksunxiboot
---- a/tools/Makefile
-+++ b/tools/Makefile
-@@ -143,6 +143,12 @@ hostprogs-$(CONFIG_KIRKWOOD) += kwboot
- hostprogs-y += proftool
- hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela
- 
-+
-+hostprogs-$(CONFIG_OX820) += mkox820crc$(SFX)
-+
-+mkox820crc$(SFX)-objs := mkox820crc.o lib/crc32.o
-+
-+
- # We build some files with extra pedantic flags to try to minimize things
- # that won't build on some weird host compiler -- though there are lots of
- # exceptions for files that aren't complaint.
---- a/drivers/serial/ns16550.c
-+++ b/drivers/serial/ns16550.c
-@@ -118,6 +118,14 @@ int ns16550_calc_divisor(NS16550_t port,
- 	}
- 	port->osc_12m_sel = 0;			/* clear if previsouly set */
- #endif
-+#ifdef CONFIG_OX820
-+	{
-+		/* with additional 3 bit fractional */
-+		u32 div = (CONFIG_SYS_NS16550_CLK + baudrate) / (baudrate * 2);
-+		port->reg9 = (div & 7) << 5;
-+		return (div >> 3);
-+	}
-+#endif
- 
- 	return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
- }
---- a/scripts/Makefile.spl
-+++ b/scripts/Makefile.spl
-@@ -202,6 +202,9 @@ OBJCOPYFLAGS_$(SPL_BIN).bin = $(SPL_OBJC
- 
- $(obj)/$(SPL_BIN).bin: $(obj)/$(SPL_BIN) FORCE
- 	$(call if_changed,objcopy)
-+ifdef CONFIG_OX820
-+	$(OBJTREE)/tools/mkox820crc $@
-+endif
- 
- LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
- ifneq ($(CONFIG_SPL_TEXT_BASE),)
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -488,6 +488,9 @@ config TARGET_BALLOON3
- config TARGET_H2200
- 	bool "Support h2200"
- 
-+config TARGET_OX820
-+	bool "Support ox820"
-+
- config TARGET_PALMLD
- 	bool "Support palmld"
- 
-@@ -650,6 +653,7 @@ source "board/logicpd/imx27lite/Kconfig"
- source "board/logicpd/imx31_litekit/Kconfig"
- source "board/mpl/vcma9/Kconfig"
- source "board/olimex/mx23_olinuxino/Kconfig"
-+source "board/ox820/Kconfig"
- source "board/palmld/Kconfig"
- source "board/palmtc/Kconfig"
- source "board/palmtreo680/Kconfig"

package/boot/uboot-oxnas/patches/400-gcc-5-compiler.patch

@@ -1,87 +0,0 @@
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 7 Feb 2015 21:52:40 +0000 (+0100)
-Subject: Add linux/compiler-gcc5.h to fix builds with gcc5
-X-Git-Tag: v2015.04-rc2~31
-X-Git-Url: http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=478b02f1a7043b673565075ea5016376f3293b23
-
-Add linux/compiler-gcc5.h to fix builds with gcc5
-
-Add linux/compiler-gcc5/h from the kernel sources at:
-
-commit 5631b8fba640a4ab2f8a954f63a603fa34eda96b
-Author: Steven Noonan <steven@uplinklabs.net>
-Date:   Sat Oct 25 15:09:42 2014 -0700
-
-    compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
-
---- /dev/null
-+++ b/include/linux/compiler-gcc5.h
-@@ -0,0 +1,65 @@
-+#ifndef __LINUX_COMPILER_H
-+#error "Please don't include <linux/compiler-gcc5.h> directly, include <linux/compiler.h> instead."
-+#endif
-+
-+#define __used				__attribute__((__used__))
-+#define __must_check			__attribute__((warn_unused_result))
-+#define __compiler_offsetof(a, b)	__builtin_offsetof(a, b)
-+
-+/* Mark functions as cold. gcc will assume any path leading to a call
-+   to them will be unlikely.  This means a lot of manual unlikely()s
-+   are unnecessary now for any paths leading to the usual suspects
-+   like BUG(), printk(), panic() etc. [but let's keep them for now for
-+   older compilers]
-+
-+   Early snapshots of gcc 4.3 don't support this and we can't detect this
-+   in the preprocessor, but we can live with this because they're unreleased.
-+   Maketime probing would be overkill here.
-+
-+   gcc also has a __attribute__((__hot__)) to move hot functions into
-+   a special section, but I don't see any sense in this right now in
-+   the kernel context */
-+#define __cold			__attribute__((__cold__))
-+
-+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
-+
-+#ifndef __CHECKER__
-+# define __compiletime_warning(message) __attribute__((warning(message)))
-+# define __compiletime_error(message) __attribute__((error(message)))
-+#endif /* __CHECKER__ */
-+
-+/*
-+ * Mark a position in code as unreachable.  This can be used to
-+ * suppress control flow warnings after asm blocks that transfer
-+ * control elsewhere.
-+ *
-+ * Early snapshots of gcc 4.5 don't support this and we can't detect
-+ * this in the preprocessor, but we can live with this because they're
-+ * unreleased.  Really, we need to have autoconf for the kernel.
-+ */
-+#define unreachable() __builtin_unreachable()
-+
-+/* Mark a function definition as prohibited from being cloned. */
-+#define __noclone	__attribute__((__noclone__))
-+
-+/*
-+ * Tell the optimizer that something else uses this function or variable.
-+ */
-+#define __visible __attribute__((externally_visible))
-+
-+/*
-+ * GCC 'asm goto' miscompiles certain code sequences:
-+ *
-+ *   http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
-+ *
-+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
-+ *
-+ * (asm goto is automatically volatile - the naming reflects this.)
-+ */
-+#define asm_volatile_goto(x...)	do { asm goto(x); asm (""); } while (0)
-+
-+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
-+#define __HAVE_BUILTIN_BSWAP32__
-+#define __HAVE_BUILTIN_BSWAP64__
-+#define __HAVE_BUILTIN_BSWAP16__
-+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */

package/boot/uboot-oxnas/patches/410-gcc-6-compiler.patch

@@ -1,306 +0,0 @@
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 7 Feb 2015 21:52:40 +0000 (+0100)
-Subject: Add linux/compiler-gcc6.h to fix builds with gcc6
-X-Git-Tag: v2015.04-rc2~31
-X-Git-Url: http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=478b02f1a7043b673565075ea5016376f3293b23
-
-Add linux/compiler-gcc6.h to fix builds with gcc6
-
-Add linux/compiler-gcc6/h from the kernel sources at:
-
-commit 5631b8fba640a4ab2f8a954f63a603fa34eda96b
-Author: Steven Noonan <steven@uplinklabs.net>
-Date:   Sat Oct 25 15:09:42 2014 -0700
-
-    compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
-
---- /dev/null
-+++ b/include/linux/compiler-gcc6.h
-@@ -0,0 +1,284 @@
-+#ifndef __LINUX_COMPILER_H
-+#error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead."
-+#endif
-+
-+/*
-+ * Common definitions for all gcc versions go here.
-+ */
-+#define GCC_VERSION (__GNUC__ * 10000		\
-+		     + __GNUC_MINOR__ * 100	\
-+		     + __GNUC_PATCHLEVEL__)
-+
-+/* Optimization barrier */
-+
-+/* The "volatile" is due to gcc bugs */
-+#define barrier() __asm__ __volatile__("": : :"memory")
-+/*
-+ * This version is i.e. to prevent dead stores elimination on @ptr
-+ * where gcc and llvm may behave differently when otherwise using
-+ * normal barrier(): while gcc behavior gets along with a normal
-+ * barrier(), llvm needs an explicit input variable to be assumed
-+ * clobbered. The issue is as follows: while the inline asm might
-+ * access any memory it wants, the compiler could have fit all of
-+ * @ptr into memory registers instead, and since @ptr never escaped
-+ * from that, it proofed that the inline asm wasn't touching any of
-+ * it. This version works well with both compilers, i.e. we're telling
-+ * the compiler that the inline asm absolutely may see the contents
-+ * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495
-+ */
-+#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory")
-+
-+/*
-+ * This macro obfuscates arithmetic on a variable address so that gcc
-+ * shouldn't recognize the original var, and make assumptions about it.
-+ *
-+ * This is needed because the C standard makes it undefined to do
-+ * pointer arithmetic on "objects" outside their boundaries and the
-+ * gcc optimizers assume this is the case. In particular they
-+ * assume such arithmetic does not wrap.
-+ *
-+ * A miscompilation has been observed because of this on PPC.
-+ * To work around it we hide the relationship of the pointer and the object
-+ * using this macro.
-+ *
-+ * Versions of the ppc64 compiler before 4.1 had a bug where use of
-+ * RELOC_HIDE could trash r30. The bug can be worked around by changing
-+ * the inline assembly constraint from =g to =r, in this particular
-+ * case either is valid.
-+ */
-+#define RELOC_HIDE(ptr, off)						\
-+({									\
-+	unsigned long __ptr;						\
-+	__asm__ ("" : "=r"(__ptr) : "0"(ptr));				\
-+	(typeof(ptr)) (__ptr + (off));					\
-+})
-+
-+/* Make the optimizer believe the variable can be manipulated arbitrarily. */
-+#define OPTIMIZER_HIDE_VAR(var)						\
-+	__asm__ ("" : "=r" (var) : "0" (var))
-+
-+#ifdef __CHECKER__
-+#define __must_be_array(a)	0
-+#else
-+/* &a[0] degrades to a pointer: a different type from an array */
-+#define __must_be_array(a)	BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
-+#endif
-+
-+/*
-+ * Force always-inline if the user requests it so via the .config,
-+ * or if gcc is too old:
-+ */
-+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) ||		\
-+    !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
-+#define inline		inline		__attribute__((always_inline)) notrace
-+#define __inline__	__inline__	__attribute__((always_inline)) notrace
-+#define __inline	__inline	__attribute__((always_inline)) notrace
-+#else
-+/* A lot of inline functions can cause havoc with function tracing */
-+#define inline		inline		notrace
-+#define __inline__	__inline__	notrace
-+#define __inline	__inline	notrace
-+#endif
-+
-+#define __always_inline	inline __attribute__((always_inline))
-+#define  noinline	__attribute__((noinline))
-+
-+#define __deprecated	__attribute__((deprecated))
-+#define __packed	__attribute__((packed))
-+#define __weak		__attribute__((weak))
-+#define __alias(symbol)	__attribute__((alias(#symbol)))
-+
-+/*
-+ * it doesn't make sense on ARM (currently the only user of __naked)
-+ * to trace naked functions because then mcount is called without
-+ * stack and frame pointer being set up and there is no chance to
-+ * restore the lr register to the value before mcount was called.
-+ *
-+ * The asm() bodies of naked functions often depend on standard calling
-+ * conventions, therefore they must be noinline and noclone.
-+ *
-+ * GCC 4.[56] currently fail to enforce this, so we must do so ourselves.
-+ * See GCC PR44290.
-+ */
-+#define __naked		__attribute__((naked)) noinline __noclone notrace
-+
-+#define __noreturn	__attribute__((noreturn))
-+
-+/*
-+ * From the GCC manual:
-+ *
-+ * Many functions have no effects except the return value and their
-+ * return value depends only on the parameters and/or global
-+ * variables.  Such a function can be subject to common subexpression
-+ * elimination and loop optimization just as an arithmetic operator
-+ * would be.
-+ * [...]
-+ */
-+#define __pure			__attribute__((pure))
-+#define __aligned(x)		__attribute__((aligned(x)))
-+#define __printf(a, b)		__attribute__((format(printf, a, b)))
-+#define __scanf(a, b)		__attribute__((format(scanf, a, b)))
-+#define __attribute_const__	__attribute__((__const__))
-+#define __maybe_unused		__attribute__((unused))
-+#define __always_unused		__attribute__((unused))
-+
-+/* gcc version specific checks */
-+
-+#if GCC_VERSION < 30200
-+# error Sorry, your compiler is too old - please upgrade it.
-+#endif
-+
-+#if GCC_VERSION < 30300
-+# define __used			__attribute__((__unused__))
-+#else
-+# define __used			__attribute__((__used__))
-+#endif
-+
-+#ifdef CONFIG_GCOV_KERNEL
-+# if GCC_VERSION < 30400
-+#   error "GCOV profiling support for gcc versions below 3.4 not included"
-+# endif /* __GNUC_MINOR__ */
-+#endif /* CONFIG_GCOV_KERNEL */
-+
-+#if GCC_VERSION >= 30400
-+#define __must_check		__attribute__((warn_unused_result))
-+#define __malloc		__attribute__((__malloc__))
-+#endif
-+
-+#if GCC_VERSION >= 40000
-+
-+/* GCC 4.1.[01] miscompiles __weak */
-+#ifdef __KERNEL__
-+# if GCC_VERSION >= 40100 &&  GCC_VERSION <= 40101
-+#  error Your version of gcc miscompiles the __weak directive
-+# endif
-+#endif
-+
-+#define __used			__attribute__((__used__))
-+#define __compiler_offsetof(a, b)					\
-+	__builtin_offsetof(a, b)
-+
-+#if GCC_VERSION >= 40100 && GCC_VERSION < 40600
-+# define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
-+#endif
-+
-+#if GCC_VERSION >= 40300
-+/* Mark functions as cold. gcc will assume any path leading to a call
-+ * to them will be unlikely.  This means a lot of manual unlikely()s
-+ * are unnecessary now for any paths leading to the usual suspects
-+ * like BUG(), printk(), panic() etc. [but let's keep them for now for
-+ * older compilers]
-+ *
-+ * Early snapshots of gcc 4.3 don't support this and we can't detect this
-+ * in the preprocessor, but we can live with this because they're unreleased.
-+ * Maketime probing would be overkill here.
-+ *
-+ * gcc also has a __attribute__((__hot__)) to move hot functions into
-+ * a special section, but I don't see any sense in this right now in
-+ * the kernel context
-+ */
-+#define __cold			__attribute__((__cold__))
-+
-+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
-+
-+#ifndef __CHECKER__
-+# define __compiletime_warning(message) __attribute__((warning(message)))
-+# define __compiletime_error(message) __attribute__((error(message)))
-+#endif /* __CHECKER__ */
-+#endif /* GCC_VERSION >= 40300 */
-+
-+#if GCC_VERSION >= 40500
-+/*
-+ * Mark a position in code as unreachable.  This can be used to
-+ * suppress control flow warnings after asm blocks that transfer
-+ * control elsewhere.
-+ *
-+ * Early snapshots of gcc 4.5 don't support this and we can't detect
-+ * this in the preprocessor, but we can live with this because they're
-+ * unreleased.  Really, we need to have autoconf for the kernel.
-+ */
-+#define unreachable() __builtin_unreachable()
-+
-+/* Mark a function definition as prohibited from being cloned. */
-+#define __noclone	__attribute__((__noclone__, __optimize__("no-tracer")))
-+
-+#endif /* GCC_VERSION >= 40500 */
-+
-+#if GCC_VERSION >= 40600
-+/*
-+ * When used with Link Time Optimization, gcc can optimize away C functions or
-+ * variables which are referenced only from assembly code.  __visible tells the
-+ * optimizer that something else uses this function or variable, thus preventing
-+ * this.
-+ */
-+#define __visible	__attribute__((externally_visible))
-+#endif
-+
-+
-+#if GCC_VERSION >= 40900 && !defined(__CHECKER__)
-+/*
-+ * __assume_aligned(n, k): Tell the optimizer that the returned
-+ * pointer can be assumed to be k modulo n. The second argument is
-+ * optional (default 0), so we use a variadic macro to make the
-+ * shorthand.
-+ *
-+ * Beware: Do not apply this to functions which may return
-+ * ERR_PTRs. Also, it is probably unwise to apply it to functions
-+ * returning extra information in the low bits (but in that case the
-+ * compiler should see some alignment anyway, when the return value is
-+ * massaged by 'flags = ptr & 3; ptr &= ~3;').
-+ */
-+#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))
-+#endif
-+
-+/*
-+ * GCC 'asm goto' miscompiles certain code sequences:
-+ *
-+ *   http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
-+ *
-+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
-+ *
-+ * (asm goto is automatically volatile - the naming reflects this.)
-+ */
-+#define asm_volatile_goto(x...)	do { asm goto(x); asm (""); } while (0)
-+
-+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
-+#if GCC_VERSION >= 40400
-+#define __HAVE_BUILTIN_BSWAP32__
-+#define __HAVE_BUILTIN_BSWAP64__
-+#endif
-+#if GCC_VERSION >= 40800
-+#define __HAVE_BUILTIN_BSWAP16__
-+#endif
-+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
-+
-+#if GCC_VERSION >= 50000
-+#define KASAN_ABI_VERSION 4
-+#elif GCC_VERSION >= 40902
-+#define KASAN_ABI_VERSION 3
-+#endif
-+
-+#if GCC_VERSION >= 40902
-+/*
-+ * Tell the compiler that address safety instrumentation (KASAN)
-+ * should not be applied to that function.
-+ * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
-+ */
-+#define __no_sanitize_address __attribute__((no_sanitize_address))
-+#endif
-+
-+#endif	/* gcc version >= 40000 specific checks */
-+
-+#if !defined(__noclone)
-+#define __noclone	/* not needed */
-+#endif
-+
-+#if !defined(__no_sanitize_address)
-+#define __no_sanitize_address
-+#endif
-+
-+/*
-+ * A trick to suppress uninitialized variable warning without generating any
-+ * code
-+ */
-+#define uninitialized_var(x) x = x

package/boot/uboot-oxnas/patches/420-gcc-7-compiler.patch

@@ -1,287 +0,0 @@
---- /dev/null
-+++ b/include/linux/compiler-gcc7.h
-@@ -0,0 +1,284 @@
-+#ifndef __LINUX_COMPILER_H
-+#error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead."
-+#endif
-+
-+/*
-+ * Common definitions for all gcc versions go here.
-+ */
-+#define GCC_VERSION (__GNUC__ * 10000		\
-+		     + __GNUC_MINOR__ * 100	\
-+		     + __GNUC_PATCHLEVEL__)
-+
-+/* Optimization barrier */
-+
-+/* The "volatile" is due to gcc bugs */
-+#define barrier() __asm__ __volatile__("": : :"memory")
-+/*
-+ * This version is i.e. to prevent dead stores elimination on @ptr
-+ * where gcc and llvm may behave differently when otherwise using
-+ * normal barrier(): while gcc behavior gets along with a normal
-+ * barrier(), llvm needs an explicit input variable to be assumed
-+ * clobbered. The issue is as follows: while the inline asm might
-+ * access any memory it wants, the compiler could have fit all of
-+ * @ptr into memory registers instead, and since @ptr never escaped
-+ * from that, it proofed that the inline asm wasn't touching any of
-+ * it. This version works well with both compilers, i.e. we're telling
-+ * the compiler that the inline asm absolutely may see the contents
-+ * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495
-+ */
-+#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory")
-+
-+/*
-+ * This macro obfuscates arithmetic on a variable address so that gcc
-+ * shouldn't recognize the original var, and make assumptions about it.
-+ *
-+ * This is needed because the C standard makes it undefined to do
-+ * pointer arithmetic on "objects" outside their boundaries and the
-+ * gcc optimizers assume this is the case. In particular they
-+ * assume such arithmetic does not wrap.
-+ *
-+ * A miscompilation has been observed because of this on PPC.
-+ * To work around it we hide the relationship of the pointer and the object
-+ * using this macro.
-+ *
-+ * Versions of the ppc64 compiler before 4.1 had a bug where use of
-+ * RELOC_HIDE could trash r30. The bug can be worked around by changing
-+ * the inline assembly constraint from =g to =r, in this particular
-+ * case either is valid.
-+ */
-+#define RELOC_HIDE(ptr, off)						\
-+({									\
-+	unsigned long __ptr;						\
-+	__asm__ ("" : "=r"(__ptr) : "0"(ptr));				\
-+	(typeof(ptr)) (__ptr + (off));					\
-+})
-+
-+/* Make the optimizer believe the variable can be manipulated arbitrarily. */
-+#define OPTIMIZER_HIDE_VAR(var)						\
-+	__asm__ ("" : "=r" (var) : "0" (var))
-+
-+#ifdef __CHECKER__
-+#define __must_be_array(a)	0
-+#else
-+/* &a[0] degrades to a pointer: a different type from an array */
-+#define __must_be_array(a)	BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
-+#endif
-+
-+/*
-+ * Force always-inline if the user requests it so via the .config,
-+ * or if gcc is too old:
-+ */
-+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) ||		\
-+    !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
-+#define inline		inline		__attribute__((always_inline)) notrace
-+#define __inline__	__inline__	__attribute__((always_inline)) notrace
-+#define __inline	__inline	__attribute__((always_inline)) notrace
-+#else
-+/* A lot of inline functions can cause havoc with function tracing */
-+#define inline		inline		notrace
-+#define __inline__	__inline__	notrace
-+#define __inline	__inline	notrace
-+#endif
-+
-+#define __always_inline	inline __attribute__((always_inline))
-+#define  noinline	__attribute__((noinline))
-+
-+#define __deprecated	__attribute__((deprecated))
-+#define __packed	__attribute__((packed))
-+#define __weak		__attribute__((weak))
-+#define __alias(symbol)	__attribute__((alias(#symbol)))
-+
-+/*
-+ * it doesn't make sense on ARM (currently the only user of __naked)
-+ * to trace naked functions because then mcount is called without
-+ * stack and frame pointer being set up and there is no chance to
-+ * restore the lr register to the value before mcount was called.
-+ *
-+ * The asm() bodies of naked functions often depend on standard calling
-+ * conventions, therefore they must be noinline and noclone.
-+ *
-+ * GCC 4.[56] currently fail to enforce this, so we must do so ourselves.
-+ * See GCC PR44290.
-+ */
-+#define __naked		__attribute__((naked)) noinline __noclone notrace
-+
-+#define __noreturn	__attribute__((noreturn))
-+
-+/*
-+ * From the GCC manual:
-+ *
-+ * Many functions have no effects except the return value and their
-+ * return value depends only on the parameters and/or global
-+ * variables.  Such a function can be subject to common subexpression
-+ * elimination and loop optimization just as an arithmetic operator
-+ * would be.
-+ * [...]
-+ */
-+#define __pure			__attribute__((pure))
-+#define __aligned(x)		__attribute__((aligned(x)))
-+#define __printf(a, b)		__attribute__((format(printf, a, b)))
-+#define __scanf(a, b)		__attribute__((format(scanf, a, b)))
-+#define __attribute_const__	__attribute__((__const__))
-+#define __maybe_unused		__attribute__((unused))
-+#define __always_unused		__attribute__((unused))
-+
-+/* gcc version specific checks */
-+
-+#if GCC_VERSION < 30200
-+# error Sorry, your compiler is too old - please upgrade it.
-+#endif
-+
-+#if GCC_VERSION < 30300
-+# define __used			__attribute__((__unused__))
-+#else
-+# define __used			__attribute__((__used__))
-+#endif
-+
-+#ifdef CONFIG_GCOV_KERNEL
-+# if GCC_VERSION < 30400
-+#   error "GCOV profiling support for gcc versions below 3.4 not included"
-+# endif /* __GNUC_MINOR__ */
-+#endif /* CONFIG_GCOV_KERNEL */
-+
-+#if GCC_VERSION >= 30400
-+#define __must_check		__attribute__((warn_unused_result))
-+#define __malloc		__attribute__((__malloc__))
-+#endif
-+
-+#if GCC_VERSION >= 40000
-+
-+/* GCC 4.1.[01] miscompiles __weak */
-+#ifdef __KERNEL__
-+# if GCC_VERSION >= 40100 &&  GCC_VERSION <= 40101
-+#  error Your version of gcc miscompiles the __weak directive
-+# endif
-+#endif
-+
-+#define __used			__attribute__((__used__))
-+#define __compiler_offsetof(a, b)					\
-+	__builtin_offsetof(a, b)
-+
-+#if GCC_VERSION >= 40100 && GCC_VERSION < 40600
-+# define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
-+#endif
-+
-+#if GCC_VERSION >= 40300
-+/* Mark functions as cold. gcc will assume any path leading to a call
-+ * to them will be unlikely.  This means a lot of manual unlikely()s
-+ * are unnecessary now for any paths leading to the usual suspects
-+ * like BUG(), printk(), panic() etc. [but let's keep them for now for
-+ * older compilers]
-+ *
-+ * Early snapshots of gcc 4.3 don't support this and we can't detect this
-+ * in the preprocessor, but we can live with this because they're unreleased.
-+ * Maketime probing would be overkill here.
-+ *
-+ * gcc also has a __attribute__((__hot__)) to move hot functions into
-+ * a special section, but I don't see any sense in this right now in
-+ * the kernel context
-+ */
-+#define __cold			__attribute__((__cold__))
-+
-+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
-+
-+#ifndef __CHECKER__
-+# define __compiletime_warning(message) __attribute__((warning(message)))
-+# define __compiletime_error(message) __attribute__((error(message)))
-+#endif /* __CHECKER__ */
-+#endif /* GCC_VERSION >= 40300 */
-+
-+#if GCC_VERSION >= 40500
-+/*
-+ * Mark a position in code as unreachable.  This can be used to
-+ * suppress control flow warnings after asm blocks that transfer
-+ * control elsewhere.
-+ *
-+ * Early snapshots of gcc 4.5 don't support this and we can't detect
-+ * this in the preprocessor, but we can live with this because they're
-+ * unreleased.  Really, we need to have autoconf for the kernel.
-+ */
-+#define unreachable() __builtin_unreachable()
-+
-+/* Mark a function definition as prohibited from being cloned. */
-+#define __noclone	__attribute__((__noclone__, __optimize__("no-tracer")))
-+
-+#endif /* GCC_VERSION >= 40500 */
-+
-+#if GCC_VERSION >= 40600
-+/*
-+ * When used with Link Time Optimization, gcc can optimize away C functions or
-+ * variables which are referenced only from assembly code.  __visible tells the
-+ * optimizer that something else uses this function or variable, thus preventing
-+ * this.
-+ */
-+#define __visible	__attribute__((externally_visible))
-+#endif
-+
-+
-+#if GCC_VERSION >= 40900 && !defined(__CHECKER__)
-+/*
-+ * __assume_aligned(n, k): Tell the optimizer that the returned
-+ * pointer can be assumed to be k modulo n. The second argument is
-+ * optional (default 0), so we use a variadic macro to make the
-+ * shorthand.
-+ *
-+ * Beware: Do not apply this to functions which may return
-+ * ERR_PTRs. Also, it is probably unwise to apply it to functions
-+ * returning extra information in the low bits (but in that case the
-+ * compiler should see some alignment anyway, when the return value is
-+ * massaged by 'flags = ptr & 3; ptr &= ~3;').
-+ */
-+#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))
-+#endif
-+
-+/*
-+ * GCC 'asm goto' miscompiles certain code sequences:
-+ *
-+ *   http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
-+ *
-+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
-+ *
-+ * (asm goto is automatically volatile - the naming reflects this.)
-+ */
-+#define asm_volatile_goto(x...)	do { asm goto(x); asm (""); } while (0)
-+
-+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
-+#if GCC_VERSION >= 40400
-+#define __HAVE_BUILTIN_BSWAP32__
-+#define __HAVE_BUILTIN_BSWAP64__
-+#endif
-+#if GCC_VERSION >= 40800
-+#define __HAVE_BUILTIN_BSWAP16__
-+#endif
-+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
-+
-+#if GCC_VERSION >= 50000
-+#define KASAN_ABI_VERSION 4
-+#elif GCC_VERSION >= 40902
-+#define KASAN_ABI_VERSION 3
-+#endif
-+
-+#if GCC_VERSION >= 40902
-+/*
-+ * Tell the compiler that address safety instrumentation (KASAN)
-+ * should not be applied to that function.
-+ * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
-+ */
-+#define __no_sanitize_address __attribute__((no_sanitize_address))
-+#endif
-+
-+#endif	/* gcc version >= 40000 specific checks */
-+
-+#if !defined(__noclone)
-+#define __noclone	/* not needed */
-+#endif
-+
-+#if !defined(__no_sanitize_address)
-+#define __no_sanitize_address
-+#endif
-+
-+/*
-+ * A trick to suppress uninitialized variable warning without generating any
-+ * code
-+ */
-+#define uninitialized_var(x) x = x

package/boot/uboot-oxnas/patches/800-fix-bootm-assertion.patch

@@ -1,11 +0,0 @@
---- a/common/cmd_bootm.c
-+++ b/common/cmd_bootm.c
-@@ -77,7 +77,7 @@ static int do_bootm_subcommand(cmd_tbl_t
- 		return CMD_RET_USAGE;
- 	}
- 
--	if (state != BOOTM_STATE_START && images.state >= state) {
-+	if (!(state & BOOTM_STATE_START) && images.state >= state) {
- 		printf("Trying to execute a command out of order\n");
- 		return CMD_RET_USAGE;
- 	}

package/boot/uboot-oxnas/src/arch/arm/cpu/arm1136/nas782x/Makefile

@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= reset.o
-obj-y	+= timer.o
-obj-y	+= clock.o
-obj-y	+= pinmux.o

package/boot/uboot-oxnas/src/arch/arm/cpu/arm1136/nas782x/clock.c

@@ -1,97 +0,0 @@
-#include <common.h>
-#include <asm/arch/sysctl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-
-typedef struct {
-	unsigned short mhz;
-	unsigned char refdiv;
-	unsigned char outdiv;
-	unsigned int fbdiv;
-	unsigned short bwadj;
-	unsigned short sfreq;
-	unsigned int sslope;
-} PLL_CONFIG;
-
-const PLL_CONFIG C_PLL_CONFIG[] = {
-	{ 500, 1, 2, 3932160, 119, 208, 189 }, //  500 MHz
-	{ 525, 2, 1, 4128768, 125, 139, 297 }, //  525 MHz
-	{ 550, 2, 1, 4325376, 131, 139, 311 }, //  550 MHz
-	{ 575, 2, 1, 4521984, 137, 139, 326 }, //  575 MHz
-	{ 600, 2, 1, 4718592, 143, 138, 339 }, //  600 MHz
-	{ 625, 1, 1, 3276800, 99, 208, 157 }, //  625 MHz
-	{ 650, 1, 1, 3407872, 103, 208, 164 }, //  650 MHz
-	{ 675, 1, 1, 3538944, 107, 208, 170 }, //  675 MHz
-	{ 700, 0, 0, 917504, 27, 416, 22 }, //  700 MHz
-	{ 725, 1, 1, 3801088, 115, 208, 182 }, //  725 MHz
-	{ 750, 0, 0, 983040, 29, 416, 23 }, //  750 MHz
-	{ 775, 3, 0, 4063232, 123, 104, 390 }, //  775 MHz
-	{ 800, 3, 0, 4194304, 127, 104, 403 }, //  800 MHz
-	{ 825, 3, 0, 4325376, 131, 104, 415 }, //  825 MHz
-	{ 850, 2, 0, 3342336, 101, 139, 241 }, //  850 MHz
-	{ 875, 2, 0, 3440640, 104, 139, 248 }, //  875 MHz
-	{ 900, 2, 0, 3538944, 107, 139, 255 }, //  900 MHz
-	{ 925, 2, 0, 3637248, 110, 139, 262 }, //  925 MHz
-	{ 950, 2, 0, 3735552, 113, 139, 269 }, //  950 MHz
-	{ 975, 2, 0, 3833856, 116, 139, 276 }, //  975 MHz
-	{ 1000, 2, 0, 3932160, 119, 139, 283 }, // 1000 MHz
-};
-
-#define PLL_BYPASS (1<<1)
-#define SAT_ENABLE (1<<3)
-
-#define PLL_OUTDIV_SHIFT	4
-#define PLL_REFDIV_SHIFT	8
-#define PLL_BWADJ_SHIFT		16
-
-#define PLL_LOW_FREQ	500
-#define PLL_FREQ_STEP	25
-static void plla_configure(int outdiv, int refdiv, int fbdiv, int bwadj,
-                           int sfreq, int sslope)
-{
-	setbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS);
-	udelay(10);
-	reset_block(SYS_CTRL_RST_PLLA, 1);
-	udelay(10);
-
-	writel((refdiv << PLL_REFDIV_SHIFT) | (outdiv << PLL_OUTDIV_SHIFT) |
-	       SAT_ENABLE | PLL_BYPASS,
-	       SYS_CTRL_PLLA_CTRL0);
-
-	writel(fbdiv, SYS_CTRL_PLLA_CTRL1);
-	writel((bwadj << PLL_BWADJ_SHIFT) | sfreq, SYS_CTRL_PLLA_CTRL2);
-	writel(sslope, SYS_CTRL_PLLA_CTRL3);
-
-	udelay(10); // 5us delay required (from TCI datasheet), use 10us
-
-	reset_block(SYS_CTRL_RST_PLLA, 0);
-
-	udelay(100); // Delay for PLL to lock
-
-	printf("  plla_ctrl0 : %08x\n", readl(SYS_CTRL_PLLA_CTRL0));
-	printf("  plla_ctrl1 : %08x\n", readl(SYS_CTRL_PLLA_CTRL1));
-	printf("  plla_ctrl2 : %08x\n", readl(SYS_CTRL_PLLA_CTRL2));
-	printf("  plla_ctrl3 : %08x\n", readl(SYS_CTRL_PLLA_CTRL3));
-
-	clrbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS); // Take PLL out of bypass
-	puts("\nPLLA Set\n");
-}
-
-int plla_set_config(int mhz)
-{
-	int index = (mhz - PLL_LOW_FREQ) / PLL_FREQ_STEP;
-	const PLL_CONFIG *cfg;
-
-	if (index < 0 || index > ARRAY_SIZE(C_PLL_CONFIG)) {
-		debug("Freq %d MHz out of range, default to lowest\n", mhz);
-		index = 0;
-	}
-	cfg = &C_PLL_CONFIG[index];
-
-	printf("Attempting to set PLLA to %d MHz ...\n", (unsigned) cfg->mhz);
-	plla_configure(cfg->outdiv, cfg->refdiv, cfg->fbdiv, cfg->bwadj,
-	               cfg->sfreq, cfg->sslope);
-
-	return cfg->mhz;
-}
-

package/boot/uboot-oxnas/src/arch/arm/cpu/arm1136/nas782x/pinmux.c

@@ -1,43 +0,0 @@
-#include <common.h>
-#include <asm/arch/pinmux.h>
-
-void pinmux_set(int bank, int pin, int func)
-{
-	u32 reg;
-	u32 base;
-	/* TODO: check parameters */
-
-	if (bank == PINMUX_BANK_MFA)
-		base = SYS_CONTROL_BASE;
-	else
-		base = SEC_CONTROL_BASE;
-
-	clrbits_le32(base + PINMUX_SECONDARY_SEL, BIT(pin));
-	clrbits_le32(base + PINMUX_TERTIARY_SEL, BIT(pin));
-	clrbits_le32(base + PINMUX_QUATERNARY_SEL, BIT(pin));
-	clrbits_le32(base + PINMUX_DEBUG_SEL, BIT(pin));
-	clrbits_le32(base + PINMUX_ALTERNATIVE_SEL, BIT(pin));
-
-	switch (func) {
-	case PINMUX_GPIO:
-	default:
-		return;
-		break;
-	case PINMUX_2:
-		reg = base + PINMUX_SECONDARY_SEL;
-		break;
-	case PINMUX_3:
-		reg = base + PINMUX_TERTIARY_SEL;
-		break;
-	case PINMUX_4:
-		reg = base + PINMUX_QUATERNARY_SEL;
-		break;
-	case PINMUX_DEBUG:
-		reg = base + PINMUX_DEBUG_SEL;
-		break;
-	case PINMUX_ALT:
-		reg = base + PINMUX_ALTERNATIVE_SEL;
-		break;
-	}
-	setbits_le32(reg, BIT(pin));
-}

package/boot/uboot-oxnas/src/arch/arm/cpu/arm1136/nas782x/reset.c

@@ -1,91 +0,0 @@
-#include <common.h>
-#include <asm/arch/sysctl.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/clock.h>
-
-void reset_cpu(ulong addr)
-{
-	u32 value;
-
-	// Assert reset to cores as per power on defaults
-	// Don't touch the DDR interface as things will come to an impromptu stop
-	// NB Possibly should be asserting reset for PLLB, but there are timing
-	//    concerns here according to the docs
-
-	value =
-		BIT(SYS_CTRL_RST_COPRO     ) |
-		BIT(SYS_CTRL_RST_USBHS     ) |
-		BIT(SYS_CTRL_RST_USBHSPHYA ) |
-		BIT(SYS_CTRL_RST_MACA      ) |
-		BIT(SYS_CTRL_RST_PCIEA     ) |
-		BIT(SYS_CTRL_RST_SGDMA     ) |
-		BIT(SYS_CTRL_RST_CIPHER    ) |
-		BIT(SYS_CTRL_RST_SATA      ) |
-		BIT(SYS_CTRL_RST_SATA_LINK ) |
-		BIT(SYS_CTRL_RST_SATA_PHY  ) |
-		BIT(SYS_CTRL_RST_PCIEPHY   ) |
-		BIT(SYS_CTRL_RST_STATIC    ) |
-		BIT(SYS_CTRL_RST_UART1     ) |
-		BIT(SYS_CTRL_RST_UART2     ) |
-		BIT(SYS_CTRL_RST_MISC      ) |
-		BIT(SYS_CTRL_RST_I2S       ) |
-		BIT(SYS_CTRL_RST_SD        ) |
-		BIT(SYS_CTRL_RST_MACB      ) |
-		BIT(SYS_CTRL_RST_PCIEB     ) |
-		BIT(SYS_CTRL_RST_VIDEO     ) |
-		BIT(SYS_CTRL_RST_USBHSPHYB ) |
-		BIT(SYS_CTRL_RST_USBDEV    );
-
-	writel(value, SYS_CTRL_RST_SET_CTRL);
-
-	// Release reset to cores as per power on defaults
-	writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL);
-
-	// Disable clocks to cores as per power-on defaults - must leave DDR
-	// related clocks enabled otherwise we'll stop rather abruptly.
-	value =
-		BIT(SYS_CTRL_CLK_COPRO) 	|
-		BIT(SYS_CTRL_CLK_DMA)   	|
-		BIT(SYS_CTRL_CLK_CIPHER)	|
-		BIT(SYS_CTRL_CLK_SD)  		|
-		BIT(SYS_CTRL_CLK_SATA)  	|
-		BIT(SYS_CTRL_CLK_I2S)   	|
-		BIT(SYS_CTRL_CLK_USBHS) 	|
-		BIT(SYS_CTRL_CLK_MAC)   	|
-		BIT(SYS_CTRL_CLK_PCIEA)   	|
-		BIT(SYS_CTRL_CLK_STATIC)	|
-		BIT(SYS_CTRL_CLK_MACB)		|
-		BIT(SYS_CTRL_CLK_PCIEB)		|
-		BIT(SYS_CTRL_CLK_REF600)	|
-		BIT(SYS_CTRL_CLK_USBDEV);
-
-	writel(value, SYS_CTRL_CLK_CLR_CTRL);
-
-	// Enable clocks to cores as per power-on defaults
-
-	// Set sys-control pin mux'ing as per power-on defaults
-
-	writel(0, SYS_CONTROL_BASE + PINMUX_SECONDARY_SEL);
-	writel(0, SYS_CONTROL_BASE + PINMUX_TERTIARY_SEL);
-	writel(0, SYS_CONTROL_BASE + PINMUX_QUATERNARY_SEL);
-	writel(0, SYS_CONTROL_BASE + PINMUX_DEBUG_SEL);
-	writel(0, SYS_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);
-	writel(0, SYS_CONTROL_BASE + PINMUX_PULLUP_SEL);
-
-	writel(0, SEC_CONTROL_BASE + PINMUX_SECONDARY_SEL);
-	writel(0, SEC_CONTROL_BASE + PINMUX_TERTIARY_SEL);
-	writel(0, SEC_CONTROL_BASE + PINMUX_QUATERNARY_SEL);
-	writel(0, SEC_CONTROL_BASE + PINMUX_DEBUG_SEL);
-	writel(0, SEC_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);
-	writel(0, SEC_CONTROL_BASE + PINMUX_PULLUP_SEL);
-
-	// No need to save any state, as the ROM loader can determine whether reset
-	// is due to power cycling or programatic action, just hit the (self-
-	// clearing) CPU reset bit of the block reset register
-	value =
-		BIT(SYS_CTRL_RST_SCU) |
-		BIT(SYS_CTRL_RST_ARM0) |
-		BIT(SYS_CTRL_RST_ARM1);
-
-	writel(value, SYS_CTRL_RST_SET_CTRL);
-}

package/boot/uboot-oxnas/src/arch/arm/cpu/arm1136/nas782x/timer.c

@@ -1,129 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#define TIMER_CLOCK	(CONFIG_SYS_CLK_FREQ / (1 << (CONFIG_TIMER_PRESCALE * 4)))
-#define TIMER_LOAD_VAL 0xFFFFFF
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER	(TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR)) \
-			/ (TIMER_CLOCK / CONFIG_SYS_HZ)
-
-#define READ_TIMER_HW	(TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR))
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int timer_init (void)
-{
-	int32_t val;
-
-	/* Start the counter ticking up */
-	writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + TIMER_LOAD);	/* reload value on overflow*/
-
-	val = (CONFIG_TIMER_PRESCALE << TIMER_PRESCALE_SHIFT) |
-			(TIMER_MODE_PERIODIC << TIMER_MODE_SHIFT) |
-			(TIMER_ENABLE << TIMER_ENABLE_SHIFT);		/* mask to enable timer*/
-	writel(val, CONFIG_SYS_TIMERBASE + TIMER_CTRL);	/* start timer */
-
-	/* reset time */
-	gd->arch.lastinc = READ_TIMER;	/* capture current incrementer value */
-	gd->arch.tbl = 0;		/* start "advancing" time stamp */
-
-	return(0);
-}
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay (unsigned long usec)
-{
-	ulong tmo, tmp;
-
-	if (usec > 100000) {		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;	/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-
-		tmp = get_timer (0);		/* get current timestamp */
-		while (get_timer (tmp) < tmo)/* loop till event */
-			/*NOP*/;
-	} else {			/* else small number, convert to hw ticks */
-		tmo = usec * (TIMER_CLOCK / 1000) / 1000;
-		/* timeout is no more than 0.1s, and the hw timer will roll over at most once */
-		tmp = READ_TIMER_HW;
-		while (((READ_TIMER_HW -tmp) & TIMER_LOAD_VAL) < tmo)/* loop till event */
-			/*NOP*/;
-	}
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;		/* current tick value */
-
-	if (now >= gd->arch.lastinc) {		/* normal mode (non roll) */
-		/* move stamp fordward with absoulte diff ticks */
-		gd->arch.tbl += (now - gd->arch.lastinc);
-	} else {
-		/* we have rollover of incrementer */
-		gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
-				 - gd->arch.lastinc) + now;
-	}
-	gd->arch.lastinc = now;
-	return gd->arch.tbl;
-}
-
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}

package/boot/uboot-oxnas/src/arch/arm/include/asm/arch-nas782x/clock.h

@@ -1,84 +0,0 @@
-#ifndef _NAS782X_CLOCK_H
-#define _NAS782X_CLOCK_H
-
-#include <asm/arch/sysctl.h>
-#include <asm/arch/cpu.h>
-
-/* bit numbers of clock control register */
-#define SYS_CTRL_CLK_COPRO  0
-#define SYS_CTRL_CLK_DMA    1
-#define SYS_CTRL_CLK_CIPHER 2
-#define SYS_CTRL_CLK_SD     3
-#define SYS_CTRL_CLK_SATA   4
-#define SYS_CTRL_CLK_I2S    5
-#define SYS_CTRL_CLK_USBHS  6
-#define SYS_CTRL_CLK_MACA   7
-#define SYS_CTRL_CLK_MAC   SYS_CTRL_CLK_MACA
-#define SYS_CTRL_CLK_PCIEA  8
-#define SYS_CTRL_CLK_STATIC 9
-#define SYS_CTRL_CLK_MACB   10
-#define SYS_CTRL_CLK_PCIEB  11
-#define SYS_CTRL_CLK_REF600 12
-#define SYS_CTRL_CLK_USBDEV 13
-#define SYS_CTRL_CLK_DDR    14
-#define SYS_CTRL_CLK_DDRPHY 15
-#define SYS_CTRL_CLK_DDRCK  16
-
-/* bit numbers of reset control register */
-#define SYS_CTRL_RST_SCU          0
-#define SYS_CTRL_RST_COPRO        1
-#define SYS_CTRL_RST_ARM0         2
-#define SYS_CTRL_RST_ARM1         3
-#define SYS_CTRL_RST_USBHS        4
-#define SYS_CTRL_RST_USBHSPHYA    5
-#define SYS_CTRL_RST_MACA         6
-#define SYS_CTRL_RST_MAC	SYS_CTRL_RST_MACA
-#define SYS_CTRL_RST_PCIEA        7
-#define SYS_CTRL_RST_SGDMA        8
-#define SYS_CTRL_RST_CIPHER       9
-#define SYS_CTRL_RST_DDR          10
-#define SYS_CTRL_RST_SATA         11
-#define SYS_CTRL_RST_SATA_LINK    12
-#define SYS_CTRL_RST_SATA_PHY     13
-#define SYS_CTRL_RST_PCIEPHY      14
-#define SYS_CTRL_RST_STATIC       15
-#define SYS_CTRL_RST_GPIO         16
-#define SYS_CTRL_RST_UART1        17
-#define SYS_CTRL_RST_UART2        18
-#define SYS_CTRL_RST_MISC         19
-#define SYS_CTRL_RST_I2S          20
-#define SYS_CTRL_RST_SD           21
-#define SYS_CTRL_RST_MACB         22
-#define SYS_CTRL_RST_PCIEB        23
-#define SYS_CTRL_RST_VIDEO        24
-#define SYS_CTRL_RST_DDR_PHY      25
-#define SYS_CTRL_RST_USBHSPHYB    26
-#define SYS_CTRL_RST_USBDEV       27
-#define SYS_CTRL_RST_ARMDBG       29
-#define SYS_CTRL_RST_PLLA         30
-#define SYS_CTRL_RST_PLLB         31
-
-static inline void reset_block(int block, int reset)
-{
-	u32 reg;
-	if (reset)
-		reg = SYS_CTRL_RST_SET_CTRL;
-	else
-		reg = SYS_CTRL_RST_CLR_CTRL;
-
-	writel(BIT(block), reg);
-}
-
-static inline void enable_clock(int block)
-{
-	writel(BIT(block), SYS_CTRL_CLK_SET_CTRL);
-}
-
-static inline void disable_clock(int block)
-{
-	writel(BIT(block), SYS_CTRL_CLK_CLR_CTRL);
-}
-
-int plla_set_config(int idx);
-
-#endif /* _NAS782X_CLOCK_H */

package/boot/uboot-oxnas/src/arch/arm/include/asm/arch-nas782x/cpu.h

@@ -1,26 +0,0 @@
-#ifndef _NAS782X_CPU_H
-#define _NAS782X_CPU_H
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-#include <asm/io.h>
-#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/timer.h>
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-
-#define BIT(x)                  (1 << (x))
-
-/* fix "implicit declaration of function" warnning */
-void *memalign(size_t alignment, size_t bytes);
-void free(void* mem);
-void *malloc(size_t bytes);
-void *calloc(size_t n, size_t elem_size);
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#endif /* _NAS782X_CPU_H */

package/boot/uboot-oxnas/src/arch/arm/include/asm/arch-nas782x/hardware.h

@@ -1,30 +0,0 @@
-#ifndef _NAS782X_HARDWARE_H
-#define _NAS782X_HARDWARE_H
-
-/* Core addresses */
-#define USB_HOST_BASE		0x40200000
-#define MACA_BASE		0x40400000
-#define MACB_BASE		0x40800000
-#define MAC_BASE		MACA_BASE
-#define STATIC_CS0_BASE		0x41000000
-#define STATIC_CS1_BASE		0x41400000
-#define STATIC_CONTROL_BASE	0x41C00000
-#define SATA_DATA_BASE		0x42000000 /* non-functional, DMA just needs an address */
-#define GPIO_1_BASE		0x44000000
-#define GPIO_2_BASE		0x44100000
-#define UART_1_BASE		0x44200000
-#define UART_2_BASE		0x44300000
-#define SYS_CONTROL_BASE	0x44e00000
-#define SEC_CONTROL_BASE	0x44f00000
-#define RPSA_BASE		0x44400000
-#define RPSC_BASE		0x44500000
-#define DDR_BASE		0x44700000
-
-#define SATA_BASE		0x45900000
-#define SATA_0_REGS_BASE	0x45900000
-#define SATA_1_REGS_BASE	0x45910000
-#define SATA_DMA_REGS_BASE	0x459a0000
-#define SATA_SGDMA_REGS_BASE	0x459b0000
-#define SATA_HOST_REGS_BASE	0x459e0000
-
-#endif /* _NAS782X_HARDWARE_H */

package/boot/uboot-oxnas/src/arch/arm/include/asm/arch-nas782x/pinmux.h

@@ -1,46 +0,0 @@
-#ifndef _NAS782X_PINMUX_H
-#define _NAS782X_PINMUX_H
-
-#include <asm/arch/cpu.h>
-
-#define PINMUX_GPIO		0
-#define PINMUX_2		1
-#define PINMUX_3		2
-#define PINMUX_4		3
-#define PINMUX_DEBUG		4
-#define PINMUX_ALT		5
-
-#define PINMUX_BANK_MFA		0
-#define PINMUX_BANK_MFB		1
-
-/* System control multi-function pin function selection */
-#define PINMUX_SECONDARY_SEL		0x14
-#define PINMUX_TERTIARY_SEL		0x8c
-#define PINMUX_QUATERNARY_SEL		0x94
-#define PINMUX_DEBUG_SEL		0x9c
-#define PINMUX_ALTERNATIVE_SEL		0xa4
-#define PINMUX_PULLUP_SEL		0xac
-
-#define PINMUX_UARTA_SIN		PINMUX_ALT
-#define PINMUX_UARTA_SOUT		PINMUX_ALT
-
-#define PINMUX_STATIC_DATA0		PINMUX_2
-#define PINMUX_STATIC_DATA1		PINMUX_2
-#define PINMUX_STATIC_DATA2		PINMUX_2
-#define PINMUX_STATIC_DATA3		PINMUX_2
-#define PINMUX_STATIC_DATA4		PINMUX_2
-#define PINMUX_STATIC_DATA5		PINMUX_2
-#define PINMUX_STATIC_DATA6		PINMUX_2
-#define PINMUX_STATIC_DATA7		PINMUX_2
-#define PINMUX_STATIC_NWE		PINMUX_2
-#define PINMUX_STATIC_NOE		PINMUX_2
-#define PINMUX_STATIC_NCS		PINMUX_2
-#define PINMUX_STATIC_ADDR18		PINMUX_2
-#define PINMUX_STATIC_ADDR19		PINMUX_2
-
-#define PINMUX_MACA_MDC			PINMUX_2
-#define PINMUX_MACA_MDIO		PINMUX_2
-
-extern void pinmux_set(int bank, int pin, int func);
-
-#endif /* _NAS782X_PINMUX_H */

package/boot/uboot-oxnas/src/arch/arm/include/asm/arch-nas782x/spl.h

@@ -1,6 +0,0 @@
-#ifndef _NAS782X_SPL_H
-#define _NAS782X_SPL_H
-
-#include <asm/arch/cpu.h>
-
-#endif /* _NAS782X_SPL_H */

package/boot/uboot-oxnas/src/arch/arm/include/asm/arch-nas782x/sysctl.h

@@ -1,125 +0,0 @@
-#ifndef _NAS782X_SYSCTL_H
-#define _NAS782X_SYSCTL_H
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
-
-#include <asm/arch/hardware.h>
-
-/**
- * System block reset and clock control
- */
-#define SYS_CTRL_PCI_STAT		(SYS_CONTROL_BASE + 0x20)
-#define SYS_CTRL_CLK_SET_CTRL		(SYS_CONTROL_BASE + 0x2C)
-#define SYS_CTRL_CLK_CLR_CTRL		(SYS_CONTROL_BASE + 0x30)
-#define SYS_CTRL_RST_SET_CTRL		(SYS_CONTROL_BASE + 0x34)
-#define SYS_CTRL_RST_CLR_CTRL		(SYS_CONTROL_BASE + 0x38)
-#define SYS_CTRL_PLLSYS_CTRL		(SYS_CONTROL_BASE + 0x48)
-#define SYS_CTRL_PLLSYS_KEY_CTRL	(SYS_CONTROL_BASE + 0x6C)
-#define SYS_CTRL_GMAC_CTRL		(SYS_CONTROL_BASE + 0x78)
-
-/* Scratch registers */
-#define SYS_CTRL_SCRATCHWORD0		(SYS_CONTROL_BASE + 0xc4)
-#define SYS_CTRL_SCRATCHWORD1		(SYS_CONTROL_BASE + 0xc8)
-#define SYS_CTRL_SCRATCHWORD2		(SYS_CONTROL_BASE + 0xcc)
-#define SYS_CTRL_SCRATCHWORD3		(SYS_CONTROL_BASE + 0xd0)
-
-#define SYS_CTRL_PLLA_CTRL0		(SYS_CONTROL_BASE + 0x1F0)
-#define SYS_CTRL_PLLA_CTRL1		(SYS_CONTROL_BASE + 0x1F4)
-#define SYS_CTRL_PLLA_CTRL2		(SYS_CONTROL_BASE + 0x1F8)
-#define SYS_CTRL_PLLA_CTRL3		(SYS_CONTROL_BASE + 0x1FC)
-
-#define SYS_CTRL_GMAC_AUTOSPEED		3
-#define SYS_CTRL_GMAC_RGMII		2
-#define SYS_CTRL_GMAC_SIMPLE_MUX	1
-#define SYS_CTRL_GMAC_CKEN_GTX		0
-
-#define SYS_CTRL_CKCTRL_CTRL_ADDR	(SYS_CONTROL_BASE + 0x64)
-
-#define SYS_CTRL_CKCTRL_PCI_DIV_BIT	0
-#define SYS_CTRL_CKCTRL_SLOW_BIT	8
-
-
-#define SYS_CTRL_USBHSMPH_CTRL		(SYS_CONTROL_BASE + 0x40)
-#define SYS_CTRL_USBHSMPH_STAT		(SYS_CONTROL_BASE + 0x44)
-#define SYS_CTRL_REF300_DIV		(SYS_CONTROL_BASE + 0xF8)
-#define SYS_CTRL_USBHSPHY_CTRL		(SYS_CONTROL_BASE + 0x84)
-#define SYS_CTRL_USB_CTRL		(SYS_CONTROL_BASE + 0x90)
-
-/* System control multi-function pin function selection */
-#define SYS_CTRL_SECONDARY_SEL		(SYS_CONTROL_BASE + 0x14)
-#define SYS_CTRL_TERTIARY_SEL		(SYS_CONTROL_BASE + 0x8c)
-#define SYS_CTRL_QUATERNARY_SEL		(SYS_CONTROL_BASE + 0x94)
-#define SYS_CTRL_DEBUG_SEL		(SYS_CONTROL_BASE + 0x9c)
-#define SYS_CTRL_ALTERNATIVE_SEL	(SYS_CONTROL_BASE + 0xa4)
-#define SYS_CTRL_PULLUP_SEL		(SYS_CONTROL_BASE + 0xac)
-
-/* Secure control multi-function pin function selection */
-#define SEC_CTRL_SECONDARY_SEL		(SEC_CONTROL_BASE + 0x14)
-#define SEC_CTRL_TERTIARY_SEL		(SEC_CONTROL_BASE + 0x8c)
-#define SEC_CTRL_QUATERNARY_SEL		(SEC_CONTROL_BASE + 0x94)
-#define SEC_CTRL_DEBUG_SEL		(SEC_CONTROL_BASE + 0x9c)
-#define SEC_CTRL_ALTERNATIVE_SEL	(SEC_CONTROL_BASE + 0xa4)
-#define SEC_CTRL_PULLUP_SEL		(SEC_CONTROL_BASE + 0xac)
-
-#define SEC_CTRL_COPRO_CTRL		(SEC_CONTROL_BASE + 0x68)
-#define SEC_CTRL_SECURE_CTRL		(SEC_CONTROL_BASE + 0x98)
-#define SEC_CTRL_LEON_DEBUG		(SEC_CONTROL_BASE + 0xF0)
-#define SEC_CTRL_PLLB_DIV_CTRL		(SEC_CONTROL_BASE + 0xF8)
-#define SEC_CTRL_PLLB_CTRL0		(SEC_CONTROL_BASE + 0x1F0)
-#define SEC_CTRL_PLLB_CTRL1		(SEC_CONTROL_BASE + 0x1F4)
-#define SEC_CTRL_PLLB_CTRL8		(SEC_CONTROL_BASE + 0x1F4)
-
-#define REF300_DIV_INT_SHIFT		8
-#define REF300_DIV_FRAC_SHIFT		0
-#define REF300_DIV_INT(val)		((val) << REF300_DIV_INT_SHIFT)
-#define REF300_DIV_FRAC(val)		((val) << REF300_DIV_FRAC_SHIFT)
-
-#define USBHSPHY_SUSPENDM_MANUAL_ENABLE		16
-#define USBHSPHY_SUSPENDM_MANUAL_STATE		15
-#define USBHSPHY_ATE_ESET			14
-#define USBHSPHY_TEST_DIN			6
-#define USBHSPHY_TEST_ADD			2
-#define USBHSPHY_TEST_DOUT_SEL			1
-#define USBHSPHY_TEST_CLK			0
-
-#define USB_CTRL_USBAPHY_CKSEL_SHIFT	5
-#define USB_CLK_XTAL0_XTAL1		(0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_XTAL0			(1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_INTERNAL		(2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-
-#define USBAMUX_DEVICE			BIT(4)
-
-#define USBPHY_REFCLKDIV_SHIFT		2
-#define USB_PHY_REF_12MHZ		(0 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_24MHZ		(1 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_48MHZ		(2 << USBPHY_REFCLKDIV_SHIFT)
-
-#define USB_CTRL_USB_CKO_SEL_BIT	0
-
-#define USB_INT_CLK_XTAL 		0
-#define USB_INT_CLK_REF300		2
-#define USB_INT_CLK_PLLB		3
-
-#define SYS_CTRL_GMAC_AUTOSPEED		3
-#define SYS_CTRL_GMAC_RGMII		2
-#define SYS_CTRL_GMAC_SIMPLE_MUX	1
-#define SYS_CTRL_GMAC_CKEN_GTX		0
-
-
-#define PLLB_ENSAT			3
-#define PLLB_OUTDIV			4
-#define PLLB_REFDIV			8
-#define PLLB_DIV_INT_SHIFT		8
-#define PLLB_DIV_FRAC_SHIFT		0
-#define PLLB_DIV_INT(val)		((val) << PLLB_DIV_INT_SHIFT)
-#define PLLB_DIV_FRAC(val)		((val) << PLLB_DIV_FRAC_SHIFT)
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#endif /* _NAS782X_SYSCTL_H */

package/boot/uboot-oxnas/src/arch/arm/include/asm/arch-nas782x/timer.h

@@ -1,23 +0,0 @@
-#ifndef _NAS782X_TIMER_H
-#define _NAS782X_TIMER_H
-
-#define TIMER1_BASE		(RPSA_BASE + 0x200)
-#define TIMER2_BASE		(RPSA_BASE + 0x220)
-
-#define TIMER_LOAD		0
-#define TIMER_CURR		4
-#define TIMER_CTRL		8
-#define	TIMER_INTR		0x0C
-
-#define TIMER_PRESCALE_SHIFT		2
-#define TIMER_PRESCALE_1		0
-#define TIMER_PRESCALE_16		1
-#define TIMER_PRESCALE_256		2
-#define TIMER_MODE_SHIFT		6
-#define TIMER_MODE_FREE_RUNNING		0
-#define TIMER_MODE_PERIODIC		1
-#define TIMER_ENABLE_SHIFT		7
-#define TIMER_DISABLE			0
-#define TIMER_ENABLE			1
-
-#endif /* _NAS782X_TIMER_H */

package/boot/uboot-oxnas/src/board/ox820/Kconfig

@@ -1,15 +0,0 @@
-if TARGET_OX820
-
-config SYS_CPU
-	default "arm1136"
-
-config SYS_SOC
-	default "nas782x"
-
-config SYS_BOARD
-	default "ox820"
-
-config SYS_CONFIG_NAME
-	default "ox820"
-
-endif

package/boot/uboot-oxnas/src/board/ox820/MAINTAINERS

@@ -1,6 +0,0 @@
-SHEEVAPLUG BOARD
-M:	Daniel Golle <daniel@makrotopia.org>
-S:	Maintained
-F:	board/ox820/
-F:	include/configs/ox820.h
-F:	configs/ox820_defconfig

package/boot/uboot-oxnas/src/board/ox820/Makefile

@@ -1,15 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += ox820.o
-obj-y += lowlevel_init.o
-
-obj-$(CONFIG_SPL_BUILD) += spl_start.o
-obj-$(CONFIG_SPL_BUILD) += ddr.o
-

package/boot/uboot-oxnas/src/board/ox820/ddr.c

@@ -1,477 +0,0 @@
-/*******************************************************************
- *
- * File:            ddr_oxsemi.c
- *
- * Description:     Declarations for DDR routines and data objects
- *
- * Author:          Julien Margetts
- *
- * Copyright:       Oxford Semiconductor Ltd, 2009
- */
-#include <common.h>
-#include <asm/arch/clock.h>
-
-#include "ddr.h"
-
-typedef unsigned int UINT;
-
-// DDR TIMING PARAMETERS
-typedef struct {
-	unsigned int holdoff_cmd_A;
-	unsigned int holdoff_cmd_ARW;
-	unsigned int holdoff_cmd_N;
-	unsigned int holdoff_cmd_LM;
-	unsigned int holdoff_cmd_R;
-	unsigned int holdoff_cmd_W;
-	unsigned int holdoff_cmd_PC;
-	unsigned int holdoff_cmd_RF;
-	unsigned int holdoff_bank_R;
-	unsigned int holdoff_bank_W;
-	unsigned int holdoff_dir_RW;
-	unsigned int holdoff_dir_WR;
-	unsigned int holdoff_FAW;
-	unsigned int latency_CAS;
-	unsigned int latency_WL;
-	unsigned int recovery_WR;
-	unsigned int width_update;
-	unsigned int odt_offset;
-	unsigned int odt_drive_all;
-	unsigned int use_fixed_re;
-	unsigned int delay_wr_to_re;
-	unsigned int wr_slave_ratio;
-	unsigned int rd_slave_ratio0;
-	unsigned int rd_slave_ratio1;
-} T_DDR_TIMING_PARAMETERS;
-
-// DDR CONFIG PARAMETERS
-
-typedef struct {
-	unsigned int ddr_mode;
-	unsigned int width;
-	unsigned int blocs;
-	unsigned int banks8;
-	unsigned int rams;
-	unsigned int asize;
-	unsigned int speed;
-	unsigned int cmd_mode_wr_cl_bl;
-} T_DDR_CONFIG_PARAMETERS;
-
-//cmd_mode_wr_cl_bl
-//when SDR : cmd_mode_wr_cl_bl = 0x80200002 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8
-//else       cmd_mode_wr_cl_bl = 0x80200003 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8
-
-//                                                            cmd_                    bank_ dir_     lat_  rec_ width_ odt_   odt_ fix delay     ratio
-//                                                                A                                F  C         update offset all  re  re_to_we  w  r0  r1
-//                                                                R     L        P  R        R  W  A  A  W  W
-//Timing Parameters                                            A  W  N  M  R  W  C  F  R  W  W  R  W  S  L  R
-static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_1GB = { 4, 5, 0, 2, 4, 4,
-	5, 51, 23, 24, 9, 11, 18, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; //elida device.
-static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_2GB = { 4, 5, 0, 2, 4, 4,
-	5, 79, 22, 24, 9, 11, 20, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 };
-static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25_CL6_1GB = { 4, 5, 0, 2, 4, 4,
-	4, 51, 22, 26, 10, 12, 18, 6, 5, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; // 400MHz, Speedgrade 25 timings (1Gb parts)
-
-//                                                          D     B  B  R  A   S
-//                                                          D  W  L  K  A  S   P
-//Config Parameters                                         R  D  C  8  M  Z   D CMD_MODE
-//static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5  = { 2,16, 1, 0, 1, 32,25,0x80200A53}; // 64 MByte
-static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5 = { 2, 16, 1, 1, 1, 64,
-	25, 0x80200A53 }; // 128 MByte
-static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25_CL6 = { 2, 16, 1, 1, 1, 128,
-	25, 0x80200A63 }; // 256 MByte
-
-static void ddr_phy_poll_until_locked(void)
-{
-	volatile UINT reg_tmp = 0;
-	volatile UINT locked = 0;
-
-	//Extra read to put in delay before starting to poll...
-	reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;      // read
-
-	//POLL C_DDR_PHY2_REG register until clock and flock
-	//!!! Ideally have a timeout on this.
-	while (locked == 0) {
-		reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;      // read
-
-		//locked when bits 30 and 31 are set
-		if (reg_tmp & 0xC0000000) {
-			locked = 1;
-		}
-	}
-}
-
-static void ddr_poll_until_not_busy(void)
-{
-	volatile UINT reg_tmp = 0;
-	volatile UINT busy = 1;
-
-	//Extra read to put in delay before starting to poll...
-	reg_tmp = *(volatile UINT *) C_DDR_STAT_REG;      // read
-
-	//POLL DDR_STAT register until no longer busy
-	//!!! Ideally have a timeout on this.
-	while (busy == 1) {
-		reg_tmp = *(volatile UINT *) C_DDR_STAT_REG;      // read
-
-		//when bit 31 is clear - core is no longer busy
-		if ((reg_tmp & 0x80000000) == 0x00000000) {
-			busy = 0;
-		}
-	}
-}
-
-static void ddr_issue_command(int commmand)
-{
-	*(volatile UINT *) C_DDR_CMD_REG = commmand;
-	ddr_poll_until_not_busy();
-}
-
-static void ddr_timing_initialisation(
-	const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters)
-{
-	volatile UINT reg_tmp = 0;
-	/* update the DDR controller registers for timing parameters */
-	reg_tmp = (ddr_timing_parameters->holdoff_cmd_A << 0);
-	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_ARW << 4);
-	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_N << 8);
-	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_LM << 12);
-	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_R << 16);
-	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_W << 20);
-	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_PC << 24);
-	*(volatile UINT *) C_DDR_REG_TIMING0 = reg_tmp;
-
-	reg_tmp = (ddr_timing_parameters->holdoff_cmd_RF << 0);
-	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_R << 8);
-	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_W << 16);
-	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_RW << 24);
-	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_WR << 28);
-	*(volatile UINT *) C_DDR_REG_TIMING1 = reg_tmp;
-
-	reg_tmp = (ddr_timing_parameters->latency_CAS << 0);
-	reg_tmp = reg_tmp + (ddr_timing_parameters->latency_WL << 4);
-	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_FAW << 8);
-	reg_tmp = reg_tmp + (ddr_timing_parameters->width_update << 16);
-	reg_tmp = reg_tmp + (ddr_timing_parameters->odt_offset << 21);
-	reg_tmp = reg_tmp + (ddr_timing_parameters->odt_drive_all << 24);
-
-	*(volatile UINT *) C_DDR_REG_TIMING2 = reg_tmp;
-
-	/* Program the timing parameters in the PHY too */
-	reg_tmp = (ddr_timing_parameters->use_fixed_re << 16)
-			| (ddr_timing_parameters->delay_wr_to_re << 8)
-			| (ddr_timing_parameters->latency_WL << 4)
-			| (ddr_timing_parameters->latency_CAS << 0);
-
-	*(volatile UINT *) C_DDR_REG_PHY_TIMING = reg_tmp;
-
-	reg_tmp = ddr_timing_parameters->wr_slave_ratio;
-
-	*(volatile UINT *) C_DDR_REG_PHY_WR_RATIO = reg_tmp;
-
-	reg_tmp = ddr_timing_parameters->rd_slave_ratio0;
-	reg_tmp += ddr_timing_parameters->rd_slave_ratio1 << 8;
-
-	*(volatile UINT *) C_DDR_REG_PHY_RD_RATIO = reg_tmp;
-
-}
-
-static void ddr_normal_initialisation(
-	const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters, int mhz)
-{
-	int i;
-	volatile UINT tmp = 0;
-	volatile UINT reg_tmp = 0;
-	volatile UINT emr_cmd = 0;
-	UINT refresh;
-
-	//Total size of memory in Mbits...
-	tmp = ddr_config_parameters->rams * ddr_config_parameters->asize
-		* ddr_config_parameters->width;
-	//Deduce value to program into DDR_CFG register...
-	switch (tmp) {
-	case 16:
-		reg_tmp = 0x00020000 * 1;
-		break;
-	case 32:
-		reg_tmp = 0x00020000 * 2;
-		break;
-	case 64:
-		reg_tmp = 0x00020000 * 3;
-		break;
-	case 128:
-		reg_tmp = 0x00020000 * 4;
-		break;
-	case 256:
-		reg_tmp = 0x00020000 * 5;
-		break;
-	case 512:
-		reg_tmp = 0x00020000 * 6;
-		break;
-	case 1024:
-		reg_tmp = 0x00020000 * 7;
-		break;
-	case 2048:
-		reg_tmp = 0x00020000 * 8;
-		break;
-	default:
-		reg_tmp = 0; //forces sims not to work if badly configured
-	}
-
-	//Memory width
-	tmp = ddr_config_parameters->rams * ddr_config_parameters->width;
-	switch (tmp) {
-	case 8:
-		reg_tmp = reg_tmp + 0x00400000;
-		break;
-	case 16:
-		reg_tmp = reg_tmp + 0x00200000;
-		break;
-	case 32:
-		reg_tmp = reg_tmp + 0x00000000;
-		break;
-	default:
-		reg_tmp = 0; //forces sims not to work if badly configured
-	}
-
-	//Setup DDR Mode
-	switch (ddr_config_parameters->ddr_mode) {
-	case 0:
-		reg_tmp = reg_tmp + 0x00000000;
-		break;   //SDR
-	case 1:
-		reg_tmp = reg_tmp + 0x40000000;
-		break;   //DDR
-	case 2:
-		reg_tmp = reg_tmp + 0x80000000;
-		break;   //DDR2
-	default:
-		reg_tmp = 0; //forces sims not to work if badly configured
-	}
-
-	//Setup Banks
-	if (ddr_config_parameters->banks8 == 1) {
-		reg_tmp = reg_tmp + 0x00800000;
-	}
-
-	//Program DDR_CFG register...
-	*(volatile UINT *) C_DDR_CFG_REG = reg_tmp;
-
-	//Configure PHY0 reg - se_mode is bit 1,
-	//needs to be 1 for DDR (single_ended drive)
-	switch (ddr_config_parameters->ddr_mode) {
-	case 0:
-		reg_tmp = 2 + (0 << 4);
-		break;   //SDR
-	case 1:
-		reg_tmp = 2 + (4 << 4);
-		break;   //DDR
-	case 2:
-		reg_tmp = 0 + (4 << 4);
-		break;   //DDR2
-	default:
-		reg_tmp = 0;
-	}
-
-	//Program DDR_PHY0 register...
-	*(volatile UINT *) C_DDR_REG_PHY0 = reg_tmp;
-
-	//Read DDR_PHY* registers to exercise paths for vcd
-	reg_tmp = *(volatile UINT *) C_DDR_REG_PHY3;
-	reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;
-	reg_tmp = *(volatile UINT *) C_DDR_REG_PHY1;
-	reg_tmp = *(volatile UINT *) C_DDR_REG_PHY0;
-
-	//Start up sequences - Different dependant on DDR mode
-	switch (ddr_config_parameters->ddr_mode) {
-	case 2:   //DDR2
-		//Start-up sequence: follows procedure described in Micron datasheet.
-		//start up DDR PHY DLL
-		reg_tmp = 0x00022828;       // dll on, start point and inc = h28
-		*(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;
-
-		reg_tmp = 0x00032828; // start on, dll on, start point and inc = h28
-		*(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;
-
-		ddr_phy_poll_until_locked();
-
-		udelay(200);   //200us
-
-		//Startup SDRAM...
-		//!!! Software: CK should be running for 200us before wake-up
-		ddr_issue_command( C_CMD_WAKE_UP);
-		ddr_issue_command( C_CMD_NOP);
-		ddr_issue_command( C_CMD_PRECHARGE_ALL);
-		ddr_issue_command( C_CMD_DDR2_EMR2);
-		ddr_issue_command( C_CMD_DDR2_EMR3);
-
-		emr_cmd = C_CMD_DDR2_EMR1 + C_CMD_ODT_75 + C_CMD_REDUCED_DRIVE
-			+ C_CMD_ENABLE_DLL;
-
-		ddr_issue_command(emr_cmd);
-		//Sets CL=3; BL=8 but also reset DLL to trigger a DLL initialisation...
-		udelay(1);   //1us
-		ddr_issue_command(
-			ddr_config_parameters->cmd_mode_wr_cl_bl
-			+ C_CMD_RESET_DLL);
-		udelay(1);   //1us
-
-		//!!! Software: Wait 200 CK cycles before...
-		//for(i=1; i<=2; i++) {
-		ddr_issue_command(C_CMD_PRECHARGE_ALL);
-		// !!! Software: Wait here at least 8 CK cycles
-		//}
-		//need a wait here to ensure PHY DLL lock before the refresh is issued
-		udelay(1);   //1us
-		for (i = 1; i <= 2; i++) {
-			ddr_issue_command( C_CMD_AUTO_REFRESH);
-			//!!! Software: Wait here at least 8 CK cycles to satify tRFC
-			udelay(1);   //1us
-		}
-		//As before but without 'RESET_DLL' bit set...
-		ddr_issue_command(ddr_config_parameters->cmd_mode_wr_cl_bl);
-		udelay(1);   //1us
-		// OCD commands
-		ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_DFLT);
-		ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_EXIT);
-		break;
-
-	default:
-		break;  //Do nothing
-	}
-
-	//Enable auto-refresh
-
-	// 8192 Refreshes required every 64ms, so maximum refresh period is 7.8125 us
-	// We have a 400 MHz DDR clock (2.5ns period) so max period is 3125 cycles
-	// Our core now does 8 refreshes in a go, so we multiply this period by 8
-
-	refresh = (64000 * mhz) / 8192; // Refresh period in clocks
-
-	reg_tmp = *(volatile UINT *) C_DDR_CFG_REG;      // read
-#ifdef BURST_REFRESH_ENABLE
-	reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 8);
-	reg_tmp |= C_CFG_BURST_REFRESH_ENABLE;
-#else
-	reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 1);
-	reg_tmp &= ~C_CFG_BURST_REFRESH_ENABLE;
-#endif
-	*(volatile UINT *) C_DDR_CFG_REG = reg_tmp;
-
-	//Verify register contents
-	reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;      // read
-	//printf("Warning XXXXXXXXXXXXXXXXXXXXXX - get bad read data from C_DDR_PHY2_REG, though it looks OK on bus XXXXXXXXXXXXXXXXXX");
-	//TBD   Check_data (read_data,  dll_reg, "Error: bad C_DDR_PHY2_REG read", tb_pass);
-	reg_tmp = *(volatile UINT *) C_DDR_CFG_REG;      // read
-	//TBD   Check_data (read_data,  cfg_reg, "Error: bad DDR_CFG read", tb_pass);
-
-	//disable optimised wrapping
-	if (ddr_config_parameters->ddr_mode == 2) {
-		reg_tmp = 0xFFFF0000;
-		*(volatile UINT *) C_DDR_REG_IGNORE = reg_tmp;
-	}
-
-	//enable midbuffer followon
-	reg_tmp = *(volatile UINT *) C_DDR_ARB_REG;      // read
-	reg_tmp = 0xFFFF0000 | reg_tmp;
-	*(volatile UINT *) C_DDR_ARB_REG = reg_tmp;
-
-	// Enable write behind coherency checking for all clients
-
-	reg_tmp = 0xFFFF0000;
-	*(volatile UINT *) C_DDR_AHB4_REG = reg_tmp;
-
-	//Wait for 200 clock cycles for SDRAM DLL to lock...
-	udelay(1);   //1us
-}
-
-// Function used to Setup DDR core
-
-void ddr_setup(int mhz)
-{
-	static const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters =
-		&C_TP_DDR2_25_CL6_1GB;
-	static const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters =
-		&C_CP_DDR2_25_CL6;
-
-	//Bring core out of Reset
-	*(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON;
-
-	//DDR TIMING INITIALISTION
-	ddr_timing_initialisation(ddr_timing_parameters);
-
-	//DDR NORMAL INITIALISATION
-	ddr_normal_initialisation(ddr_config_parameters, mhz);
-
-	// route all writes through one client
-	*(volatile UINT *) C_DDR_TRANSACTION_ROUTING = (0
-		<< DDR_ROUTE_CPU0_INSTR_SHIFT)
-		| (1 << DDR_ROUTE_CPU0_RDDATA_SHIFT)
-		| (3 << DDR_ROUTE_CPU0_WRDATA_SHIFT)
-		| (2 << DDR_ROUTE_CPU1_INSTR_SHIFT)
-		| (3 << DDR_ROUTE_CPU1_RDDATA_SHIFT)
-		| (3 << DDR_ROUTE_CPU1_WRDATA_SHIFT);
-
-	//Bring all clients out of reset
-	*(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON + 0x0000FFFF;
-
-}
-
-void set_ddr_timing(unsigned int w, unsigned int i)
-{
-	unsigned int reg;
-	unsigned int wnow = 16;
-	unsigned int inow = 32;
-
-	/* reset all timing controls to known value (31) */
-	writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);
-	writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST | DDR_PHY_TIMING_CK,
-	       DDR_PHY_TIMING);
-	writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);
-
-	/* step up or down read delay to the requested value */
-	while (wnow != w) {
-		if (wnow < w) {
-			reg = DDR_PHY_TIMING_INC;
-			wnow++;
-		} else {
-			reg = 0;
-			wnow--;
-		}
-		writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);
-		writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_W_CE | reg,
-		       DDR_PHY_TIMING);
-		writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);
-	}
-
-	/* now write delay */
-	while (inow != i) {
-		if (inow < i) {
-			reg = DDR_PHY_TIMING_INC;
-			inow++;
-		} else {
-			reg = 0;
-			inow--;
-		}
-		writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);
-		writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_I_CE | reg,
-		       DDR_PHY_TIMING);
-		writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);
-	}
-}
-
-//Function used to Setup SDRAM in DDR/SDR mode
-void init_ddr(int mhz)
-{
-	/* start clocks */
-	enable_clock(SYS_CTRL_CLK_DDRPHY);
-	enable_clock(SYS_CTRL_CLK_DDR);
-	enable_clock(SYS_CTRL_CLK_DDRCK);
-
-	/* bring phy and core out of reset */
-	reset_block(SYS_CTRL_RST_DDR_PHY, 0);
-	reset_block(SYS_CTRL_RST_DDR, 0);
-
-	/* DDR runs at half the speed of the CPU */
-	ddr_setup(mhz >> 1);
-	return;
-}

package/boot/uboot-oxnas/src/board/ox820/ddr.h

@@ -1,148 +0,0 @@
-/*******************************************************************
-*
-* File:			ddr_oxsemi.h
-*
-* Description:		Declarations for DDR routines and data objects
-*
-* Author:		Julien Margetts
-*
-* Copyright:		Oxford Semiconductor Ltd, 2009
-*/
-
-void ddr_oxsemi_setup(int mhz);
-
-/* define to refresh in bursts of 8 */
-#define BURST_REFRESH_ENABLE
-
-#define DDR_BASE			0x44700000
-
-#define C_DDR_CFG_REG			(DDR_BASE + 0x00)
-#define C_CFG_DDR			0x80000000
-#define C_CFG_SDR			0x00000000
-#define C_CFG_WIDTH8			0x00200000
-#define C_CFG_WIDTH16			0x00100000
-#define C_CFG_WIDTH32			0x00000000
-#define C_CFG_SIZE_FACTOR		0x00020000
-#define C_CFG_REFRESH_ENABLE		0x00010000
-#define C_CFG_BURST_REFRESH_ENABLE	0x01000000
-#define C_CFG_SIZE(x)			(x << 17)
-#define CFG_SIZE_2MB			1
-#define CFG_SIZE_4MB			2
-#define CFG_SIZE_8MB			3
-#define CFG_SIZE_16MB			4
-#define CFG_SIZE_32MB			5
-#define CFG_SIZE_64MB			6
-#define CFG_SIZE_128MB			7
-
-#define C_DDR_BLKEN_REG			(DDR_BASE + 0x04)
-#define C_BLKEN_DDR_ON			0x80000000
-
-#define C_DDR_STAT_REG			(DDR_BASE + 0x08)
-
-#define C_DDR_CMD_REG			(DDR_BASE + 0x0C)
-#define C_CMD_SEND_COMMAND		(1UL << 31) | (1 << 21) // RAS/CAS/WE/CS all low(active), CKE High, indicates
-#define C_CMD_WAKE_UP			0x80FC0000 // Asserts CKE
-#define C_CMD_MODE_SDR			0x80200022 // Sets CL=2 BL=4
-#define C_CMD_MODE_DDR			0x80200063 // Sets CL=2.5 BL=8
-#define C_CMD_RESET_DLL			0x00000100 // A8=1 Use in conjunction with C_CMD_MODE_DDR
-#define C_CMD_PRECHARGE_ALL		0x80280400
-#define C_CMD_AUTO_REFRESH		0x80240000
-#define C_CMD_SELF_REFRESH		0x80040000 // As AUTO-REFRESH but with CKE low
-#define C_CMD_NOP			0x803C0000 // NOP just to insert guaranteed delay
-#define C_CMD_DDR2_EMR1			0x80210000 // Load extended mode register 1 with zeros (for init), CKE still set
-//#define C_CMD_DDR2_EMR1		0x80210400 // Load extended mode register 1 with zeros (for init), CKE still set
-#define C_CMD_ENABLE_DLL		0x00000000 // Values used in conjuction with C_CMD_DDR2_EMR1
-#define C_CMD_DISABLE_DLL		0x00000001
-#define C_CMD_REDUCED_DRIVE		0x00000002
-#define C_CMD_ODT_DISABLED		0x00000000
-#define C_CMD_ODT_50			0x00000044
-#define C_CMD_ODT_75			0x00000004
-#define C_CMD_ODT_150			0x00000040
-#define C_CMD_MODE_DDR2_OCD_DFLT	0x00000380
-#define C_CMD_MODE_DDR2_OCD_EXIT	0x00000000
-
-#define C_CMD_DDR2_EMR2			0x80220000 // Load extended mode register 2 with zeros (for init), CKE still set
-#define C_CMD_DDR2_EMR3			0x80230000 // Load extended mode register 3 with zeros (for init), CKE still set
-
-#define C_DDR_AHB_REG			(DDR_BASE + 0x10)
-#define C_AHB_NO_RCACHES		0xFFFF0000
-#define C_AHB_FLUSH_ALL_RCACHES		0x0000FFFF
-#define C_AHB_FLUSH_AHB0_RCACHE		0x00000001
-#define C_AHB_FLUSH_AHB1_RCACHE		0x00000002
-
-#define C_DDR_DLL_REG			(DDR_BASE + 0x14)
-#define C_DLL_DISABLED			0x00000000
-#define C_DLL_MANUAL			0x80000000
-#define C_DLL_AUTO_OFFSET		0xA0000000
-#define C_DLL_AUTO_IN_REFRESH		0xC0000000
-#define C_DLL_AUTOMATIC			0xE0000000
-
-#define C_DDR_MON_REG			(DDR_BASE + 0x18)
-#define C_MON_ALL			0x00000010
-#define C_MON_CLIENT			0x00000000
-
-#define C_DDR_DIAG_REG			(DDR_BASE + 0x1C)
-#define C_DDR_DIAG2_REG			(DDR_BASE + 0x20)
-
-#define C_DDR_IOC_REG			(DDR_BASE + 0x24)
-#define C_DDR_IOC_PWR_DWN		(1 << 10)
-#define C_DDR_IOC_SEL_SSTL		(1 << 9)
-#define C_DDR_IOC_CK_DRIVE(x)		((x) << 6)
-#define C_DDR_IOC_DQ_DRIVE(x)		((x) << 3)
-#define C_DDR_IOC_XX_DRIVE(x)		((x) << 0)
-
-#define C_DDR_ARB_REG			(DDR_BASE + 0x28)
-#define C_DDR_ARB_MIDBUF		(1 << 4)
-#define C_DDR_ARB_LRUBANK		(1 << 3)
-#define C_DDR_ARB_REQAGE		(1 << 2)
-#define C_DDR_ARB_DATDIR		(1 << 1)
-#define C_DDR_ARB_DATDIR_NC		(1 << 0)
-
-#define C_TOP_ADDRESS_BIT_TEST		22
-#define C_MEM_BASE			C_SDRAM_BASE
-
-#define C_MEM_TEST_BASE			0
-#define C_MEM_TEST_LEN			1920
-#define C_MAX_RAND_ACCESS_LEN		16
-
-#define C_DDR_REG_IGNORE		(DDR_BASE + 0x2C)
-#define C_DDR_AHB4_REG			(DDR_BASE + 0x44)
-
-#define C_DDR_REG_TIMING0		(DDR_BASE + 0x34)
-#define C_DDR_REG_TIMING1		(DDR_BASE + 0x38)
-#define C_DDR_REG_TIMING2		(DDR_BASE + 0x3C)
-
-#define C_DDR_REG_PHY0			(DDR_BASE + 0x48)
-#define C_DDR_REG_PHY1			(DDR_BASE + 0x4C)
-#define C_DDR_REG_PHY2			(DDR_BASE + 0x50)
-#define C_DDR_REG_PHY3			(DDR_BASE + 0x54)
-
-#define C_DDR_REG_GENERIC		(DDR_BASE + 0x60)
-
-#define C_OXSEMI_DDRC_SIGNATURE		0x054415AA
-
-#define DDR_PHY_BASE			(DDR_BASE + 0x80000)
-#define DDR_PHY_TIMING			(DDR_PHY_BASE + 0x48)
-#define DDR_PHY_TIMING_CK		(1 << 12)
-#define DDR_PHY_TIMING_INC		(1 << 13)
-#define DDR_PHY_TIMING_W_CE		(1 << 14)
-#define DDR_PHY_TIMING_W_RST		(1 << 15)
-#define DDR_PHY_TIMING_I_CE		(1 << 16)
-#define DDR_PHY_TIMING_I_RST		(1 << 17)
-
-#define C_DDR_REG_PHY_TIMING		(DDR_PHY_BASE + 0x50)
-#define C_DDR_REG_PHY_WR_RATIO		(DDR_PHY_BASE + 0x74)
-#define C_DDR_REG_PHY_RD_RATIO		(DDR_PHY_BASE + 0x78)
-
-#define C_DDR_TRANSACTION_ROUTING	(DDR_PHY_BASE + 0xC8)
-#define DDR_ROUTE_CPU0_INSTR_SHIFT	0
-#define DDR_ROUTE_CPU0_RDDATA_SHIFT	4
-#define DDR_ROUTE_CPU0_WRDATA_SHIFT	6
-#define DDR_ROUTE_CPU1_INSTR_SHIFT	8
-#define DDR_ROUTE_CPU1_RDDATA_SHIFT	12
-#define DDR_ROUTE_CPU1_WRDATA_SHIFT	14
-
-unsigned int ddrc_signature(void);
-void set_ddr_timing(unsigned int w, unsigned int i);
-int pause(unsigned int us);
-void set_ddr_sel(int val);

package/boot/uboot-oxnas/src/board/ox820/lowlevel_init.S

@@ -1,20 +0,0 @@
-#include <config.h>
-#ifndef CONFIG_SPL_BUILD
-
-.globl lowlevel_init
-lowlevel_init:
-	/*
-	 * Copy exception table to relocated address in internal SRAM
-	 */
-	ldr	r0, src		/* Address of exception table in flash */
-	ldr	r1, dest	/* Relocated address of exception table */
-	ldmia	r0!, {r3-r10}	/* Copy exception table and jump values from */
-	stmia	r1!, {r3-r10}	/* FLASH to relocated address */
-	ldmia	r0!, {r3-r10}
-	stmia	r1!, {r3-r10}
-	mov	pc, lr
-
-src:	.word CONFIG_SYS_TEXT_BASE
-dest:	.word CONFIG_SRAM_BASE
-
-#endif

package/boot/uboot-oxnas/src/board/ox820/ox820.c

@@ -1,374 +0,0 @@
-#include <common.h>
-#include <spl.h>
-#include <phy.h>
-#include <netdev.h>
-#include <ide.h>
-#include <nand.h>
-#include <asm/arch/spl.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sysctl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SPL_BUILD
-
-#ifdef DEBUG
-#define DILIGENCE (1048576/4)
-static int test_memory(u32 memory)
-{
-	volatile u32 *read;
-	volatile u32 *write;
-	const u32 INIT_PATTERN = 0xAA55AA55;
-	const u32 INC_PATTERN = 0x01030507;
-	u32 pattern;
-	int check;
-	int i;
-
-	check = 0;
-	read = write = (volatile u32 *) memory;
-	pattern = INIT_PATTERN;
-	for (i = 0; i < DILIGENCE; i++) {
-		*write++ = pattern;
-		pattern += INC_PATTERN;
-	}
-	puts("testing\n");
-	pattern = INIT_PATTERN;
-	for (i = 0; i < DILIGENCE; i++) {
-		check += (pattern == *read++) ? 1 : 0;
-		pattern += INC_PATTERN;
-	}
-	return (check == DILIGENCE) ? 0 : -1;
-}
-#endif
-
-void uart_init(void)
-{
-	/* Reset UART1 */
-	reset_block(SYS_CTRL_RST_UART1, 1);
-	udelay(100);
-	reset_block(SYS_CTRL_RST_UART1, 0);
-	udelay(100);
-
-	/* Setup pin mux'ing for UART1 */
-	pinmux_set(PINMUX_BANK_MFA, 30, PINMUX_UARTA_SIN);
-	pinmux_set(PINMUX_BANK_MFA, 31, PINMUX_UARTA_SOUT);
-}
-
-extern void init_ddr(int mhz);
-
-void board_inithw(void)
-{
-	int plla_freq;
-#ifdef DEBUG
-	int i;
-#endif	/* DEBUG */
-
-	timer_init();
-	uart_init();
-	preloader_console_init();
-
-	plla_freq = plla_set_config(CONFIG_PLLA_FREQ_MHZ);
-	init_ddr(plla_freq);
-
-#ifdef DEBUG
-	if(test_memory(CONFIG_SYS_SDRAM_BASE)) {
-		puts("memory test failed\n");
-	} else {
-		puts("memory test done\n");
-	}
-#endif /* DEBUG */
-#ifdef CONFIG_SPL_BSS_DRAM_START
-	extern char __bss_dram_start[];
-	extern char __bss_dram_end[];
-	memset(&__bss_dram_start, 0, __bss_dram_end - __bss_dram_start);
-#endif
-}
-
-void board_init_f(ulong dummy)
-{
-	/* Set the stack pointer. */
-	asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
-
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	/* Set global data pointer. */
-	gd = &gdata;
-
-	board_inithw();
-
-	board_init_r(NULL, 0);
-}
-
-u32 spl_boot_device(void)
-{
-	return CONFIG_SPL_BOOT_DEVICE;
-}
-
-#ifdef CONFIG_SPL_BLOCK_SUPPORT
-void spl_block_device_init(void)
-{
-	ide_init();
-}
-#endif
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
-        /* break into full u-boot on 'c' */
-        return (serial_tstc() && serial_getc() == 'c');
-}
-#endif
-
-void spl_display_print(void)
-{
-	/* print a hint, so that we will not use the wrong SPL by mistake */
-	puts("  Boot device: " BOOT_DEVICE_TYPE "\n" );
-}
-
-void lowlevel_init(void)
-{
-}
-
-#ifdef USE_DL_PREFIX
-/* quick and dirty memory allocation */
-static ulong next_mem = CONFIG_SPL_MALLOC_START;
-
-void *memalign(size_t alignment, size_t bytes)
-{
-	ulong mem = ALIGN(next_mem, alignment);
-
-	next_mem = mem + bytes;
-
-	if (next_mem > CONFIG_SYS_SDRAM_BASE + CONFIG_MIN_SDRAM_SIZE) {
-		printf("spl: out of memory\n");
-		hang();
-	}
-
-	return (void *)mem;
-}
-
-void free(void* mem)
-{
-}
-#endif
-
-#endif /* CONFIG_SPL_BUILD */
-
-int board_early_init_f(void)
-{
-	return 0;
-}
-
-#define STATIC_CTL_BANK0		(STATIC_CONTROL_BASE + 4)
-#define STATIC_READ_CYCLE_SHIFT		0
-#define STATIC_DELAYED_OE		(1 << 7)
-#define STATIC_WRITE_CYCLE_SHIFT	8
-#define STATIC_WRITE_PULSE_SHIFT	16
-#define STATIC_WRITE_BURST_EN		(1 << 23)
-#define STATIC_TURN_AROUND_SHIFT	24
-#define STATIC_BUFFER_PRESENT		(1 << 28)
-#define STATIC_READ_BURST_EN		(1 << 29)
-#define STATIC_BUS_WIDTH8		(0 << 30)
-#define STATIC_BUS_WIDTH16		(1 << 30)
-#define STATIC_BUS_WIDTH32		(2 << 30)
-
-void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	struct nand_chip *this = mtd->priv;
-	unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
-
-	if (ctrl & NAND_CTRL_CHANGE) {
-		nandaddr &= ~(BIT(NAND_ALE_ADDR_PIN) | BIT(NAND_CLE_ADDR_PIN));
-		if (ctrl & NAND_CLE)
-			nandaddr |= BIT(NAND_CLE_ADDR_PIN);
-		else if (ctrl & NAND_ALE)
-			nandaddr |= BIT(NAND_ALE_ADDR_PIN);
-		this->IO_ADDR_W = (void __iomem *) nandaddr;
-	}
-
-	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, (void __iomem *) nandaddr);
-}
-
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOOT_FROM_NAND)
-
-int nand_dev_ready(struct mtd_info *mtd)
-{
-	struct nand_chip *chip = mtd->priv;
-
-	udelay(chip->chip_delay);
-
-	return 1;
-}
-
-void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
-	int i;
-	struct nand_chip *chip = mtd->priv;
-
-	for (i = 0; i < len; i++)
-		buf[i] = readb(chip->IO_ADDR_R);
-}
-
-void nand_dev_reset(struct nand_chip *chip)
-{
-	writeb(NAND_CMD_RESET, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));
-	udelay(chip->chip_delay);
-	writeb(NAND_CMD_STATUS, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));
-	while (!(readb(chip->IO_ADDR_R) & NAND_STATUS_READY)) {
-		;
-	}
-}
-
-#else
-
-#define nand_dev_reset(chip)	/* framework will reset the chip anyway */
-#define nand_read_buf		NULL /* framework will provide a default one */
-#define nand_dev_ready		NULL /* dev_ready is optional */
-
-#endif
-
-int board_nand_init(struct nand_chip *chip)
-{
-	/* Block reset Static core */
-	reset_block(SYS_CTRL_RST_STATIC, 1);
-	reset_block(SYS_CTRL_RST_STATIC, 0);
-
-	/* Enable clock to Static core */
-	enable_clock(SYS_CTRL_CLK_STATIC);
-
-	/* enable flash support on static bus.
-	 * Enable static bus onto GPIOs, only CS0 */
-	pinmux_set(PINMUX_BANK_MFA, 12, PINMUX_STATIC_DATA0);
-	pinmux_set(PINMUX_BANK_MFA, 13, PINMUX_STATIC_DATA1);
-	pinmux_set(PINMUX_BANK_MFA, 14, PINMUX_STATIC_DATA2);
-	pinmux_set(PINMUX_BANK_MFA, 15, PINMUX_STATIC_DATA3);
-	pinmux_set(PINMUX_BANK_MFA, 16, PINMUX_STATIC_DATA4);
-	pinmux_set(PINMUX_BANK_MFA, 17, PINMUX_STATIC_DATA5);
-	pinmux_set(PINMUX_BANK_MFA, 18, PINMUX_STATIC_DATA6);
-	pinmux_set(PINMUX_BANK_MFA, 19, PINMUX_STATIC_DATA7);
-
-	pinmux_set(PINMUX_BANK_MFA, 20, PINMUX_STATIC_NWE);
-	pinmux_set(PINMUX_BANK_MFA, 21, PINMUX_STATIC_NOE);
-	pinmux_set(PINMUX_BANK_MFA, 22, PINMUX_STATIC_NCS);
-	pinmux_set(PINMUX_BANK_MFA, 23, PINMUX_STATIC_ADDR18);
-	pinmux_set(PINMUX_BANK_MFA, 24, PINMUX_STATIC_ADDR19);
-
-	/* Setup the static bus CS0 to access FLASH */
-
-	writel((0x3f << STATIC_READ_CYCLE_SHIFT)
-			| (0x3f << STATIC_WRITE_CYCLE_SHIFT)
-			| (0x1f << STATIC_WRITE_PULSE_SHIFT)
-			| (0x03 << STATIC_TURN_AROUND_SHIFT) |
-			STATIC_BUS_WIDTH16,
-		STATIC_CTL_BANK0);
-
-	chip->cmd_ctrl = nand_hwcontrol;
-	chip->ecc.mode = NAND_ECC_SOFT;
-	chip->chip_delay = 30;
-	chip->dev_ready = nand_dev_ready;
-	chip->read_buf = nand_read_buf;
-
-	nand_dev_reset(chip);
-
-	return 0;
-}
-
-int board_init(void)
-{
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-	gd->bd->bi_arch_number = MACH_TYPE_OXNAS;
-
-	/* assume uart is already initialized by SPL */
-
-#if defined(CONFIG_START_IDE)
-	puts("IDE:   ");
-	ide_init();
-#endif
-
-	return 0;
-}
-
-/* copied from board/evb64260/sdram_init.c */
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-static long int dram_size (long int *base, long int maxsize)
-{
-	volatile long int *addr, *b = base;
-	long int cnt, val, save1, save2;
-
-#define STARTVAL (CONFIG_MIN_SDRAM_SIZE / 2)	/* start test at half size */
-	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
-	     cnt <<= 1) {
-		addr = base + cnt;	/* pointer arith! */
-
-		save1 = *addr;	/* save contents of addr */
-		save2 = *b;	/* save contents of base */
-
-		*addr = cnt;	/* write cnt to addr */
-		*b = 0;		/* put null at base */
-
-		/* check at base address */
-		if ((*b) != 0) {
-			*addr = save1;	/* restore *addr */
-			*b = save2;	/* restore *b */
-			return (0);
-		}
-		val = *addr;	/* read *addr */
-
-		*addr = save1;
-		*b = save2;
-
-		if (val != cnt) {
-			/* fix boundary condition.. STARTVAL means zero */
-			if (cnt == STARTVAL / sizeof (long))
-				cnt = 0;
-			return (cnt * sizeof (long));
-		}
-	}
-	return maxsize;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = dram_size((long int *)CONFIG_SYS_SDRAM_BASE,
-					CONFIG_MAX_SDRAM_SIZE);
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	u32 value;
-
-	/* set the pin multiplexers to enable talking to Ethernent Phys */
-	pinmux_set(PINMUX_BANK_MFA, 3, PINMUX_MACA_MDC);
-	pinmux_set(PINMUX_BANK_MFA, 4, PINMUX_MACA_MDIO);
-
-	// Ensure the MAC block is properly reset
-	reset_block(SYS_CTRL_RST_MAC, 1);
-	udelay(10);
-	reset_block(SYS_CTRL_RST_MAC, 0);
-
-	// Enable the clock to the MAC block
-	enable_clock(SYS_CTRL_CLK_MAC);
-
-	value = readl(SYS_CTRL_GMAC_CTRL);
-	/* Use simple mux for 25/125 Mhz clock switching */
-	value |= BIT(SYS_CTRL_GMAC_SIMPLE_MUX);
-	/* Enable GMII_GTXCLK to follow GMII_REFCLK - required for gigabit PHY */
-	value |= BIT(SYS_CTRL_GMAC_CKEN_GTX);
-	/* set auto tx speed */
-	value |= BIT(SYS_CTRL_GMAC_AUTOSPEED);
-
-	writel(value, SYS_CTRL_GMAC_CTRL);
-
-	return designware_initialize(MAC_BASE, PHY_INTERFACE_MODE_RGMII);
-}
-

package/boot/uboot-oxnas/src/board/ox820/spl_start.S

@@ -1,21 +0,0 @@
-.section .init
-.globl _spl_start
-_spl_start:
-	b	_start
-	b	_start+0x4
-	b	_start+0x8
-	b	_start+0xc
-	b	_start+0x10
-	b	_start+0x14
-	b	_start+0x18
-	b	_start+0x1c
-	.space	0x30 - (. - _spl_start)
-	.ascii	"BOOT"		/* 0x30 signature*/
-	.word	0x50		/* 0x34 header size itself */
-	.word	0		/* 0x38 */
-	.word	0x5000f000	/* boot report location */
-	.word	_start		/* 0x40 */
-
-main_crc_size:	.word	code_size	/* 0x44 filled by linker */
-main_crc:	.word	0		/* 0x48 fill later */
-header_crc:	.word	0		/* 0x4C header crc*/

package/boot/uboot-oxnas/src/board/ox820/u-boot-spl.lds

@@ -1,101 +0,0 @@
-/*
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-MEMORY
-{
-	 sram (rwx) : ORIGIN = CONFIG_SPL_TEXT_BASE, LENGTH = CONFIG_SPL_MAX_SIZE
-	 dram : ORIGIN = CONFIG_SPL_BSS_DRAM_START, LENGTH = CONFIG_SPL_BSS_DRAM_SIZE
-}
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_spl_start)
-SECTIONS
-{
-	.text.0	:
-	{
-		*(.init*)
-	}
-
-
-	/* Start of the rest of the SPL */
-	code_start = . ;
-
-	.text.1	:
-	{
-		*(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data*)
-	}
-
-	. = ALIGN(4);
-
-	__image_copy_end = .;
-	code_size = . - code_start;
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	. = ALIGN(0x800);
-
-	_end = .;
-
-	.bss.sram __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss.stdio_devices)
-		*(.bss.serial_current)
-		 . = ALIGN(4);
-		__bss_end = .;
-	}
-
-	.bss : {
-		__bss_dram_start = .;
-		*(.bss*)
-		__bss_dram_end = .;
-	} > dram
-
-	/DISCARD/ : { *(.bss*) }
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynsym*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.hash*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}

package/boot/uboot-oxnas/src/common/env_ext4.c

@@ -1,116 +0,0 @@
-/*
- * (c) Copyright 2011 by Tigris Elektronik GmbH
- *
- * Author:
- *  Maximilian Schwerin <mvs@tigris.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#include <command.h>
-#include <environment.h>
-#include <linux/stddef.h>
-#include <malloc.h>
-#include <search.h>
-#include <errno.h>
-#include <ext4fs.h>
-
-char *env_name_spec = "EXT4";
-
-env_t *env_ptr;
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int env_init(void)
-{
-	/* use default */
-	gd->env_addr = (ulong)&default_environment[0];
-	gd->env_valid = 1;
-
-	return 0;
-}
-
-#ifdef CONFIG_CMD_SAVEENV
-int saveenv(void)
-{
-	env_t	env_new;
-	ssize_t	len;
-	char	*res;
-	block_dev_desc_t *dev_desc = NULL;
-	int dev = EXT4_ENV_DEVICE;
-	int part = EXT4_ENV_PART;
-	int err;
-
-	res = (char *)&env_new.data;
-	len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
-	if (len < 0) {
-		error("Cannot export environment: errno = %d\n", errno);
-		return 1;
-	}
-
-	dev_desc = get_dev(EXT4_ENV_INTERFACE, dev);
-	if (dev_desc == NULL) {
-		printf("Failed to find %s%d\n",
-			EXT4_ENV_INTERFACE, dev);
-		return 1;
-	}
-
-	err = ext4_register_device(dev_desc, part);
-	if (err) {
-		printf("Failed to register %s%d:%d\n",
-			EXT4_ENV_INTERFACE, dev, part);
-		return 1;
-	}
-
-	env_new.crc = crc32(0, env_new.data, ENV_SIZE);
-	err = ext4fs_write(EXT4_ENV_FILE, (void *)&env_new, sizeof(env_t));
-	ext4fs_close();
-	if (err == -1) {
-		printf("\n** Unable to write \"%s\" from %s%d:%d **\n",
-			EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part);
-		return 1;
-	}
-
-	puts("done\n");
-	return 0;
-}
-#endif /* CONFIG_CMD_SAVEENV */
-
-void env_relocate_spec(void)
-{
-	char buf[CONFIG_ENV_SIZE];
-	block_dev_desc_t *dev_desc = NULL;
-	int dev = EXT4_ENV_DEVICE;
-	int part = EXT4_ENV_PART;
-	int err;
-
-	dev_desc = get_dev(EXT4_ENV_INTERFACE, dev);
-	if (dev_desc == NULL) {
-		printf("Failed to find %s%d\n",
-			EXT4_ENV_INTERFACE, dev);
-		set_default_env(NULL);
-		return;
-	}
-
-	err = ext4_register_device(dev_desc, part);
-	if (err) {
-		printf("Failed to register %s%d:%d\n",
-			EXT4_ENV_INTERFACE, dev, part);
-		set_default_env(NULL);
-		return;
-	}
-
-	err = ext4_read_file(EXT4_ENV_FILE, (uchar *)&buf, 0, CONFIG_ENV_SIZE);
-	ext4fs_close();
-
-	if (err == -1) {
-		printf("\n** Unable to read \"%s\" from %s%d:%d **\n",
-			EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part);
-		set_default_env(NULL);
-		return;
-	}
-
-	env_import(buf, 1);
-}

package/boot/uboot-oxnas/src/common/spl/spl_block.c

@@ -1,236 +0,0 @@
-/*
- * (C) Copyright 2013
- *
- * Ma Haijun <mahaijuns@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <spl.h>
-#include <asm/u-boot.h>
-#include <asm/utils.h>
-#include <version.h>
-#include <part.h>
-#include <fat.h>
-#include <ext4fs.h>
-
-/* should be implemented by board */
-extern void spl_block_device_init(void);
-
-block_dev_desc_t * spl_get_block_device(void)
-{
-	block_dev_desc_t * device;
-
-	spl_block_device_init();
-
-	device = get_dev(CONFIG_SPL_BLOCKDEV_INTERFACE, CONFIG_SPL_BLOCKDEV_ID);
-	if (!device) {
-		printf("blk device %s%d not exists\n",
-			CONFIG_SPL_BLOCKDEV_INTERFACE,
-			CONFIG_SPL_BLOCKDEV_ID);
-		hang();
-	}
-
-	return device;
-}
-
-#ifdef CONFIG_SPL_FAT_SUPPORT
-static int block_load_image_fat(const char *filename)
-{
-	int err;
-	struct image_header *header;
-
-	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
-						sizeof(struct image_header));
-
-	err = file_fat_read(filename, header, sizeof(struct image_header));
-	if (err <= 0)
-		goto end;
-
-	spl_parse_image_header(header);
-
-	err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
-
-end:
-	if (err <= 0)
-		printf("spl: error reading image %s, err - %d\n",
-		       filename, err);
-
-	return (err <= 0);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-static int block_load_image_fat_os(void)
-{
-	int err;
-
-	err = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME,
-			    (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
-	if (err <= 0) {
-		return -1;
-	}
-
-	return block_load_image_fat(CONFIG_SPL_FAT_LOAD_KERNEL_NAME);
-}
-#endif
-
-void spl_block_load_image(void)
-{
-	int err;
-	block_dev_desc_t * device;
-
-	device = spl_get_block_device();
-	err = fat_register_device(device, CONFIG_BLOCKDEV_FAT_BOOT_PARTITION);
-	if (err) {
-		printf("spl: fat register err - %d\n", err);
-		hang();
-	}
-#ifdef CONFIG_SPL_OS_BOOT
-	if (spl_start_uboot() || block_load_image_fat_os())
-#endif
-	{
-		err = block_load_image_fat(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
-		if (err)
-			hang();
-	}
-}
-#elif defined(CONFIG_SPL_EXT4_SUPPORT) /* end CONFIG_SPL_FAT_SUPPORT */
-static int block_load_image_ext4(const char *filename)
-{
-	int err;
-	struct image_header *header;
-
-	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
-						sizeof(struct image_header));
-
-	err = ext4_read_file(filename, header, 0, sizeof(struct image_header));
-	if (err <= 0)
-		goto end;
-
-	spl_parse_image_header(header);
-
-	err = ext4_read_file(filename, (u8 *)spl_image.load_addr, 0, 0);
-
-end:
-	return (err <= 0);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-static int block_load_image_ext4_os(void)
-{
-	int err;
-
-	err = ext4_read_file(CONFIG_SPL_EXT4_LOAD_ARGS_NAME,
-			    (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0, 0);
-	if (err <= 0) {
-		return -1;
-	}
-
-	return block_load_image_ext4(CONFIG_SPL_EXT4_LOAD_KERNEL_NAME);
-}
-#endif
-
-void spl_block_load_image(void)
-{
-	int err;
-	block_dev_desc_t * device;
-
-	device = spl_get_block_device();
-	err = ext4_register_device(device, CONFIG_BLOCKDEV_EXT4_BOOT_PARTITION);
-	if (err) {
-		hang();
-	}
-#ifdef CONFIG_SPL_OS_BOOT
-	if (spl_start_uboot() || block_load_image_ext4_os())
-#endif
-	{
-		err = block_load_image_ext4(CONFIG_SPL_EXT4_LOAD_PAYLOAD_NAME);
-		if (err)
-			hang();
-	}
-}
-#else /* end CONFIG_SPL_EXT4_SUPPORT */
-static int block_load_image_raw(block_dev_desc_t * device, lbaint_t sector)
-{
-	int n;
-	u32 image_size_sectors;
-	struct image_header *header;
-
-	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
-						sizeof(struct image_header));
-
-	/* read image header to find the image size & load address */
-	n = device->block_read(device->dev, sector, 1, header);
-
-	if (n != 1) {
-		printf("spl: blk read err\n");
-		return 1;
-	}
-
-	spl_parse_image_header(header);
-
-	/* convert size to sectors - round up */
-	image_size_sectors = (spl_image.size + 512 - 1) / 512;
-	n = device->block_read(device->dev, sector, image_size_sectors,
-					(void *)spl_image.load_addr);
-
-	if (n != image_size_sectors) {
-		printf("spl: blk read err\n");
-		return 1;
-	}
-	return 0;
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-static int block_load_image_raw_os(block_dev_desc_t * device)
-{
-	int n;
-
-	n = device->block_read(device->dev, CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTOR,
-					CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS,
-					(u32 *)CONFIG_SYS_SPL_ARGS_ADDR);
-	/* flush cache after read */
-	flush_cache(addr, CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS * 512);
-
-	if (n != CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS) {
-		printf("args blk read error\n");
-		return -1;
-	}
-
-	return block_load_image_raw(device, CONFIG_SYS_BLOCK_RAW_MODE_KERNEL_SECTOR);
-}
-#endif
-
-void spl_block_load_image(void)
-{
-	int err;
-	block_dev_desc_t * device;
-
-	device = spl_get_block_device();
-#ifdef CONFIG_SPL_OS_BOOT
-	if (spl_start_uboot() || block_load_image_raw_os(device))
-#endif
-	{
-		err = block_load_image_raw(device,
-					 CONFIG_SYS_BLOCK_RAW_MODE_U_BOOT_SECTOR);
-		if (err)
-			hang();
-	}
-}
-#endif /* CONFIG_SPL_FAT_SUPPORT */