Browse Source

Fresh pull from upstream lede-17.01 branch @ commit d77fe9219af17dce2d00147d904267d4489ae841

RISCi_ATOM 2 years ago
parent
commit
f6b96b2052
100 changed files with 3066 additions and 6531 deletions
  1. 5 0
      include/host-build.mk
  2. 2 4
      include/kernel-version.mk
  3. 13 10
      include/kernel.mk
  4. 1 1
      include/prereq-build.mk
  5. 2 0
      include/site/darwin
  6. 2 7
      include/target.mk
  7. 3 3
      package/base-files/Makefile
  8. 1 1
      package/base-files/files/bin/config_generate
  9. 1 1
      package/base-files/files/etc/init.d/system
  10. 1 1
      package/base-files/files/lib/functions.sh
  11. 1 1
      package/base-files/files/usr/lib/os-release
  12. 0 0
      package/boot/uboot-envtools/files/ipq
  13. 0 88
      package/boot/uboot-xburst/Makefile
  14. 0 894
      package/boot/uboot-xburst/patches/0001-qi_lb60-add-nand-spl-support.patch
  15. 0 916
      package/boot/uboot-xburst/patches/0002-qi_lb60-add-software-usbboot-support.patch
  16. 0 1664
      package/boot/uboot-xburst/patches/0003-add-mmc-support.patch
  17. 0 200
      package/boot/uboot-xburst/patches/0004-add-more-boot-options-F1-F2-F3-F4-M-S.patch
  18. 0 847
      package/boot/uboot-xburst/patches/0005-add-nanonote-lcd-support.patch
  19. 0 60
      package/boot/uboot-xburst/patches/0006-enable-silent-console.patch
  20. 1 0
      package/kernel/linux/modules/netdevices.mk
  21. 19 12
      package/kernel/mac80211/files/regdb.txt
  22. 1 9
      package/kernel/om-watchdog/Makefile
  23. 40 31
      package/kernel/om-watchdog/files/om-watchdog.init
  24. 3 3
      package/libs/uclient/Makefile
  25. 0 5
      package/luci/.buildpath
  26. 0 221
      package/luci/.cproject
  27. 0 78
      package/luci/.project
  28. 0 62
      package/luci/CONTRIBUTING.md
  29. 0 34
      package/luci/README.md
  30. 0 26
      package/luci/THANKYOU
  31. 42 37
      package/luci/applications/luci-app-adblock/luasrc/model/cbi/adblock/overview_tab.lua
  32. 3 0
      package/luci/applications/luci-app-adblock/luasrc/view/adblock/config_css.htm
  33. 95 36
      package/luci/applications/luci-app-adblock/po/it/adblock.po
  34. 53 36
      package/luci/applications/luci-app-adblock/po/ja/adblock.po
  35. 56 24
      package/luci/applications/luci-app-adblock/po/pt-br/adblock.po
  36. 70 33
      package/luci/applications/luci-app-adblock/po/sv/adblock.po
  37. 32 18
      package/luci/applications/luci-app-adblock/po/templates/adblock.pot
  38. 134 62
      package/luci/applications/luci-app-adblock/po/zh-cn/adblock.po
  39. 455 0
      package/luci/applications/luci-app-adblock/po/zh-tw/adblock.po
  40. 9 8
      package/luci/applications/luci-app-advanced-reboot/po/sv/luci-app-advanced-reboot.po
  41. 142 121
      package/luci/applications/luci-app-aria2/po/zh-cn/aria2.po
  42. 221 0
      package/luci/applications/luci-app-aria2/po/zh-tw/aria2.po
  43. 1 1
      package/luci/applications/luci-app-attendedsysupgrade/Makefile
  44. 375 231
      package/luci/applications/luci-app-attendedsysupgrade/luasrc/view/attendedsysupgrade.htm
  45. 6 0
      package/luci/applications/luci-app-attendedsysupgrade/root/etc/uci-defaults/40_luci-attendedsysupgrade
  46. 31 0
      package/luci/applications/luci-app-attendedsysupgrade/root/usr/share/rpcd/acl.d/attendedsysupgrade.json
  47. 3 3
      package/luci/applications/luci-app-bcp38/po/zh-cn/bcp38.po
  48. 52 0
      package/luci/applications/luci-app-bcp38/po/zh-tw/bcp38.po
  49. 1 1
      package/luci/applications/luci-app-commands/po/zh-tw/commands.po
  50. 1 1
      package/luci/applications/luci-app-ddns/po/it/ddns.po
  51. 144 129
      package/luci/applications/luci-app-ddns/po/zh-cn/ddns.po
  52. 250 206
      package/luci/applications/luci-app-ddns/po/zh-tw/ddns.po
  53. 3 3
      package/luci/applications/luci-app-diag-core/po/zh-tw/diag_core.po
  54. 8 8
      package/luci/applications/luci-app-diag-devinfo/po/sv/diag_devinfo.po
  55. 9 3
      package/luci/applications/luci-app-dnscrypt-proxy/luasrc/controller/dnscrypt-proxy.lua
  56. 2 0
      package/luci/applications/luci-app-dnscrypt-proxy/luasrc/model/cbi/dnscrypt-proxy/cfg_dnsmasq_tab.lua
  57. 39 0
      package/luci/applications/luci-app-dnscrypt-proxy/luasrc/model/cbi/dnscrypt-proxy/cfg_resolvcrypt_tab.lua
  58. 130 62
      package/luci/applications/luci-app-dnscrypt-proxy/luasrc/model/cbi/dnscrypt-proxy/overview_tab.lua
  59. 82 35
      package/luci/applications/luci-app-dnscrypt-proxy/po/ja/dnscrypt-proxy.po
  60. 59 22
      package/luci/applications/luci-app-dnscrypt-proxy/po/templates/dnscrypt-proxy.pot
  61. 12 4
      package/luci/applications/luci-app-firewall/po/zh-cn/firewall.po
  62. 137 144
      package/luci/applications/luci-app-firewall/po/zh-tw/firewall.po
  63. 3 3
      package/luci/applications/luci-app-freifunk-policyrouting/po/zh-cn/freifunk-policyrouting.po
  64. 1 0
      package/luci/applications/luci-app-fwknopd/root/etc/uci-defaults/40_luci-fwknopd
  65. 9 9
      package/luci/applications/luci-app-fwknopd/root/usr/sbin/gen-qr.sh
  66. 3 3
      package/luci/applications/luci-app-meshwizard/po/zh-cn/meshwizard.po
  67. 5 1
      package/luci/applications/luci-app-minidlna/luasrc/model/cbi/minidlna.lua
  68. 8 1
      package/luci/applications/luci-app-minidlna/po/ca/minidlna.po
  69. 8 1
      package/luci/applications/luci-app-minidlna/po/cs/minidlna.po
  70. 8 1
      package/luci/applications/luci-app-minidlna/po/de/minidlna.po
  71. 8 1
      package/luci/applications/luci-app-minidlna/po/el/minidlna.po
  72. 9 2
      package/luci/applications/luci-app-minidlna/po/en/minidlna.po
  73. 10 3
      package/luci/applications/luci-app-minidlna/po/es/minidlna.po
  74. 8 1
      package/luci/applications/luci-app-minidlna/po/fr/minidlna.po
  75. 8 1
      package/luci/applications/luci-app-minidlna/po/he/minidlna.po
  76. 9 2
      package/luci/applications/luci-app-minidlna/po/hu/minidlna.po
  77. 14 9
      package/luci/applications/luci-app-minidlna/po/it/minidlna.po
  78. 20 10
      package/luci/applications/luci-app-minidlna/po/ja/minidlna.po
  79. 8 1
      package/luci/applications/luci-app-minidlna/po/ms/minidlna.po
  80. 12 5
      package/luci/applications/luci-app-minidlna/po/no/minidlna.po
  81. 10 3
      package/luci/applications/luci-app-minidlna/po/pl/minidlna.po
  82. 10 3
      package/luci/applications/luci-app-minidlna/po/pt-br/minidlna.po
  83. 8 1
      package/luci/applications/luci-app-minidlna/po/pt/minidlna.po
  84. 8 1
      package/luci/applications/luci-app-minidlna/po/ro/minidlna.po
  85. 10 3
      package/luci/applications/luci-app-minidlna/po/ru/minidlna.po
  86. 8 1
      package/luci/applications/luci-app-minidlna/po/sk/minidlna.po
  87. 8 1
      package/luci/applications/luci-app-minidlna/po/sv/minidlna.po
  88. 8 1
      package/luci/applications/luci-app-minidlna/po/templates/minidlna.pot
  89. 8 1
      package/luci/applications/luci-app-minidlna/po/tr/minidlna.po
  90. 8 1
      package/luci/applications/luci-app-minidlna/po/uk/minidlna.po
  91. 8 1
      package/luci/applications/luci-app-minidlna/po/vi/minidlna.po
  92. 12 4
      package/luci/applications/luci-app-minidlna/po/zh-cn/minidlna.po
  93. 8 1
      package/luci/applications/luci-app-minidlna/po/zh-tw/minidlna.po
  94. 5 5
      package/luci/applications/luci-app-mwan3/luasrc/model/cbi/mwan/interface.lua
  95. 5 5
      package/luci/applications/luci-app-mwan3/luasrc/model/cbi/mwan/interfaceconfig.lua
  96. 1 1
      package/luci/applications/luci-app-mwan3/luasrc/model/cbi/mwan/policyconfig.lua
  97. 1 1
      package/luci/applications/luci-app-mwan3/luasrc/model/cbi/mwan/rule.lua
  98. 1 1
      package/luci/applications/luci-app-mwan3/luasrc/model/cbi/mwan/ruleconfig.lua
  99. 18 18
      package/luci/applications/luci-app-mwan3/po/ja/mwan3.po
  100. 17 17
      package/luci/applications/luci-app-mwan3/po/templates/mwan3.pot

+ 5 - 0
include/host-build.mk

@@ -77,6 +77,10 @@ HOST_MAKE_FLAGS =
 
 HOST_CONFIGURE_CMD = $(BASH) ./configure
 
+ifeq ($(HOST_OS),Darwin)
+  HOST_CONFIG_SITE:=$(INCLUDE_DIR)/site/darwin
+endif
+
 define Host/Configure/Default
 	$(if $(HOST_CONFIGURE_PARALLEL),+)(cd $(HOST_BUILD_DIR)/$(3); \
 		if [ -x configure ]; then \
@@ -127,6 +131,7 @@ define Host/Exports/Default
   $(1) : export PKG_CONFIG_PATH=$$(STAGING_DIR_HOST)/lib/pkgconfig:$$(HOST_BUILD_PREFIX)/lib/pkgconfig
   $(1) : export PKG_CONFIG_LIBDIR=$$(HOST_BUILD_PREFIX)/lib/pkgconfig
   $(1) : export CCACHE_DIR:=$(STAGING_DIR_HOST)/ccache
+  $(if $(HOST_CONFIG_SITE),$(1) : export CONFIG_SITE:=$(HOST_CONFIG_SITE))
   $(if $(IS_PACKAGE_BUILD),$(1) : export PATH=$$(TARGET_PATH_PKG))
 endef
 Host/Exports=$(Host/Exports/Default)

+ 2 - 4
include/kernel-version.mk

@@ -2,11 +2,9 @@
 
 LINUX_RELEASE?=1
 
-LINUX_VERSION-3.18 = .43
-LINUX_VERSION-4.4 = .87
+LINUX_VERSION-4.4 = .102
 
-LINUX_KERNEL_HASH-3.18.43 = 1236e8123a6ce537d5029232560966feed054ae31776fe8481dd7d18cdd5492c
-LINUX_KERNEL_HASH-4.4.87 = f2e26505e3aecf622d4f4e1ede44b3b97a38739ad8b78ede14eb354f22d1387a
+LINUX_KERNEL_HASH-4.4.102 = 67104295ed20d23291773b41fe4514e4b12f47351f8ca5f2bbfd87b3071a549a
 
 ifdef KERNEL_PATCHVER
   LINUX_VERSION:=$(KERNEL_PATCHVER)$(strip $(LINUX_VERSION-$(KERNEL_PATCHVER)))

+ 13 - 10
include/kernel.mk

@@ -59,7 +59,7 @@ else
   LINUX_SOURCE:=linux-libre-$(LINUX_VERSION)-gnu.tar.xz
   TESTING:=$(if $(findstring -rc,$(LINUX_VERSION)),/testing,)
   ifeq ($(call qstrip,$(CONFIG_EXTERNAL_KERNEL_TREE))$(call qstrip,$(CONFIG_KERNEL_GIT_CLONE_URI)),)
-      LINUX_SITE:=@KERNEL_LIBRE/$(LINUX_VERSION)-gnu$(TESTING)
+	LINUX_SITE:=@KERNEL_LIBRE/$(LINUX_VERSION)-gnu$(TESTING)
   endif
 
   ifneq ($(TARGET_BUILD),1)
@@ -95,15 +95,16 @@ define ModuleAutoLoad
 	$(SH_FUNC) \
 	export modules=; \
 	probe_module() { \
-		mods="$$$$$$$$1"; \
-		boot="$$$$$$$$2"; \
+		local mods="$$$$$$$$1"; \
+		local boot="$$$$$$$$2"; \
+		local mod; \
 		shift 2; \
-		for mod in $(sort $$$$$$$$mods); do \
+		for mod in $$$$$$$$mods; do \
 			mkdir -p $(2)/etc/modules.d; \
 			echo "$$$$$$$$mod" >> $(2)/etc/modules.d/$(1); \
 		done; \
 		if [ -e $(2)/etc/modules.d/$(1) ]; then \
-			if [ "$$$$$$$$boot" = "1" ]; then \
+			if [ "$$$$$$$$boot" = "1" -a ! -e $(2)/etc/modules-boot.d/$(1) ]; then \
 				mkdir -p $(2)/etc/modules-boot.d; \
 				ln -s ../modules.d/$(1) $(2)/etc/modules-boot.d/; \
 			fi; \
@@ -111,16 +112,17 @@ define ModuleAutoLoad
 		fi; \
 	}; \
 	add_module() { \
-		priority="$$$$$$$$1"; \
-		mods="$$$$$$$$2"; \
-		boot="$$$$$$$$3"; \
+		local priority="$$$$$$$$1"; \
+		local mods="$$$$$$$$2"; \
+		local boot="$$$$$$$$3"; \
+		local mod; \
 		shift 3; \
-		for mod in $(sort $$$$$$$$mods); do \
+		for mod in $$$$$$$$mods; do \
 			mkdir -p $(2)/etc/modules.d; \
 			echo "$$$$$$$$mod" >> $(2)/etc/modules.d/$$$$$$$$priority-$(1); \
 		done; \
 		if [ -e $(2)/etc/modules.d/$$$$$$$$priority-$(1) ]; then \
-			if [ "$$$$$$$$boot" = "1" ]; then \
+			if [ "$$$$$$$$boot" = "1" -a ! -e $(2)/etc/modules-boot.d/$$$$$$$$priority-$(1) ]; then \
 				mkdir -p $(2)/etc/modules-boot.d; \
 				ln -s ../modules.d/$$$$$$$$priority-$(1) $(2)/etc/modules-boot.d/; \
 			fi; \
@@ -129,6 +131,7 @@ define ModuleAutoLoad
 	}; \
 	$(3) \
 	if [ -n "$$$$$$$$modules" ]; then \
+		modules="$$$$$$$$(echo "$$$$$$$$modules" | tr ' ' '\n' | sort | uniq | paste -s -d' ' -)"; \
 		mkdir -p $(2)/etc/modules.d; \
 		mkdir -p $(2)/CONTROL; \
 		echo "#!/bin/sh" > $(2)/CONTROL/postinst-pkg; \

+ 1 - 1
include/prereq-build.mk

@@ -20,7 +20,7 @@ $(eval $(call TestHostCommand,working-make, \
 	$(MAKE) -v | grep -E 'Make (3\.8[1-9]|3\.9[0-9]|[4-9]\.)'))
 
 $(eval $(call TestHostCommand,case-sensitive-fs, \
-	libreCMC can only be built on a case-sensitive filesystem, \
+	LEDE can only be built on a case-sensitive filesystem, \
 	rm -f $(TMP_DIR)/test.*; touch $(TMP_DIR)/test.fs; \
 		test ! -f $(TMP_DIR)/test.FS))
 

+ 2 - 0
include/site/darwin

@@ -0,0 +1,2 @@
+ac_cv_func_futimens=no
+ac_cv_func_utimensat=no

+ 2 - 7
include/target.mk

@@ -13,18 +13,13 @@ __target_inc=1
 DEVICE_TYPE?=router
 
 # Default packages - the really basic set
-DEFAULT_PACKAGES:=base-files ca-bundle libmbedtls libustream-mbedtls libc libgcc busybox dropbear mtd uci opkg netifd fstools uclient-fetch logd
-
+DEFAULT_PACKAGES:=base-files libc libgcc busybox dropbear mtd uci opkg netifd fstools uclient-fetch logd
 # For nas targets
 DEFAULT_PACKAGES.nas:=block-mount fdisk lsblk mdadm
-
 # For router targets
-DEFAULT_PACKAGES.router:=dnsmasq iptables ip6tables ppp ppp-mod-pppoe ppp-mod-pppoa firewall odhcpd odhcp6c
+DEFAULT_PACKAGES.router:=dnsmasq iptables ip6tables ppp ppp-mod-pppoe firewall odhcpd odhcp6c
 DEFAULT_PACKAGES.bootloader:=
 
-# Small Router Targets
-DEFAULT_PACKAGES.small-router:=-ca-bundle -opkg -libmbedtls -libustream-mbedtls
-
 ifneq ($(DUMP),)
   all: dumpinfo
 endif

+ 3 - 3
package/base-files/Makefile

@@ -31,7 +31,7 @@ endif
 define Package/base-files
   SECTION:=base
   CATEGORY:=Base system
-  DEPENDS:=+netifd +libc +procd +jsonfilter +SIGNED_PACKAGES:usign +SIGNED_PACKAGES:librecmc-keyring +fstools +fwtool
+  DEPENDS:=+netifd +libc +procd +jsonfilter +SIGNED_PACKAGES:usign +SIGNED_PACKAGES:lede-keyring +fstools +fwtool
   TITLE:=Base filesystem for Lede
   URL:=http://openwrt.org/
   VERSION:=$(PKG_RELEASE)-$(REVISION)
@@ -75,9 +75,9 @@ define ImageConfigOptions
 	echo 'pi_init_cmd=$(if $(CONFIG_TARGET_INIT_CMD),$(CONFIG_TARGET_INIT_CMD),"/sbin/init")' >>$(1)/lib/preinit/00_preinit.conf
 	echo 'pi_init_suppress_stderr="$(CONFIG_TARGET_INIT_SUPPRESS_STDERR)"' >>$(1)/lib/preinit/00_preinit.conf
 	echo 'pi_ifname=$(if $(CONFIG_TARGET_PREINIT_IFNAME),$(CONFIG_TARGET_PREINIT_IFNAME),"")' >>$(1)/lib/preinit/00_preinit.conf
-	echo 'pi_ip=$(if $(CONFIG_TARGET_PREINIT_IP),$(CONFIG_TARGET_PREINIT_IP),"192.168.10.1")' >>$(1)/lib/preinit/00_preinit.conf
+	echo 'pi_ip=$(if $(CONFIG_TARGET_PREINIT_IP),$(CONFIG_TARGET_PREINIT_IP),"192.168.1.1")' >>$(1)/lib/preinit/00_preinit.conf
 	echo 'pi_netmask=$(if $(CONFIG_TARGET_PREINIT_NETMASK),$(CONFIG_TARGET_PREINIT_NETMASK),"255.255.255.0")' >>$(1)/lib/preinit/00_preinit.conf
-	echo 'pi_broadcast=$(if $(CONFIG_TARGET_PREINIT_BROADCAST),$(CONFIG_TARGET_PREINIT_BROADCAST),"192.168.10.255")' >>$(1)/lib/preinit/00_preinit.conf
+	echo 'pi_broadcast=$(if $(CONFIG_TARGET_PREINIT_BROADCAST),$(CONFIG_TARGET_PREINIT_BROADCAST),"192.168.1.255")' >>$(1)/lib/preinit/00_preinit.conf
 	echo 'pi_preinit_net_messages="$(CONFIG_TARGET_PREINIT_SHOW_NETMSG)"' >>$(1)/lib/preinit/00_preinit.conf
 	echo 'pi_preinit_no_failsafe_netmsg="$(CONFIG_TARGET_PREINIT_SUPPRESS_FAILSAFE_NETMSG)"' >>$(1)/lib/preinit/00_preinit.conf
 	echo 'pi_preinit_no_failsafe="$(CONFIG_TARGET_PREINIT_DISABLE_FAILSAFE)"' >>$(1)/lib/preinit/00_preinit.conf

+ 1 - 1
package/base-files/files/bin/config_generate

@@ -91,7 +91,7 @@ generate_network() {
 		static)
 			local ipad
 			case "$1" in
-				lan) ipad=${ipaddr:-"192.168.10.1"} ;;
+				lan) ipad=${ipaddr:-"192.168.1.1"} ;;
 				*) ipad=${ipaddr:-"192.168.$((addr_offset++)).1"} ;;
 			esac
 

+ 1 - 1
package/base-files/files/etc/init.d/system

@@ -7,7 +7,7 @@ USE_PROCD=1
 validate_system_section()
 {
 	uci_validate_section system system "${1}" \
-		'hostname:string:librecmc' \
+		'hostname:string:lede' \
 		'conloglevel:uinteger' \
 		'buffersize:uinteger' \
 		'timezone:string:UTC' \

+ 1 - 1
package/base-files/files/lib/functions.sh

@@ -240,7 +240,7 @@ default_postinst() {
 		[ -d /tmp/.uci ] || mkdir -p /tmp/.uci
 		for i in $(sed -ne 's!^/etc/uci-defaults/!!p' "/usr/lib/opkg/info/${pkgname}.list"); do (
 			cd /etc/uci-defaults
-			[ -f "$i" ] && . "$i" && rm -f "$i"
+			[ -f "$i" ] && . ./"$i" && rm -f "$i"
 		) done
 		uci commit
 	fi

+ 1 - 1
package/base-files/files/usr/lib/os-release

@@ -1,7 +1,7 @@
 NAME="%D"
 VERSION="%V, %N"
 ID="%d"
-ID_LIKE="librecmc openwrt"
+ID_LIKE="lede openwrt"
 PRETTY_NAME="%D %N %V"
 VERSION_ID="%v"
 HOME_URL="%m"

+ 0 - 0
package/boot/uboot-envtools/files/ipq


+ 0 - 88
package/boot/uboot-xburst/Makefile

@@ -1,88 +0,0 @@
-#
-# Copyright (C) 2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_NAME:=u-boot
-PKG_VERSION:=2012.10-rc2
-PKG_RELEASE:=1
-
-PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
-PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
-PKG_SOURCE_URL:= \
-	http://mirror2.openwrt.org/sources \
-	ftp://ftp.denx.de/pub/u-boot
-PKG_HASH:=6d094cafa7ecea8b671fbdcd21130b6a4f5744fc47dd263e101ed5d3629dffd4
-PKG_TARGETS:=bin
-
-PKG_LICENSE:=GPL-2.0 GPL-2.0+
-PKG_LICENSE_FILES:=Licenses/README
-
-include $(INCLUDE_DIR)/package.mk
-
-define uboot/Default
-  TITLE:=
-  CONFIG:=
-  IMAGE:=
-endef
-
-define uboot/qi_lb60
-  TITLE:=U-boot for the qi_lb60 board
-endef
-
-UBOOTS:=qi_lb60
-
-define Package/uboot/template
-define Package/uboot-xburst-$(1)
-  SECTION:=boot
-  CATEGORY:=Boot Loaders
-  DEPENDS:=@TARGET_xburst
-  TITLE:=$(2)
-  URL:=http://www.denx.de/wiki/UBoot/WebHome
-  VARIANT:=$(1)
-endef
-endef
-
-define BuildUbootPackage
-	$(eval $(uboot/Default))
-	$(eval $(uboot/$(1)))
-	$(call Package/uboot/template,$(1),$(TITLE))
-endef
-
-
-ifdef BUILD_VARIANT
-$(eval $(call uboot/$(BUILD_VARIANT)))
-UBOOT_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
-UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_VARIANT)-u-boot.bin)
-endif
-
-define Build/Configure
-	$(MAKE) -C $(PKG_BUILD_DIR) \
-		$(UBOOT_CONFIG)_config
-endef
-
-define Build/Compile
-	$(MAKE) -C $(PKG_BUILD_DIR) \
-		CROSS_COMPILE=$(TARGET_CROSS)
-endef
-
-define Package/uboot/install/template
-define Package/uboot-xburst-$(1)/install
-	$(CP) $(PKG_BUILD_DIR)/u-boot-xburst.bin $(BIN_DIR)/$(2)
-	rmdir $$(1)
-endef
-endef
-
-$(foreach u,$(UBOOTS), \
-	$(eval $(call Package/uboot/install/template,$(u),openwrt-$(BOARD)-$(u)-u-boot.bin)) \
-)
-
-$(foreach u,$(UBOOTS), \
-	$(eval $(call BuildUbootPackage,$(u))) \
-	$(eval $(call BuildPackage,uboot-xburst-$(u))) \
-)

+ 0 - 894
package/boot/uboot-xburst/patches/0001-qi_lb60-add-nand-spl-support.patch

@@ -1,894 +0,0 @@
-From 0329cf7965956a5a7044827e0ce88ae8d5150e54 Mon Sep 17 00:00:00 2001
-From: Xiangfu <xiangfu@openmobilefree.net>
-Date: Fri, 12 Oct 2012 09:46:58 +0800
-Subject: [PATCH 1/6] qi_lb60: add nand spl support
-
-  The JZ4740 CPU can load 8KB from two different addresses:
-   1. the normal area up to 8KB starting from NAND flash address 0x00000000
-   2. the backup area up to 8KB starting from NAND flash address 0x00002000
-
-Signed-off-by: Xiangfu <xiangfu@openmobilefree.net>
----
- Makefile                          |   12 +++
- arch/mips/cpu/xburst/Makefile     |    7 +-
- arch/mips/cpu/xburst/cpu.c        |    4 +
- arch/mips/cpu/xburst/jz4740.c     |   82 +++++++----------
- arch/mips/cpu/xburst/spl/Makefile |   47 ++++++++++
- arch/mips/cpu/xburst/spl/start.S  |   63 +++++++++++++
- board/qi/qi_lb60/Makefile         |    4 +
- board/qi/qi_lb60/qi_lb60-spl.c    |   30 +++++++
- board/qi/qi_lb60/qi_lb60.c        |    8 +-
- board/qi/qi_lb60/u-boot-spl.lds   |   61 +++++++++++++
- drivers/mtd/nand/jz4740_nand.c    |   39 ++++++++-
- include/configs/qi_lb60.h         |  175 ++++++++++++++++++-------------------
- 12 files changed, 386 insertions(+), 146 deletions(-)
- create mode 100644 arch/mips/cpu/xburst/spl/Makefile
- create mode 100644 arch/mips/cpu/xburst/spl/start.S
- create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c
- create mode 100644 board/qi/qi_lb60/u-boot-spl.lds
-
-diff --git a/Makefile b/Makefile
-index 34d9075..a22778e 100644
---- a/Makefile
-+++ b/Makefile
-@@ -393,6 +393,10 @@ ALL-y += $(obj)u-boot-nodtb-tegra.bin
- endif
- endif
- 
-+ifeq ($(CPU),xburst)
-+ALL-y += $(obj)u-boot-xburst.bin
-+endif
-+
- all:		$(ALL-y) $(SUBDIR_EXAMPLES)
- 
- $(obj)u-boot.dtb:	$(obj)u-boot
-@@ -506,6 +510,14 @@ $(obj)u-boot-nodtb-tegra.bin:	$(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
- endif
- endif
- 
-+ifeq ($(CPU),xburst)
-+$(obj)u-boot-xburst.bin:	$(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
-+	        dd if=$(obj)spl/u-boot-spl.bin of=$(obj)spl/u-boot-pad.bin conv=sync bs=8192 count=1
-+		dd if=$(obj)spl/u-boot-spl.bin of=$(obj)spl/u-boot-pad.bin conv=sync,notrunc oflag=append bs=8192 count=1
-+	        tr '\0' '\377' < /dev/zero | dd of=$(obj)spl/u-boot-pad.bin conv=sync,notrunc oflag=append bs=16384 count=1
-+	        cat $(obj)spl/u-boot-pad.bin u-boot.bin > $@
-+endif
-+
- ifeq ($(CONFIG_SANDBOX),y)
- GEN_UBOOT = \
- 		cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
-diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile
-index b1f2ae4..ec35e55 100644
---- a/arch/mips/cpu/xburst/Makefile
-+++ b/arch/mips/cpu/xburst/Makefile
-@@ -24,9 +24,12 @@ include $(TOPDIR)/config.mk
- 
- LIB	= $(obj)lib$(CPU).o
- 
-+COBJS-y	= cpu.o jz_serial.o
-+
-+ifneq ($(CONFIG_SPL_BUILD),y)
- START	= start.o
--SOBJS-y	=
--COBJS-y	= cpu.o timer.o jz_serial.o
-+COBJS-y += timer.o
-+endif
- 
- COBJS-$(CONFIG_JZ4740) += jz4740.o
- 
-diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
-index ddcbfaa..1432838 100644
---- a/arch/mips/cpu/xburst/cpu.c
-+++ b/arch/mips/cpu/xburst/cpu.c
-@@ -42,6 +42,8 @@
- 		:			\
- 		: "i" (op), "R" (*(unsigned char *)(addr)))
- 
-+#ifndef CONFIG_SPL_BUILD
-+
- void __attribute__((weak)) _machine_restart(void)
- {
- 	struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
-@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
- 		cache_op(Hit_Invalidate_D, addr);
- }
- 
-+#endif
-+
- void flush_icache_all(void)
- {
- 	u32 addr, t = 0;
-diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c
-index c0b9817..8816aa3 100644
---- a/arch/mips/cpu/xburst/jz4740.c
-+++ b/arch/mips/cpu/xburst/jz4740.c
-@@ -32,31 +32,19 @@ int disable_interrupts(void)
- 	return 0;
- }
- 
--/*
-- * PLL output clock = EXTAL * NF / (NR * NO)
-- * NF = FD + 2, NR = RD + 2
-- * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
-- */
- void pll_init(void)
- {
- 	struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
- 
--	register unsigned int cfcr, plcr1;
--	int n2FR[33] = {
--		0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
--		7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
--		9
--	};
--	int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
--	int nf, pllout2;
-+	register unsigned int cfcr, plcr;
-+	unsigned int nf, pllout2;
- 
- 	cfcr =	CPM_CPCCR_CLKOEN |
--		CPM_CPCCR_PCS |
--		(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
--		(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
--		(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
--		(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
--		(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
-+		(0 << CPM_CPCCR_CDIV_BIT) |
-+		(2 << CPM_CPCCR_HDIV_BIT) |
-+		(2 << CPM_CPCCR_PDIV_BIT) |
-+		(2 << CPM_CPCCR_MDIV_BIT) |
-+		(2 << CPM_CPCCR_LDIV_BIT);
- 
- 	pllout2 = (cfcr & CPM_CPCCR_PCS) ?
- 		CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
-@@ -65,15 +53,18 @@ void pll_init(void)
- 	writel(pllout2 / 48000000 - 1, &cpm->uhccdr);
- 
- 	nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
--	plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
-+	plcr = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
- 		(0 << CPM_CPPCR_PLLN_BIT) |	/* RD=0, NR=2 */
- 		(0 << CPM_CPPCR_PLLOD_BIT) |	/* OD=0, NO=1 */
--		(0x20 << CPM_CPPCR_PLLST_BIT) |	/* PLL stable time */
-+		(0x32 << CPM_CPPCR_PLLST_BIT) |	/* PLL stable time */
- 		CPM_CPPCR_PLLEN;		/* enable PLL */
- 
- 	/* init PLL */
- 	writel(cfcr, &cpm->cpccr);
--	writel(plcr1, &cpm->cppcr);
-+	writel(plcr, &cpm->cppcr);
-+
-+	while (!(readl(&cpm->cppcr) & CPM_CPPCR_PLLS))
-+		;
- }
- 
- void sdram_init(void)
-@@ -92,26 +83,12 @@ void sdram_init(void)
- 		2 << EMC_DMCR_TCL_BIT	/* CAS latency is 3 */
- 	};
- 
--	int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
--
- 	cpu_clk = CONFIG_SYS_CPU_SPEED;
--	mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
-+	mem_clk = 84000000;
- 
- 	writel(0, &emc->bcr);	/* Disable bus release */
- 	writew(0, &emc->rtcsr);	/* Disable clock for counting */
- 
--	/* Fault DMCR value for mode register setting*/
--#define SDRAM_ROW0	11
--#define SDRAM_COL0	8
--#define SDRAM_BANK40	0
--
--	dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
--		((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
--		(SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
--		(SDRAM_BW16 << EMC_DMCR_BW_BIT) |
--		EMC_DMCR_EPIN |
--		cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
--
- 	/* Basic DMCR value */
- 	dmcr = ((SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
- 		((SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
-@@ -128,31 +105,31 @@ void sdram_init(void)
- 	if (tmp > 11)
- 		tmp = 11;
- 	dmcr |= (tmp - 4) << EMC_DMCR_TRAS_BIT;
--	tmp = SDRAM_RCD / ns;
- 
-+	tmp = SDRAM_RCD / ns;
- 	if (tmp > 3)
- 		tmp = 3;
- 	dmcr |= tmp << EMC_DMCR_RCD_BIT;
--	tmp = SDRAM_TPC / ns;
- 
-+	tmp = SDRAM_TPC / ns;
- 	if (tmp > 7)
- 		tmp = 7;
- 	dmcr |= tmp << EMC_DMCR_TPC_BIT;
--	tmp = SDRAM_TRWL / ns;
- 
-+	tmp = SDRAM_TRWL / ns;
- 	if (tmp > 3)
- 		tmp = 3;
- 	dmcr |= tmp << EMC_DMCR_TRWL_BIT;
--	tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
- 
-+	tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
- 	if (tmp > 14)
- 		tmp = 14;
- 	dmcr |= ((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT;
- 
- 	/* SDRAM mode value */
--	sdmode = EMC_SDMR_BT_SEQ |
--		 EMC_SDMR_OM_NORMAL |
--		 EMC_SDMR_BL_4 |
-+	sdmode = EMC_SDMR_BT_SEQ	|
-+		 EMC_SDMR_OM_NORMAL	|
-+		 EMC_SDMR_BL_4		|
- 		 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
- 
- 	/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
-@@ -172,8 +149,8 @@ void sdram_init(void)
- 	if (tmp > 0xff)
- 		tmp = 0xff;
- 	writew(tmp, &emc->rtcor);
-+
- 	writew(0, &emc->rtcnt);
--	/* Divisor is 64, CKO/64 */
- 	writew(EMC_RTCSR_CKS_64, &emc->rtcsr);
- 
- 	/* Wait for number of auto-refresh cycles */
-@@ -182,13 +159,17 @@ void sdram_init(void)
- 		;
- 
- 	/* Stage 3. Mode Register Set */
-+	dmcr0 = (11 << EMC_DMCR_RA_BIT)	|
-+		(8 << EMC_DMCR_CA_BIT)	|
-+		(0 << EMC_DMCR_BA_BIT)	|
-+		EMC_DMCR_EPIN		|
-+		(SDRAM_BW16 << EMC_DMCR_BW_BIT) |
-+		cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
- 	writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
- 	writeb(0, JZ4740_EMC_SDMR0 | sdmode);
- 
- 	/* Set back to basic DMCR value */
- 	writel(dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
--
--	/* everything is ok now */
- }
- 
- DECLARE_GLOBAL_DATA_PTR;
-@@ -232,9 +213,10 @@ void rtc_init(void)
- phys_size_t initdram(int board_type)
- {
- 	struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
--	u32 dmcr;
--	u32 rows, cols, dw, banks;
--	ulong size;
-+
-+	unsigned int dmcr;
-+	unsigned int rows, cols, dw, banks;
-+	unsigned long size;
- 
- 	dmcr = readl(&emc->dmcr);
- 	rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
-diff --git a/arch/mips/cpu/xburst/spl/Makefile b/arch/mips/cpu/xburst/spl/Makefile
-new file mode 100644
-index 0000000..f45e8c8
---- /dev/null
-+++ b/arch/mips/cpu/xburst/spl/Makefile
-@@ -0,0 +1,47 @@
-+#
-+# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
-+#
-+# See file CREDITS for list of people who contributed to this
-+# project.
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+
-+include $(TOPDIR)/config.mk
-+
-+LIB	= $(obj)lib$(CPU).o
-+
-+START	= start.o
-+SOBJS-y	=
-+COBJS-y	=
-+
-+SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-+START	:= $(addprefix $(obj),$(START))
-+
-+all:	$(obj).depend $(START) $(LIB)
-+
-+$(LIB):	$(OBJS)
-+	$(call cmd_link_o_target, $(OBJS))
-+
-+#########################################################################
-+
-+# defines $(obj).depend target
-+include $(SRCTREE)/rules.mk
-+
-+sinclude $(obj).depend
-+
-+#########################################################################
-diff --git a/arch/mips/cpu/xburst/spl/start.S b/arch/mips/cpu/xburst/spl/start.S
-new file mode 100644
-index 0000000..e31c4c8
---- /dev/null
-+++ b/arch/mips/cpu/xburst/spl/start.S
-@@ -0,0 +1,63 @@
-+/*
-+ * Copyright (c) 2010 Xiangfu Liu <xiangfu@openmobilefree.net>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 3 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#include <config.h>
-+#include <version.h>
-+#include <asm/regdef.h>
-+#include <asm/mipsregs.h>
-+#include <asm/addrspace.h>
-+#include <asm/cacheops.h>
-+
-+#include <asm/jz4740.h>
-+
-+	.set noreorder
-+
-+	.globl _start
-+	.text
-+_start:
-+	.word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
-+reset:
-+	/*
-+	 * STATUS register
-+	 * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
-+	 */
-+	li	t0, 0x0040FC04
-+	mtc0	t0, CP0_STATUS
-+	/*
-+	 * CAUSE register
-+	 * IV=1, use the specical interrupt vector (0x200)
-+	 */
-+	li	t1, 0x00800000
-+	mtc0	t1, CP0_CAUSE
-+
-+	bal     1f
-+	 nop
-+	.word   _GLOBAL_OFFSET_TABLE_
-+1:
-+	move    gp, ra
-+	lw      t1, 0(ra)
-+	move	gp, t1
-+
-+	la	sp, 0x80004000
-+	la	t9, nand_spl_boot
-+	j	t9
-+	nop
-diff --git a/board/qi/qi_lb60/Makefile b/board/qi/qi_lb60/Makefile
-index 5dae11b..e399246 100644
---- a/board/qi/qi_lb60/Makefile
-+++ b/board/qi/qi_lb60/Makefile
-@@ -22,7 +22,11 @@ include $(TOPDIR)/config.mk
- 
- LIB	= $(obj)lib$(BOARD).o
- 
-+ifeq ($(CONFIG_SPL_BUILD),y)
-+COBJS	:= $(BOARD)-spl.o
-+else
- COBJS	:= $(BOARD).o
-+endif
- 
- SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
- OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-diff --git a/board/qi/qi_lb60/qi_lb60-spl.c b/board/qi/qi_lb60/qi_lb60-spl.c
-new file mode 100644
-index 0000000..3fe3fa3
---- /dev/null
-+++ b/board/qi/qi_lb60/qi_lb60-spl.c
-@@ -0,0 +1,30 @@
-+/*
-+ * Authors: Xiangfu Liu <xiangfu@openmobilefree.cc>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version
-+ * 3 of the License, or (at your option) any later version.
-+ */
-+
-+#include <common.h>
-+#include <nand.h>
-+#include <asm/io.h>
-+#include <asm/jz4740.h>
-+
-+void nand_spl_boot(void)
-+{
-+	__gpio_as_sdram_16bit_4720();
-+	__gpio_as_uart0();
-+	__gpio_jtag_to_uart0();
-+
-+	serial_init();
-+
-+	pll_init();
-+	sdram_init();
-+
-+	nand_init();
-+
-+	puts("\nQi LB60 SPL: Starting U-Boot ...\n");
-+	nand_boot();
-+}
-diff --git a/board/qi/qi_lb60/qi_lb60.c b/board/qi/qi_lb60/qi_lb60.c
-index d975209..3bd4e2f 100644
---- a/board/qi/qi_lb60/qi_lb60.c
-+++ b/board/qi/qi_lb60/qi_lb60.c
-@@ -1,5 +1,5 @@
- /*
-- * Authors: Xiangfu Liu <xiangfu@sharism.cc>
-+ * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
-  *
-  * This program is free software; you can redistribute it and/or
-  * modify it under the terms of the GNU General Public License
-@@ -97,8 +97,10 @@ int board_early_init_f(void)
- /* U-Boot common routines */
- int checkboard(void)
- {
--	printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %ld MHz)\n",
--	       gd->cpu_clk / 1000000);
-+	printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC)\n");
-+	printf(" CPU: %ld\n", gd->cpu_clk);
-+	printf(" MEM: %ld\n", gd->mem_clk);
-+	printf(" DEV: %ld\n", gd->dev_clk);
- 
- 	return 0;
- }
-diff --git a/board/qi/qi_lb60/u-boot-spl.lds b/board/qi/qi_lb60/u-boot-spl.lds
-new file mode 100644
-index 0000000..930537f
---- /dev/null
-+++ b/board/qi/qi_lb60/u-boot-spl.lds
-@@ -0,0 +1,61 @@
-+/*
-+ * (C) Copyright 2012 Xiangfu Liu <xiangfu@openmobilefree.net>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
-+
-+OUTPUT_ARCH(mips)
-+ENTRY(_start)
-+SECTIONS
-+{
-+	. = 0x80000000;
-+	. = ALIGN(4);
-+	.text :
-+	{
-+	  *(.text)
-+	}
-+
-+	. = ALIGN(4);
-+	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-+
-+	. = ALIGN(4);
-+	.data  : { *(.data) }
-+
-+	. = ALIGN(4);
-+	.sdata  : { *(.sdata) }
-+
-+	_gp = ALIGN(16);
-+
-+	__got_start = .;
-+	.got  : { *(.got) }
-+	__got_end = .;
-+
-+	. = .;
-+	__u_boot_cmd_start = .;
-+	.u_boot_cmd : { *(.u_boot_cmd) }
-+	__u_boot_cmd_end = .;
-+
-+	uboot_end_data = .;
-+	num_got_entries = (__got_end - __got_start) >> 2;
-+
-+	. = ALIGN(4);
-+	.sbss  : { *(.sbss) }
-+	.bss  : { *(.bss) }
-+	uboot_end = .;
-+}
-+ASSERT(uboot_end <= 0x80002000, "NAND bootstrap too big");
-diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
-index 3ec34f3..24a4921 100644
---- a/drivers/mtd/nand/jz4740_nand.c
-+++ b/drivers/mtd/nand/jz4740_nand.c
-@@ -15,6 +15,9 @@
- #include <asm/io.h>
- #include <asm/jz4740.h>
- 
-+#ifdef CONFIG_SPL_BUILD
-+#define printf(s) puts(s)
-+#endif
- #define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
- #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
- #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
-@@ -176,7 +179,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
- 		for (k = 0; k < 9; k++)
- 			writeb(read_ecc[k], &emc->nfpar[k]);
- 	}
--	/* Set PRDY */
-+
- 	writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
- 
- 	/* Wait for completion */
-@@ -184,7 +187,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
- 		status = readl(&emc->nfints);
- 	} while (!(status & EMC_NFINTS_DECF));
- 
--	/* disable ecc */
-+	/* Disable ECC */
- 	writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
- 
- 	/* Check decoding */
-@@ -192,7 +195,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
- 		return 0;
- 
- 	if (status & EMC_NFINTS_UNCOR) {
--		printf("uncorrectable ecc\n");
-+		printf("JZ4740 uncorrectable ECC\n");
- 		return -1;
- 	}
- 
-@@ -230,6 +233,32 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
- 	return errcnt;
- }
- 
-+#ifdef CONFIG_SPL_BUILD
-+static void jz_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-+{
-+	int i;
-+	struct nand_chip *this = mtd->priv;
-+
-+#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3) || \
-+	(JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2)
-+	for (i = 0; i < len; i += 2)
-+		buf[i] = readw(this->IO_ADDR_R);
-+#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3) || \
-+	(JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2)
-+	for (i = 0; i < len; i++)
-+		buf[i] = readb(this->IO_ADDR_R);
-+#else
-+	#error JZ4740_NANDBOOT_CFG not defined or wrong
-+#endif
-+}
-+
-+static uint8_t jz_nand_read_byte(struct mtd_info *mtd)
-+{
-+	struct nand_chip *this = mtd->priv;
-+	return readb(this->IO_ADDR_R);
-+}
-+#endif
-+
- /*
-  * Main initialization routine
-  */
-@@ -254,6 +283,10 @@ int board_nand_init(struct nand_chip *nand)
- 	nand->ecc.size		= CONFIG_SYS_NAND_ECCSIZE;
- 	nand->ecc.bytes		= CONFIG_SYS_NAND_ECCBYTES;
- 	nand->ecc.layout	= &qi_lb60_ecclayout_2gb;
-+#ifdef CONFIG_SPL_BUILD
-+	nand->read_byte		= jz_nand_read_byte;
-+	nand->read_buf		= jz_nand_read_buf;
-+#endif
- 	nand->chip_delay	= 50;
- 	nand->options		= NAND_USE_FLASH_BBT;
- 
-diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
-index 4bb5bbc..7bff444 100644
---- a/include/configs/qi_lb60.h
-+++ b/include/configs/qi_lb60.h
-@@ -1,5 +1,5 @@
- /*
-- * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
-+ * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
-  *
-  * This program is free software; you can redistribute it and/or
-  * modify it under the terms of the GNU General Public License
-@@ -14,7 +14,6 @@
- #define CONFIG_SYS_LITTLE_ENDIAN
- #define CONFIG_JZSOC		/* Jz SoC */
- #define CONFIG_JZ4740		/* Jz4740 SoC */
--#define CONFIG_NAND_JZ4740
- 
- #define CONFIG_SYS_CPU_SPEED	336000000	/* CPU clock: 336 MHz */
- #define CONFIG_SYS_EXTAL	12000000	/* EXTAL freq: 12 MHz */
-@@ -24,24 +23,43 @@
- #define CONFIG_SYS_UART_BASE	JZ4740_UART0_BASE /* Base of the UART channel */
- #define CONFIG_BAUDRATE		57600
- 
-+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAUL)
-+#define CONFIG_BOOTDELAY	0
-+#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
-+#define CONFIG_BOOTCOMMAND	"nand read 0x80600000 0x400000 0x280000;bootm"
-+
-+/*
-+ * Miscellaneous configurable options
-+ */
-+#define CONFIG_SYS_SDRAM_BASE		0x80000000	/* Cached addr */
-+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
-+#define CONFIG_SYS_LOAD_ADDR		0x80600000
-+#define CONFIG_SYS_MEMTEST_START	0x80100000
-+#define CONFIG_SYS_MEMTEST_END		0x80A00000
-+#define CONFIG_SYS_TEXT_BASE		0x80100000
-+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-+
-+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
-+
-+#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
-+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-+
-+#define CONFIG_SYS_LONGHELP
-+#define CONFIG_SYS_MAXARGS	16
-+#define CONFIG_SYS_PROMPT	"NanoNote# "
-+
- #define CONFIG_SKIP_LOWLEVEL_INIT
- #define CONFIG_BOARD_EARLY_INIT_F
- #define CONFIG_SYS_NO_FLASH
- #define CONFIG_SYS_FLASH_BASE	0 /* init flash_base as 0 */
--#define CONFIG_ENV_OVERWRITE
--
--#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAUL)
--#define CONFIG_BOOTDELAY	0
--#define CONFIG_BOOTARGS		"mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
--#define CONFIG_BOOTCOMMAND	"nand read 0x80600000 0x400000 0x200000;bootm"
- 
- /*
-- * Command line configuration.
-+ * Command line configuration
-  */
- #define CONFIG_CMD_BOOTD	/* bootd			*/
- #define CONFIG_CMD_CONSOLE	/* coninfo			*/
- #define CONFIG_CMD_ECHO		/* echo arguments		*/
--
- #define CONFIG_CMD_LOADB	/* loadb			*/
- #define CONFIG_CMD_LOADS	/* loads			*/
- #define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop mtest */
-@@ -58,45 +76,16 @@
- #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
- 
- /*
-- * Miscellaneous configurable options
-- */
--#define CONFIG_SYS_MAXARGS 16
--#define CONFIG_SYS_LONGHELP
--#define CONFIG_SYS_PROMPT "NanoNote# "
--#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
--#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
--
--#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
--#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
--
--#define CONFIG_SYS_SDRAM_BASE		0x80000000	/* Cached addr */
--#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
--#define CONFIG_SYS_LOAD_ADDR		0x80600000
--#define CONFIG_SYS_MEMTEST_START	0x80100000
--#define CONFIG_SYS_MEMTEST_END		0x80800000
--
--/*
-- * Environment
-+ * NAND driver configuration
-  */
--#define CONFIG_ENV_IS_IN_NAND		/* use NAND for environment vars */
--
--#define CONFIG_SYS_NAND_5_ADDR_CYCLE
--/*
-- * if board nand flash is 1GB, set to 1
-- * if board nand flash is 2GB, set to 2
-- * for change the PAGE_SIZE and BLOCK_SIZE
-- * will delete when there is no 1GB flash
-- */
--#define NANONOTE_NAND_SIZE	2
--
--#define CONFIG_SYS_NAND_PAGE_SIZE	(2048 * NANONOTE_NAND_SIZE)
--#define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * NANONOTE_NAND_SIZE << 10)
--/* nand bad block was marked at this page in a block, start from 0 */
-+#define CONFIG_NAND_JZ4740
-+#define CONFIG_SYS_NAND_PAGE_SIZE	4096
-+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 << 10)
-+/* NAND bad block was marked at this page in a block, start from 0 */
- #define CONFIG_SYS_NAND_BADBLOCK_PAGE	127
- #define CONFIG_SYS_NAND_PAGE_COUNT	128
- #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
--/* ECC offset position in oob area, default value is 6 if it isn't defined */
--#define CONFIG_SYS_NAND_ECC_POS		(6 * NANONOTE_NAND_SIZE)
-+#define CONFIG_SYS_NAND_ECC_POS		12
- #define CONFIG_SYS_NAND_ECCSIZE		512
- #define CONFIG_SYS_NAND_ECCBYTES	9
- #define CONFIG_SYS_NAND_ECCPOS		\
-@@ -115,10 +104,9 @@
- #define CONFIG_SYS_ONENAND_BASE		CONFIG_SYS_NAND_BASE
- #define CONFIG_SYS_MAX_NAND_DEVICE	1
- #define CONFIG_SYS_NAND_SELECT_DEVICE	1 /* nand driver supports mutipl.*/
--#define CONFIG_NAND_SPL_TEXT_BASE	0x80000000
- 
- /*
-- * IPL (Initial Program Loader, integrated inside CPU)
-+ * IPL (Initial Program Loader, integrated inside Ingenic Xburst JZ4740 CPU)
-  * Will load first 8k from NAND (SPL) into cache and execute it from there.
-  *
-  * SPL (Secondary Program Loader)
-@@ -130,77 +118,88 @@
-  * NUB (NAND U-Boot)
-  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
-  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
-- *
-  */
-+
-+/*
-+ * NAND SPL configuration
-+ */
-+#define CONFIG_SPL
-+#define CONFIG_SPL_LIBGENERIC_SUPPORT
-+#define CONFIG_SPL_LIBCOMMON_SUPPORT
-+#define CONFIG_SPL_NAND_LOAD
-+#define CONFIG_SPL_NAND_SIMPLE
-+#define CONFIG_SPL_NAND_SUPPORT
-+#define CONFIG_SPL_TEXT_BASE	0x80000000
-+#define CONFIG_SPL_START_S_PATH	"arch/mips/cpu/xburst/spl"
-+
-+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
-+#define JZ4740_NANDBOOT_CFG		JZ4740_NANDBOOT_B8R3
-+
- #define CONFIG_SYS_NAND_U_BOOT_DST	0x80100000 /* Load NUB to this addr */
- #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
--/* Start NUB from this addr*/
-+					/* Start NUB from this addr */
-+#define CONFIG_SYS_NAND_U_BOOT_OFFS (32  << 10) /* Offset of NUB */
-+#define CONFIG_SYS_NAND_U_BOOT_SIZE (256 << 10) /* Size of NUB */
- 
- /*
-- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
-+ * Environment configuration
-  */
--#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
--#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
--
-+#define CONFIG_ENV_OVERWRITE
-+#define CONFIG_ENV_IS_IN_NAND
- #define CONFIG_ENV_SIZE		(4 << 10)
- #define CONFIG_ENV_OFFSET	\
- 	(CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
- #define CONFIG_ENV_OFFSET_REDUND \
- 	(CONFIG_ENV_OFFSET  + CONFIG_SYS_NAND_BLOCK_SIZE)
- 
--#define CONFIG_SYS_TEXT_BASE	0x80100000
--#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
--
- /*
-- * SDRAM Info.
-+ * CPU cache configuration
-  */
--#define CONFIG_NR_DRAM_BANKS	1
-+#define CONFIG_SYS_DCACHE_SIZE		16384
-+#define CONFIG_SYS_ICACHE_SIZE		16384
-+#define CONFIG_SYS_CACHELINE_SIZE	32
- 
- /*
-- * Cache Configuration
-+ * SDRAM configuration
-  */
--#define CONFIG_SYS_DCACHE_SIZE	16384
--#define CONFIG_SYS_ICACHE_SIZE	16384
--#define CONFIG_SYS_CACHELINE_SIZE	32
-+#define CONFIG_NR_DRAM_BANKS	1
-+
-+#define SDRAM_BW16		1	/* Data bus width: 0-32bit, 1-16bit */
-+#define SDRAM_BANK4		1	/* Banks each chip: 0-2bank, 1-4bank */
-+#define SDRAM_ROW		13	/* Row address: 11 to 13 */
-+#define SDRAM_COL		9	/* Column address: 8 to 12 */
-+#define SDRAM_CASL		2	/* CAS latency: 2 or 3 */
-+#define SDRAM_TRAS		45	/* RAS# Active Time */
-+#define SDRAM_RCD		20	/* RAS# to CAS# Delay */
-+#define SDRAM_TPC		20	/* RAS# Precharge Time */
-+#define SDRAM_TRWL		7	/* Write Latency Time */
-+#define SDRAM_TREF		15625	/* Refresh period: 8192 cycles/64ms */
- 
- /*
-- * GPIO definition
-+ * GPIO configuration
-  */
--#define GPIO_LCD_CS	(2 * 32 + 21)
--#define GPIO_AMP_EN	(3 * 32 + 4)
-+#define GPIO_LCD_CS		(2 * 32 + 21)
-+#define GPIO_AMP_EN		(3 * 32 + 4)
- 
--#define GPIO_SDPW_EN	(3 * 32 + 2)
--#define GPIO_SD_DETECT	(3 * 32 + 0)
-+#define GPIO_SDPW_EN		(3 * 32 + 2)
-+#define GPIO_SD_DETECT		(3 * 32 + 0)
- 
--#define GPIO_BUZZ_PWM	(3 * 32 + 27)
--#define GPIO_USB_DETECT	(3 * 32 + 28)
-+#define GPIO_BUZZ_PWM		(3 * 32 + 27)
-+#define GPIO_USB_DETECT		(3 * 32 + 28)
- 
--#define GPIO_AUDIO_POP	(1 * 32 + 29)
--#define GPIO_COB_TEST	(1 * 32 + 30)
-+#define GPIO_AUDIO_POP		(1 * 32 + 29)
-+#define GPIO_COB_TEST		(1 * 32 + 30)
- 
- #define GPIO_KEYOUT_BASE	(2 * 32 + 10)
--#define GPIO_KEYIN_BASE	(3 * 32 + 18)
--#define GPIO_KEYIN_8	(3 * 32 + 26)
-+#define GPIO_KEYIN_BASE		(3 * 32 + 18)
-+#define GPIO_KEYIN_8		(3 * 32 + 26)
- 
--#define GPIO_SD_CD_N	GPIO_SD_DETECT		/* SD Card insert detect */
-+#define GPIO_SD_CD_N		GPIO_SD_DETECT	/* SD Card insert detect */
- #define GPIO_SD_VCC_EN_N	GPIO_SDPW_EN	/* SD Card Power Enable */
- 
- #define SPEN	GPIO_LCD_CS	/* LCDCS :Serial command enable      */
- #define SPDA	(2 * 32 + 22)	/* LCDSCL:Serial command clock input */
- #define SPCK	(2 * 32 + 23)	/* LCDSDA:Serial command data input  */
- 
--/* SDRAM paramters */
--#define SDRAM_BW16		1	/* Data bus width: 0-32bit, 1-16bit */
--#define SDRAM_BANK4		1	/* Banks each chip: 0-2bank, 1-4bank */
--#define SDRAM_ROW		13	/* Row address: 11 to 13 */
--#define SDRAM_COL		9	/* Column address: 8 to 12 */
--#define SDRAM_CASL		2	/* CAS latency: 2 or 3 */
--
--/* SDRAM Timings, unit: ns */
--#define SDRAM_TRAS		45	/* RAS# Active Time */
--#define SDRAM_RCD		20	/* RAS# to CAS# Delay */
--#define SDRAM_TPC		20	/* RAS# Precharge Time */
--#define SDRAM_TRWL		7	/* Write Latency Time */
--#define SDRAM_TREF		15625	/* Refresh period: 8192 cycles/64ms */
--
- #endif
--- 
-1.7.9.5
-

+ 0 - 916
package/boot/uboot-xburst/patches/0002-qi_lb60-add-software-usbboot-support.patch

@@ -1,916 +0,0 @@
-From fa51192b912d296b8eec10f7d44c6c17eb1dd368 Mon Sep 17 00:00:00 2001
-From: Xiangfu <xiangfu@openmobilefree.net>
-Date: Fri, 12 Oct 2012 09:47:39 +0800
-Subject: [PATCH 2/6] qi_lb60: add software usbboot support
-
-  JZ4740 CPU have a internal ROM have such kind of code, that make
-  JZ4740 can boot from USB
-
-  usbboot.S can downloads user program from the USB port to internal
-  SRAM and branches to the internal SRAM to execute the program
-
-Signed-off-by: Xiangfu <xiangfu@openmobilefree.net>
----
- board/qi/qi_lb60/Makefile      |    1 +
- board/qi/qi_lb60/qi_lb60-spl.c |   20 +
- board/qi/qi_lb60/usbboot.S     |  838 ++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 859 insertions(+)
- create mode 100644 board/qi/qi_lb60/usbboot.S
-
-diff --git a/board/qi/qi_lb60/Makefile b/board/qi/qi_lb60/Makefile
-index e399246..6dd8c6f 100644
---- a/board/qi/qi_lb60/Makefile
-+++ b/board/qi/qi_lb60/Makefile
-@@ -23,6 +23,7 @@ include $(TOPDIR)/config.mk
- LIB	= $(obj)lib$(BOARD).o
- 
- ifeq ($(CONFIG_SPL_BUILD),y)
-+SOBJS	:= usbboot.o
- COBJS	:= $(BOARD)-spl.o
- else
- COBJS	:= $(BOARD).o
-diff --git a/board/qi/qi_lb60/qi_lb60-spl.c b/board/qi/qi_lb60/qi_lb60-spl.c
-index 3fe3fa3..aea459c 100644
---- a/board/qi/qi_lb60/qi_lb60-spl.c
-+++ b/board/qi/qi_lb60/qi_lb60-spl.c
-@@ -12,6 +12,24 @@
- #include <asm/io.h>
- #include <asm/jz4740.h>
- 
-+#define KEY_U_OUT       (32 * 2 + 16)
-+#define KEY_U_IN        (32 * 3 + 19)
-+
-+extern void usb_boot(void);
-+
-+static void check_usb_boot(void)
-+{
-+	__gpio_as_input(KEY_U_IN);
-+	__gpio_enable_pull(KEY_U_IN);
-+	__gpio_as_output(KEY_U_OUT);
-+	__gpio_clear_pin(KEY_U_OUT);
-+
-+	if (!__gpio_get_pin(KEY_U_IN)) {
-+		puts("[U] pressed, goto USBBOOT mode\n");
-+		usb_boot();
-+	}
-+}
-+
- void nand_spl_boot(void)
- {
- 	__gpio_as_sdram_16bit_4720();
-@@ -23,6 +41,8 @@ void nand_spl_boot(void)
- 	pll_init();
- 	sdram_init();
- 
-+	check_usb_boot();
-+
- 	nand_init();
- 
- 	puts("\nQi LB60 SPL: Starting U-Boot ...\n");
-diff --git a/board/qi/qi_lb60/usbboot.S b/board/qi/qi_lb60/usbboot.S
-new file mode 100644
-index 0000000..c872266
---- /dev/null
-+++ b/board/qi/qi_lb60/usbboot.S
-@@ -0,0 +1,838 @@
-+/*
-+ *  for jz4740 usb boot
-+ *
-+ *  Copyright (c) 2009 Author: <jlwei@ingenic.cn>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+    .set noreorder
-+    .globl usb_boot
-+    .text
-+
-+/*
-+ * Both NAND and USB boot load data to D-Cache first, then transfer
-+ * data from D-Cache to I-Cache, and jump to execute the code in I-Cache.
-+ * So init caches first and then dispatch to a proper boot routine.
-+ */
-+
-+.macro load_addr reg addr
-+	li \reg, 0x80000000
-+	addiu \reg, \reg, \addr
-+	la $2, usbboot_begin
-+	subu \reg, \reg, $2
-+.endm
-+
-+usb_boot:
-+	/* Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz. */
-+	la	$9, 0xB0000000		/* CPCCR: Clock Control Register */
-+	la	$8, 0x42041110		/* I:S:M:P=1:2:2:2 */
-+	sw	$8, 0($9)
-+
-+	la	$9, 0xB0000010		/* CPPCR: PLL Control Register */
-+	la	$8, 0x06000120		/* M=12 N=0 D=0 CLK=12*(M+2)/(N+2) */
-+	sw	$8, 0($9)
-+
-+	mtc0	$0, $26		/* CP0_ERRCTL, restore WST reset state */
-+	nop
-+
-+	mtc0	$0, $16			/* CP0_CONFIG */
-+	nop
-+
-+	/* Relocate code to beginning of the ram */
-+
-+	la $2, usbboot_begin
-+	la $3, usbboot_end
-+	li $4, 0x80000000
-+
-+1:
-+	lw $5, 0($2)
-+	sw $5, 0($4)
-+	addiu $2, $2, 4
-+	bne $2, $3, 1b
-+	addiu $4, $4, 4
-+
-+	li $2, 0x80000000
-+	ori $3, $2, 0
-+	addiu $3, $3, usbboot_end
-+	la $4, usbboot_begin
-+	subu $3, $3, $4
-+
-+
-+2:
-+	cache	0x0, 0($2)		/* Index_Invalidate_I */
-+	cache	0x1, 0($2)		/* Index_Writeback_Inv_D */
-+	addiu	$2, $2, 32
-+	subu $4, $3, $2
-+	bgtz	$4, 2b
-+	nop
-+
-+	load_addr $3, usb_boot_return
-+
-+	jr $3
-+
-+usbboot_begin:
-+
-+init_caches:
-+	li	$2, 3			/* cacheable for kseg0 access */
-+	mtc0	$2, $16			/* CP0_CONFIG */
-+	nop
-+
-+	li	$2, 0x20000000		/* enable idx-store-data cache insn */
-+	mtc0	$2, $26			/* CP0_ERRCTL */
-+
-+	ori	$2, $28, 0		/* start address */
-+	ori	$3, $2, 0x3fe0		/* end address, total 16KB */
-+	mtc0	$0, $28, 0		/* CP0_TAGLO */
-+	mtc0	$0, $28, 1		/* CP0_DATALO */
-+cache_clear_a_line:
-+	cache	0x8, 0($2)		/* Index_Store_Tag_I */
-+	cache	0x9, 0($2)		/* Index_Store_Tag_D */
-+	bne	$2, $3, cache_clear_a_line
-+	addiu	$2, $2, 32		/* increment CACHE_LINE_SIZE */
-+
-+	ori	$2, $28, 0		/* start address */
-+	ori	$3, $2, 0x3fe0		/* end address, total 16KB */
-+	la	$4, 0x1ffff000		/* physical address and 4KB page mask */
-+cache_alloc_a_line:
-+	and	$5, $2, $4
-+	ori	$5, $5, 1		/* V bit of the physical tag */
-+	mtc0	$5, $28, 0		/* CP0_TAGLO */
-+	cache	0x8, 0($2)		/* Index_Store_Tag_I */
-+	cache	0x9, 0($2)		/* Index_Store_Tag_D */
-+	bne	$2, $3, cache_alloc_a_line
-+	addiu	$2, $2, 32		/* increment CACHE_LINE_SIZE */
-+
-+	nop
-+	nop
-+	nop
-+	/*
-+	 * Transfer data from dcache to icache, then jump to icache.
-+	 * Input parameters:
-+	 * $19: data length in bytes
-+	 * $20: jump target address
-+	 */
-+xfer_d2i:
-+
-+	ori	$8, $20, 0
-+	addu	$9, $8, $19		/* total 16KB */
-+
-+1:
-+	cache	0x0, 0($8)		/* Index_Invalidate_I */
-+	cache	0x1, 0($8)		/* Index_Writeback_Inv_D */
-+	bne	$8, $9, 1b
-+	addiu	$8, $8, 32
-+
-+	/* flush write-buffer */
-+	sync
-+
-+	/* Invalidate BTB */
-+	mfc0	$8, $16, 7		/* CP0_CONFIG */
-+	nop
-+	ori	$8, 2
-+	mtc0	$8, $16, 7
-+	nop
-+
-+	/* Overwrite config to disable ram initalisation */
-+	li $2, 0xff
-+	sb $2, 20($20)
-+
-+	jalr	$20
-+	nop
-+
-+icache_return:
-+	/* User code can return to here after executing itself in
-+	  icache, by jumping to $31. */
-+	b	usb_boot_return
-+	nop
-+
-+
-+usb_boot_return:
-+	/* Enable the USB PHY */
-+	la	$9, 0xB0000024		/* CPM_SCR */
-+	lw	$8, 0($9)
-+	ori	$8, 0x40		/* USBPHY_ENABLE */
-+	sw	$8, 0($9)
-+
-+	/* Initialize USB registers */
-+	la	$27, 0xb3040000	/* USB registers base address */
-+
-+	sb	$0, 0x0b($27)	/* INTRUSBE: disable common USB interrupts */
-+	sh	$0, 0x06($27)	/* INTRINE: disable EPIN interrutps */
-+	sh	$0, 0x08($27)	/* INTROUTE: disable EPOUT interrutps */
-+
-+	li	$9, 0x61
-+	sb	$9, 0x01($27)	/* POWER: HSENAB | SUSPENDM | SOFTCONN */
-+
-+	/* Initialize USB states */
-+	li	$22, 0			/* set EP0 to IDLE state */
-+	li	$23, 1			/* no data stage */
-+
-+	/* Main loop of polling the usb commands */
-+usb_command_loop:
-+	lbu	$9, 0x0a($27)		/* read INTRUSB */
-+	andi	$9, 0x04		/* check USB_INTR_RESET */
-+	beqz	$9, check_intr_ep0in
-+	nop
-+
-+ 	/* 1. Handle USB reset interrupt */
-+handle_reset_intr:
-+	lbu	$9, 0x01($27)		/* read POWER */
-+	andi	$9, 0x10		/* test HS_MODE */
-+	bnez	$9, _usb_set_maxpktsize
-+	li	$9, 512			/* max packet size of HS mode */
-+	li	$9, 64			/* max packet size of FS mode */
-+
-+_usb_set_maxpktsize:
-+	li	$8, 1
-+	sb	$8, 0x0e($27)		/* set INDEX 1 */
-+
-+	sh	$9, 0x10($27)		/* INMAXP */
-+	sb	$0, 0x13($27)		/* INCSRH */
-+	sh	$9, 0x14($27)		/* OUTMAXP */
-+	sb	$0, 0x17($27)		/* OUTCSRH */
-+
-+_usb_flush_fifo:
-+	li	$8, 0x48		/* INCSR_CDT && INCSR_FF */
-+	sb	$8, 0x12($27)		/* INCSR */
-+	li	$8, 0x90		/* OUTCSR_CDT && OUTCSR_FF */
-+	sb	$8, 0x16($27)		/* OUTCSR */
-+
-+	li	$22, 0			/* set EP0 to IDLE state */
-+	li	$23, 1			/* no data stage */
-+
-+	/* 2. Check and handle EP0 interrupt */
-+check_intr_ep0in:
-+	lhu	$10, 0x02($27)		/* read INTRIN */
-+	andi	$9, $10, 0x1		/* check EP0 interrupt */
-+	beqz	$9, check_intr_ep1in
-+	nop
-+
-+handle_ep0_intr:
-+	sb	$0, 0x0e($27)		/* set INDEX 0 */
-+	lbu	$11, 0x12($27)		/* read CSR0 */
-+
-+	andi	$9, $11, 0x04		/* check SENTSTALL */
-+	beqz	$9, _ep0_setupend
-+	nop
-+
-+_ep0_sentstall:
-+	andi	$9, $11, 0xdb
-+	sb	$9, 0x12($27)		/* clear SENDSTALL and SENTSTALL */
-+	li	$22, 0			/* set EP0 to IDLE state */
-+
-+_ep0_setupend:
-+	andi	$9, $11, 0x10		/* check SETUPEND */
-+	beqz	$9, ep0_idle_state
-+	nop
-+
-+	ori	$9, $11, 0x80
-+	sb	$9, 0x12($27)		/* set SVDSETUPEND */
-+	li	$22, 0			/* set EP0 to IDLE state */
-+
-+ep0_idle_state:
-+	bnez	$22, ep0_tx_state
-+	nop
-+
-+	/* 2.1 Handle EP0 IDLE state interrupt */
-+	andi	$9, $11, 0x01		/* check OUTPKTRDY */
-+	beqz	$9, check_intr_ep1in
-+	nop
-+
-+	/* Read 8-bytes setup packet from the FIFO */
-+	lw	$25, 0x20($27)		/* first word of setup packet */
-+	lw	$26, 0x20($27)		/* second word of setup packet */
-+
-+	andi	$9, $25, 0x60		/* bRequestType & USB_TYPE_MASK */
-+	beqz	$9, _ep0_std_req
-+	nop
-+
-+	/* 2.1.1 Vendor-specific setup request */
-+_ep0_vend_req:
-+	li	$22, 0			/* set EP0 to IDLE state */
-+	li	$23, 1			/* NoData = 1 */
-+
-+	andi	$9, $25, 0xff00		/* check bRequest */
-+	srl	$9, $9, 8
-+	beqz	$9, __ep0_get_cpu_info
-+	sub	$8, $9, 0x1
-+	beqz	$8, __ep0_set_data_address
-+	sub	$8, $9, 0x2
-+	beqz	$8, __ep0_set_data_length
-+	sub	$8, $9, 0x3
-+	beqz	$8, __ep0_flush_caches
-+	sub	$8, $9, 0x4
-+	beqz	$8, __ep0_prog_start1
-+	sub	$8, $9, 0x5
-+	beqz	$8, __ep0_prog_start2
-+	nop
-+	b	_ep0_idle_state_fini	/* invalid request */
-+	nop
-+
-+__ep0_get_cpu_info:
-+	load_addr $20, cpu_info_data	/* data pointer to transfer */
-+	li	$21, 8			/* bytes left to transfer */
-+	li	$22, 1			/* set EP0 to TX state */
-+	li	$23, 0			/* NoData = 0 */
-+
-+	b	_ep0_idle_state_fini
-+	nop
-+
-+__ep0_set_data_address:
-+	li	$9, 0xffff0000
-+	and	$9, $25, $9
-+	andi	$8, $26, 0xffff
-+	or	$20, $9, $8		/* data address of next transfer */
-+
-+	b	_ep0_idle_state_fini
-+	nop
-+
-+__ep0_set_data_length:
-+	li	$9, 0xffff0000
-+	and	$9, $25, $9
-+	andi	$8, $26, 0xffff
-+	or	$21, $9, $8		/* data length of next transfer */
-+
-+	li	$9, 0x48		/* SVDOUTPKTRDY and DATAEND */
-+	sb	$9, 0x12($27)		/* CSR0 */
-+
-+	/* We must write packet to FIFO before EP1-IN interrupt here. */
-+	b	handle_epin1_intr
-+	nop
-+
-+__ep0_flush_caches:
-+	/* Flush dcache and invalidate icache. */
-+	li	$8, 0x80000000
-+	addi	$9, $8, 0x3fe0		/* total 16KB */
-+
-+1:
-+	cache	0x0, 0($8)		/* Index_Invalidate_I */
-+	cache	0x1, 0($8)		/* Index_Writeback_Inv_D */
-+	bne	$8, $9, 1b
-+	addiu	$8, $8, 32
-+
-+	/* flush write-buffer */
-+	sync
-+
-+	/* Invalidate BTB */
-+	mfc0	$8, $16, 7		/* CP0_CONFIG */
-+	nop
-+	ori	$8, 2
-+	mtc0	$8, $16, 7
-+	nop
-+
-+	b	_ep0_idle_state_fini
-+	nop
-+
-+__ep0_prog_start1:
-+	li	$9, 0x48		/* SVDOUTPKTRDY and DATAEND */
-+	sb	$9, 0x12($27)		/* CSR0 */
-+
-+	li	$9, 0xffff0000
-+	and	$9, $25, $9
-+	andi	$8, $26, 0xffff
-+	or	$20, $9, $8		/* target address */
-+
-+	b	xfer_d2i
-+	li	$19, 0x2000		/* 16KB data length */
-+
-+__ep0_prog_start2:
-+	li	$9, 0x48		/* SVDOUTPKTRDY and DATAEND */
-+	sb	$9, 0x12($27)		/* CSR0 */
-+
-+	li	$9, 0xffff0000
-+	and	$9, $25, $9
-+	andi	$8, $26, 0xffff
-+	or	$20, $9, $8		/* target address */
-+
-+	jalr	$20		/* jump, and place the return address in $31 */
-+	nop
-+
-+__ep0_prog_start2_return:
-+/* User code can return to here after executing itself, by jumping to $31 */
-+	b	usb_boot_return
-+	nop
-+
-+	/* 2.1.2 Standard setup request */
-+_ep0_std_req:
-+	andi	$12, $25, 0xff00	/* check bRequest */
-+	srl	$12, $12, 8
-+	sub	$9, $12, 0x05		/* check USB_REQ_SET_ADDRESS */
-+	bnez	$9, __ep0_req_set_config
-+	nop
-+
-+	/* Handle USB_REQ_SET_ADDRESS */
-+__ep0_req_set_addr:
-+	srl	$9, $25, 16		/* get wValue */
-+	sb	$9, 0x0($27)		/* set FADDR */
-+	li	$23, 1			/* NoData = 1 */
-+	b	_ep0_idle_state_fini
-+	nop
-+
-+__ep0_req_set_config:
-+	sub	$9, $12, 0x09		/* check USB_REQ_SET_CONFIGURATION */
-+	bnez	$9, __ep0_req_get_desc
-+	nop
-+
-+	/* Handle USB_REQ_SET_CONFIGURATION */
-+	li	$23, 1			/* NoData = 1 */
-+	b	_ep0_idle_state_fini
-+	nop
-+
-+__ep0_req_get_desc:
-+	sub	$9, $12, 0x06		/* check USB_REQ_GET_DESCRIPTOR */
-+	bnez	$9, _ep0_idle_state_fini
-+	li	$23, 1			/* NoData = 1 */
-+
-+	/* Handle USB_REQ_GET_DESCRIPTOR */
-+	li	$23, 0			/* NoData = 0 */
-+
-+	srl	$9, $25, 24		/* wValue >> 8 */
-+	sub	$8, $9, 0x01		/* check USB_DT_DEVICE */
-+	beqz	$8, ___ep0_get_dev_desc
-+	srl	$21, $26, 16		/* get wLength */
-+	sub	$8, $9, 0x02		/* check USB_DT_CONFIG */
-+	beqz	$8, ___ep0_get_conf_desc
-+	sub	$8, $9, 0x03		/* check USB_DT_STRING */
-+	beqz	$8, ___ep0_get_string_desc
-+	sub	$8, $9, 0x06		/* check USB_DT_DEVICE_QUALIFIER */
-+	beqz	$8, ___ep0_get_dev_qualifier
-+	nop
-+	b	_ep0_idle_state_fini
-+	nop
-+
-+___ep0_get_dev_desc:
-+	load_addr	$20, device_desc	/* data pointer */
-+	li	$22, 1			/* set EP0 to TX state */
-+	sub	$8, $21, 18
-+	blez	$8, _ep0_idle_state_fini /* wLength <= 18 */
-+	nop
-+	li	$21, 18			/* max length of device_desc */
-+	b	_ep0_idle_state_fini
-+	nop
-+
-+___ep0_get_dev_qualifier:
-+	load_addr	$20, dev_qualifier	/* data pointer */
-+	li	$22, 1			/* set EP0 to TX state */
-+	sub	$8, $21, 10
-+	blez	$8, _ep0_idle_state_fini /* wLength <= 10 */
-+	nop
-+	li	$21, 10			/* max length of dev_qualifier */
-+	b	_ep0_idle_state_fini
-+	nop
-+
-+___ep0_get_conf_desc:
-+	load_addr	$20, config_desc_fs	/* data pointer of FS mode */
-+	lbu	$8, 0x01($27)		/* read POWER */
-+	andi	$8, 0x10		/* test HS_MODE */
-+	beqz	$8, ___ep0_get_conf_desc2
-+	nop
-+	load_addr $20, config_desc_hs	/* data pointer of HS mode */
-+
-+___ep0_get_conf_desc2:
-+	li	$22, 1			/* set EP0 to TX state */
-+	sub	$8, $21, 32
-+	blez	$8, _ep0_idle_state_fini /* wLength <= 32 */
-+	nop
-+	li	$21, 32			/* max length of config_desc */
-+	b	_ep0_idle_state_fini
-+	nop
-+
-+___ep0_get_string_desc:
-+	li	$22, 1			/* set EP0 to TX state */
-+
-+	srl	$9, $25, 16		/* wValue & 0xff */
-+	andi	$9, 0xff
-+
-+	sub	$8, $9, 1
-+	beqz	$8, ___ep0_get_string_manufacture
-+	sub	$8, $9, 2
-+	beqz	$8, ___ep0_get_string_product
-+	nop
-+
-+___ep0_get_string_lang_ids:
-+	load_addr	$20, string_lang_ids	/* data pointer */
-+	b	_ep0_idle_state_fini
-+	li	$21, 4			/* data length */
-+
-+___ep0_get_string_manufacture:
-+	load_addr	$20, string_manufacture	/* data pointer */
-+	b	_ep0_idle_state_fini
-+	li	$21, 16			/* data length */
-+
-+___ep0_get_string_product:
-+	load_addr	$20, string_product	/* data pointer */
-+	b	_ep0_idle_state_fini
-+	li	$21, 46			/* data length */
-+
-+_ep0_idle_state_fini:
-+	li	$9, 0x40		/* SVDOUTPKTRDY */
-+	beqz	$23, _ep0_idle_state_fini2
-+	nop
-+	ori	$9, $9, 0x08		/* DATAEND */
-+_ep0_idle_state_fini2:
-+	sb	$9, 0x12($27)		/* CSR0 */
-+	beqz	$22, check_intr_ep1in
-+	nop
-+
-+	/* 2.2 Handle EP0 TX state interrupt */
-+ep0_tx_state:
-+	sub	$9, $22, 1
-+	bnez	$9, check_intr_ep1in
-+	nop
-+
-+	sub	$9, $21, 64		/* max packetsize */
-+	blez	$9, _ep0_tx_state2	/* data count <= 64 */
-+	ori	$19, $21, 0
-+	li	$19, 64
-+
-+_ep0_tx_state2:
-+	beqz	$19, _ep0_tx_state3	/* send ZLP */
-+	ori	$18, $19, 0		/* record bytes to be transferred */
-+	sub	$21, $21, $19		/* decrement data count */
-+
-+_ep0_fifo_write_loop:
-+	lbu	$9, 0($20)		/* read data */
-+	sb	$9, 0x20($27)		/* load FIFO */
-+	sub	$19, $19, 1		/* decrement counter */
-+	bnez	$19, _ep0_fifo_write_loop
-+	addi	$20, $20, 1		/* increment data pointer */
-+
-+	sub	$9, $18, 64		/* max packetsize */
-+	beqz	$9, _ep0_tx_state4
-+	nop
-+
-+_ep0_tx_state3:
-+	/* transferred bytes < max packetsize */
-+	li	$9, 0x0a		/* set INPKTRDY and DATAEND */
-+	sb	$9, 0x12($27)		/* CSR0 */
-+	li	$22, 0			/* set EP0 to IDLE state */
-+	b	check_intr_ep1in
-+	nop
-+
-+_ep0_tx_state4:
-+	/* transferred bytes == max packetsize */
-+	li	$9, 0x02		/* set INPKTRDY */
-+	sb	$9, 0x12($27)		/* CSR0 */
-+	b	check_intr_ep1in
-+	nop
-+
-+	/* 3. Check and handle EP1 BULK-IN interrupt */
-+check_intr_ep1in:
-+	andi	$9, $10, 0x2		/* check EP1 IN interrupt */
-+	beqz	$9, check_intr_ep1out
-+	nop
-+
-+handle_epin1_intr:
-+	li	$9, 1
-+	sb	$9, 0x0e($27)		/* set INDEX 1 */
-+	lbu	$9, 0x12($27)		/* read INCSR */
-+
-+	andi	$8, $9, 0x2		/* check INCSR_FFNOTEMPT */
-+	bnez	$8, _epin1_tx_state4
-+	nop
-+
-+_epin1_write_fifo:
-+	lhu	$9, 0x10($27)		/* get INMAXP */
-+	sub	$8, $21, $9
-+	blez	$8, _epin1_tx_state1	/* bytes left <= INMAXP */
-+	ori	$19, $21, 0
-+	ori	$19, $9, 0
-+
-+_epin1_tx_state1:
-+	beqz	$19, _epin1_tx_state4	/* No data */
-+	nop
-+
-+	sub	$21, $21, $19		/* decrement data count */
-+
-+	srl	$5, $19, 2		/* # of word */
-+	andi	$6, $19, 0x3		/* # of byte */
-+	beqz	$5, _epin1_tx_state2
-+	nop
-+
-+_epin1_fifo_write_word:
-+	lw	$9, 0($20)		/* read data from source address */
-+	sw	$9, 0x24($27)		/* write FIFO */
-+	sub	$5, $5, 1		/* decrement counter */
-+	bnez	$5, _epin1_fifo_write_word
-+	addiu	$20, $20, 4		/* increment dest address */
-+
-+_epin1_tx_state2:
-+	beqz	$6, _epin1_tx_state3
-+	nop
-+
-+_epin1_fifo_write_byte:
-+	lbu	$9, 0($20)		/* read data from source address */
-+	sb	$9, 0x24($27)		/* write FIFO */
-+	sub	$6, $6, 1		/* decrement counter */
-+	bnez	$6, _epin1_fifo_write_byte
-+	addiu	$20, $20, 1		/* increment dest address */
-+
-+_epin1_tx_state3:
-+	li	$9, 0x1
-+	sb	$9, 0x12($27)		/* INCSR, set INPKTRDY */
-+
-+_epin1_tx_state4:
-+	/* 4. Check and handle EP1 BULK-OUT interrupt */
-+check_intr_ep1out:
-+	lhu	$9, 0x04($27)		/* read INTROUT */
-+	andi	$9, 0x2
-+	beqz	$9, check_status_next
-+	nop
-+
-+handle_epout1_intr:
-+	li	$9, 1
-+	sb	$9, 0x0e($27)		/* set INDEX 1 */
-+
-+	lbu	$9, 0x16($27)		/* read OUTCSR */
-+	andi	$9, 0x1			/* check OUTPKTRDY */
-+	beqz	$9, check_status_next
-+	nop
-+
-+_epout1_read_fifo:
-+	lhu	$19, 0x18($27)		/* read OUTCOUNT */
-+	srl	$5, $19, 2		/* # of word */
-+	andi	$6, $19, 0x3		/* # of byte */
-+	beqz	$5, _epout1_rx_state1
-+	nop
-+
-+_epout1_fifo_read_word:
-+	lw	$9, 0x24($27)		/* read FIFO */
-+	sw	$9, 0($20)		/* store to dest address */
-+	sub	$5, $5, 1		/* decrement counter */
-+	bnez	$5, _epout1_fifo_read_word
-+	addiu	$20, $20, 4		/* increment dest address */
-+
-+_epout1_rx_state1:
-+	beqz	$6, _epout1_rx_state2
-+	nop
-+
-+_epout1_fifo_read_byte:
-+	lbu	$9, 0x24($27)		/* read FIFO */
-+	sb	$9, 0($20)		/* store to dest address */
-+	sub	$6, $6, 1		/* decrement counter */
-+	bnez	$6, _epout1_fifo_read_byte
-+	addiu	$20, $20, 1		/* increment dest address */
-+
-+_epout1_rx_state2:
-+	sb	$0, 0x16($27)		/* clear OUTPKTRDY */
-+
-+check_status_next:
-+	b	usb_command_loop
-+	nop
-+
-+/* Device/Configuration/Interface/Endpoint/String Descriptors */
-+
-+	.align	2
-+device_desc:
-+	.byte	0x12		/* bLength */
-+	.byte	0x01		/* bDescriptorType */
-+	.byte	0x00		/* bcdUSB */
-+	.byte	0x02		/* bcdUSB */
-+	.byte	0x00		/* bDeviceClass */
-+	.byte	0x00		/* bDeviceSubClass */
-+	.byte	0x00		/* bDeviceProtocol */
-+	.byte	0x40		/* bMaxPacketSize0 */
-+	.byte	0x1a		/* idVendor */
-+	.byte	0x60		/* idVendor */
-+	.byte	0x40		/* idProduct */
-+	.byte	0x47		/* idProduct */
-+	.byte	0x00		/* bcdDevice */
-+	.byte	0x01		/* bcdDevice */
-+	.byte	0x01		/* iManufacturer */
-+	.byte	0x02		/* iProduct */
-+	.byte	0x00		/* iSerialNumber */
-+	.byte	0x01		/* bNumConfigurations */
-+
-+	.align	2
-+dev_qualifier:
-+	.byte	0x0a		/* bLength */
-+	.byte	0x06		/* bDescriptorType */
-+	.byte	0x00		/* bcdUSB */
-+	.byte	0x02		/* bcdUSB */
-+	.byte	0x00		/* bDeviceClass */
-+	.byte	0x00		/* bDeviceSubClass */
-+	.byte	0x00		/* bDeviceProtocol */
-+	.byte	0x40		/* bMaxPacketSize0 */
-+	.byte	0x01		/* bNumConfigurations */
-+	.byte	0x00		/* bRESERVED */
-+
-+	.align	2
-+config_desc_hs:
-+	.byte	0x09		/* bLength */
-+	.byte	0x02		/* bDescriptorType */
-+	.byte	0x20		/* wTotalLength */
-+	.byte	0x00		/* wTotalLength */
-+	.byte	0x01		/* bNumInterfaces */
-+	.byte	0x01		/* bConfigurationValue */
-+	.byte	0x00		/* iConfiguration */
-+	.byte	0xc0		/* bmAttributes */
-+	.byte	0x01		/* MaxPower */
-+intf_desc_hs:
-+	.byte	0x09		/* bLength */
-+	.byte	0x04		/* bDescriptorType */
-+	.byte	0x00		/* bInterfaceNumber */
-+	.byte	0x00		/* bAlternateSetting */
-+	.byte	0x02		/* bNumEndpoints */
-+	.byte	0xff		/* bInterfaceClass */
-+	.byte	0x00		/* bInterfaceSubClass */
-+	.byte	0x50		/* bInterfaceProtocol */
-+	.byte	0x00		/* iInterface */
-+ep1_desc_hs:
-+	.byte	0x07		/* bLength */
-+	.byte	0x05		/* bDescriptorType */
-+	.byte	0x01		/* bEndpointAddress */
-+	.byte	0x02		/* bmAttributes */
-+	.byte	0x00		/* wMaxPacketSize */
-+	.byte	0x02		/* wMaxPacketSize */
-+	.byte	0x00		/* bInterval */
-+ep2_desc_hs:
-+	.byte	0x07		/* bLength */
-+	.byte	0x05		/* bDescriptorType */
-+	.byte	0x81		/* bEndpointAddress */
-+	.byte	0x02		/* bmAttributes */
-+	.byte	0x00		/* wMaxPacketSize */
-+	.byte	0x02		/* wMaxPacketSize */
-+	.byte	0x00		/* bInterval */
-+
-+	.align	2
-+config_desc_fs:
-+	.byte	0x09		/* bLength */
-+	.byte	0x02		/* bDescriptorType */
-+	.byte	0x20		/* wTotalLength */
-+	.byte	0x00		/* wTotalLength */
-+	.byte	0x01		/* bNumInterfaces */
-+	.byte	0x01		/* bConfigurationValue */
-+	.byte	0x00		/* iConfiguration */
-+	.byte	0xc0		/* bmAttributes */
-+	.byte	0x01		/* MaxPower */
-+intf_desc_fs:
-+	.byte	0x09		/* bLength */
-+	.byte	0x04		/* bDescriptorType */
-+	.byte	0x00		/* bInterfaceNumber */
-+	.byte	0x00		/* bAlternateSetting */
-+	.byte	0x02		/* bNumEndpoints */
-+	.byte	0xff		/* bInterfaceClass */
-+	.byte	0x00		/* bInterfaceSubClass */
-+	.byte	0x50		/* bInterfaceProtocol */
-+	.byte	0x00		/* iInterface */
-+ep1_desc_fs:
-+	.byte	0x07		/* bLength */
-+	.byte	0x05		/* bDescriptorType */
-+	.byte	0x01		/* bEndpointAddress */
-+	.byte	0x02		/* bmAttributes */
-+	.byte	0x40		/* wMaxPacketSize */
-+	.byte	0x00		/* wMaxPacketSize */
-+	.byte	0x00		/* bInterval */
-+ep2_desc_fs:
-+	.byte	0x07		/* bLength */
-+	.byte	0x05		/* bDescriptorType */
-+	.byte	0x81		/* bEndpointAddress */
-+	.byte	0x02		/* bmAttributes */
-+	.byte	0x40		/* wMaxPacketSize */
-+	.byte	0x00		/* wMaxPacketSize */
-+	.byte	0x00		/* bInterval */
-+
-+	.align	2
-+string_lang_ids:
-+	.byte	0x04
-+	.byte	0x03
-+	.byte	0x09
-+	.byte	0x04
-+
-+	.align	2
-+string_manufacture:
-+	.byte	0x10
-+	.byte	0x03
-+	.byte	0x49
-+	.byte	0x00
-+	.byte	0x6e
-+	.byte	0x00
-+	.byte	0x67
-+	.byte	0x00
-+	.byte	0x65
-+	.byte	0x00
-+	.byte	0x6e
-+	.byte	0x00
-+	.byte	0x69
-+	.byte	0x00
-+	.byte	0x63
-+	.byte	0x00
-+
-+	.align	2
-+string_product:
-+	.byte	0x2e
-+	.byte	0x03
-+	.byte	0x4a
-+	.byte	0x00
-+	.byte	0x5a
-+	.byte	0x00
-+	.byte	0x34
-+	.byte	0x00
-+	.byte	0x37
-+	.byte	0x00
-+	.byte	0x34
-+	.byte	0x00
-+	.byte	0x30
-+	.byte	0x00
-+	.byte	0x20
-+	.byte	0x00
-+	.byte	0x55
-+	.byte	0x00
-+	.byte	0x53
-+	.byte	0x00
-+	.byte	0x42
-+	.byte	0x00
-+	.byte	0x20
-+	.byte	0x00
-+	.byte	0x42
-+	.byte	0x00
-+	.byte	0x6f
-+	.byte	0x00
-+	.byte	0x6f
-+	.byte	0x00
-+	.byte	0x74
-+	.byte	0x00
-+	.byte	0x20
-+	.byte	0x00
-+	.byte	0x44
-+	.byte	0x00
-+	.byte	0x65
-+	.byte	0x00
-+	.byte	0x76
-+	.byte	0x00
-+	.byte	0x69
-+	.byte	0x00
-+	.byte	0x63
-+	.byte	0x00
-+	.byte	0x65
-+	.byte	0x00
-+
-+	.align	2
-+cpu_info_data:
-+	.byte	0x4a
-+	.byte	0x5a
-+	.byte	0x34
-+	.byte	0x37
-+	.byte	0x34
-+	.byte	0x30
-+	.byte	0x56
-+	.byte	0x31
-+usbboot_end:
-+
-+    .set reorder
--- 
-1.7.9.5
-

+ 0 - 1664
package/boot/uboot-xburst/patches/0003-add-mmc-support.patch

@@ -1,1664 +0,0 @@
-From bd36739e77669e8df45c38f6acfe2cea511534d9 Mon Sep 17 00:00:00 2001
-From: Xiangfu <xiangfu@openmobilefree.net>
-Date: Wed, 10 Oct 2012 18:19:41 +0800
-Subject: [PATCH 3/6] add mmc support
-
----
- arch/mips/include/asm/jz4740.h |  166 ++++++
- board/qi/qi_lb60/qi_lb60.c     |    9 +-
- drivers/mmc/Makefile           |    1 +
- drivers/mmc/jz_mmc.c           | 1179 ++++++++++++++++++++++++++++++++++++++++
- drivers/mmc/jz_mmc.h           |  176 ++++++
- include/configs/qi_lb60.h      |    9 +
- include/mmc.h                  |   40 ++
- 7 files changed, 1578 insertions(+), 2 deletions(-)
- create mode 100644 drivers/mmc/jz_mmc.c
- create mode 100644 drivers/mmc/jz_mmc.h
-
-diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h
-index 7a7cfff..68287fb 100644
---- a/arch/mips/include/asm/jz4740.h
-+++ b/arch/mips/include/asm/jz4740.h
-@@ -1146,5 +1146,171 @@ extern void sdram_init(void);
- extern void calc_clocks(void);
- extern void rtc_init(void);
- 
-+/*************************************************************************
-+ * MSC
-+ *************************************************************************/
-+#define REG8(addr)	*((volatile u8 *)(addr))
-+#define REG16(addr)	*((volatile u16 *)(addr))
-+#define REG32(addr)	*((volatile u32 *)(addr))
-+
-+#define	CPM_BASE	0xB0000000
-+#define CPM_CPCCR	(CPM_BASE+0x00)
-+#define CPM_MSCCDR	(CPM_BASE+0x68)
-+#define REG_CPM_MSCCDR	REG32(CPM_MSCCDR)
-+#define REG_CPM_CPCCR	REG32(CPM_CPCCR)
-+
-+#define	MSC_BASE	0xB0021000
-+
-+#define	MSC_STRPCL		(MSC_BASE + 0x000)
-+#define	MSC_STAT		(MSC_BASE + 0x004)
-+#define	MSC_CLKRT		(MSC_BASE + 0x008)
-+#define	MSC_CMDAT		(MSC_BASE + 0x00C)
-+#define	MSC_RESTO		(MSC_BASE + 0x010)
-+#define	MSC_RDTO		(MSC_BASE + 0x014)
-+#define	MSC_BLKLEN		(MSC_BASE + 0x018)
-+#define	MSC_NOB			(MSC_BASE + 0x01C)
-+#define	MSC_SNOB		(MSC_BASE + 0x020)
-+#define	MSC_IMASK		(MSC_BASE + 0x024)
-+#define	MSC_IREG		(MSC_BASE + 0x028)
-+#define	MSC_CMD			(MSC_BASE + 0x02C)
-+#define	MSC_ARG			(MSC_BASE + 0x030)
-+#define	MSC_RES			(MSC_BASE + 0x034)
-+#define	MSC_RXFIFO		(MSC_BASE + 0x038)
-+#define	MSC_TXFIFO		(MSC_BASE + 0x03C)
-+
-+#define	REG_MSC_STRPCL		REG16(MSC_STRPCL)
-+#define	REG_MSC_STAT		REG32(MSC_STAT)
-+#define	REG_MSC_CLKRT		REG16(MSC_CLKRT)
-+#define	REG_MSC_CMDAT		REG32(MSC_CMDAT)
-+#define	REG_MSC_RESTO		REG16(MSC_RESTO)
-+#define	REG_MSC_RDTO		REG16(MSC_RDTO)
-+#define	REG_MSC_BLKLEN		REG16(MSC_BLKLEN)
-+#define	REG_MSC_NOB		REG16(MSC_NOB)
-+#define	REG_MSC_SNOB		REG16(MSC_SNOB)
-+#define	REG_MSC_IMASK		REG16(MSC_IMASK)
-+#define	REG_MSC_IREG		REG16(MSC_IREG)
-+#define	REG_MSC_CMD		REG8(MSC_CMD)
-+#define	REG_MSC_ARG		REG32(MSC_ARG)
-+#define	REG_MSC_RES		REG16(MSC_RES)
-+#define	REG_MSC_RXFIFO		REG32(MSC_RXFIFO)
-+#define	REG_MSC_TXFIFO		REG32(MSC_TXFIFO)
-+
-+/* MSC Clock and Control Register (MSC_STRPCL) */
-+
-+#define MSC_STRPCL_EXIT_MULTIPLE	(1 << 7)
-+#define MSC_STRPCL_EXIT_TRANSFER	(1 << 6)
-+#define MSC_STRPCL_START_READWAIT	(1 << 5)
-+#define MSC_STRPCL_STOP_READWAIT	(1 << 4)
-+#define MSC_STRPCL_RESET		(1 << 3)
-+#define MSC_STRPCL_START_OP		(1 << 2)
-+#define MSC_STRPCL_CLOCK_CONTROL_BIT	0
-+#define MSC_STRPCL_CLOCK_CONTROL_MASK	(0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-+  #define MSC_STRPCL_CLOCK_CONTROL_STOP	  (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
-+  #define MSC_STRPCL_CLOCK_CONTROL_START  (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
-+
-+/* MSC Status Register (MSC_STAT) */
-+
-+#define MSC_STAT_IS_RESETTING		(1 << 15)
-+#define MSC_STAT_SDIO_INT_ACTIVE	(1 << 14)
-+#define MSC_STAT_PRG_DONE		(1 << 13)
-+#define MSC_STAT_DATA_TRAN_DONE		(1 << 12)
-+#define MSC_STAT_END_CMD_RES		(1 << 11)
-+#define MSC_STAT_DATA_FIFO_AFULL	(1 << 10)
-+#define MSC_STAT_IS_READWAIT		(1 << 9)
-+#define MSC_STAT_CLK_EN			(1 << 8)
-+#define MSC_STAT_DATA_FIFO_FULL		(1 << 7)
-+#define MSC_STAT_DATA_FIFO_EMPTY	(1 << 6)
-+#define MSC_STAT_CRC_RES_ERR		(1 << 5)
-+#define MSC_STAT_CRC_READ_ERROR		(1 << 4)
-+#define MSC_STAT_CRC_WRITE_ERROR_BIT	2
-+#define MSC_STAT_CRC_WRITE_ERROR_MASK	(0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-+  #define MSC_STAT_CRC_WRITE_ERROR_NO		(0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
-+  #define MSC_STAT_CRC_WRITE_ERROR		(1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
-+  #define MSC_STAT_CRC_WRITE_ERROR_NOSTS	(2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
-+#define MSC_STAT_TIME_OUT_RES		(1 << 1)
-+#define MSC_STAT_TIME_OUT_READ		(1 << 0)
-+
-+/* MSC Bus Clock Control Register (MSC_CLKRT) */
-+
-+#define	MSC_CLKRT_CLK_RATE_BIT		0
-+#define	MSC_CLKRT_CLK_RATE_MASK		(0x7 << MSC_CLKRT_CLK_RATE_BIT)
-+  #define MSC_CLKRT_CLK_RATE_DIV_1	  (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
-+  #define MSC_CLKRT_CLK_RATE_DIV_2	  (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
-+  #define MSC_CLKRT_CLK_RATE_DIV_4	  (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
-+  #define MSC_CLKRT_CLK_RATE_DIV_8	  (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
-+  #define MSC_CLKRT_CLK_RATE_DIV_16	  (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
-+  #define MSC_CLKRT_CLK_RATE_DIV_32	  (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
-+  #define MSC_CLKRT_CLK_RATE_DIV_64	  (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
-+  #define MSC_CLKRT_CLK_RATE_DIV_128	  (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
-+
-+/* MSC Command Sequence Control Register (MSC_CMDAT) */
-+
-+#define	MSC_CMDAT_IO_ABORT	(1 << 11)
-+#define	MSC_CMDAT_BUS_WIDTH_BIT	9
-+#define	MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
-+#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
-+#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
-+#define	MSC_CMDAT_DMA_EN	(1 << 8)
-+#define	MSC_CMDAT_INIT		(1 << 7)
-+#define	MSC_CMDAT_BUSY		(1 << 6)
-+#define	MSC_CMDAT_STREAM_BLOCK	(1 << 5)
-+#define	MSC_CMDAT_WRITE		(1 << 4)
-+#define	MSC_CMDAT_READ		(0 << 4)
-+#define	MSC_CMDAT_DATA_EN	(1 << 3)
-+#define	MSC_CMDAT_RESPONSE_BIT	0
-+#define	MSC_CMDAT_RESPONSE_MASK	(0x7 << MSC_CMDAT_RESPONSE_BIT)
-+#define MSC_CMDAT_RESPONSE_NONE	(0x0 << MSC_CMDAT_RESPONSE_BIT)
-+#define MSC_CMDAT_RESPONSE_R1	(0x1 << MSC_CMDAT_RESPONSE_BIT)
-+#define MSC_CMDAT_RESPONSE_R2	(0x2 << MSC_CMDAT_RESPONSE_BIT)
-+#define MSC_CMDAT_RESPONSE_R3	(0x3 << MSC_CMDAT_RESPONSE_BIT)
-+#define MSC_CMDAT_RESPONSE_R4	(0x4 << MSC_CMDAT_RESPONSE_BIT)
-+#define MSC_CMDAT_RESPONSE_R5	(0x5 << MSC_CMDAT_RESPONSE_BIT)
-+#define MSC_CMDAT_RESPONSE_R6	(0x6 << MSC_CMDAT_RESPONSE_BIT)
-+
-+/* MSC Interrupts Mask Register (MSC_IMASK) */
-+#define	MSC_IMASK_SDIO			(1 << 7)
-+#define	MSC_IMASK_TXFIFO_WR_REQ		(1 << 6)
-+#define	MSC_IMASK_RXFIFO_RD_REQ		(1 << 5)
-+#define	MSC_IMASK_END_CMD_RES		(1 << 2)
-+#define	MSC_IMASK_PRG_DONE		(1 << 1)
-+#define	MSC_IMASK_DATA_TRAN_DONE	(1 << 0)
-+
-+
-+/* MSC Interrupts Status Register (MSC_IREG) */
-+#define	MSC_IREG_SDIO			(1 << 7)
-+#define	MSC_IREG_TXFIFO_WR_REQ		(1 << 6)
-+#define	MSC_IREG_RXFIFO_RD_REQ		(1 << 5)
-+#define	MSC_IREG_END_CMD_RES		(1 << 2)
-+#define	MSC_IREG_PRG_DONE		(1 << 1)
-+#define	MSC_IREG_DATA_TRAN_DONE		(1 << 0)
-+
-+static __inline__ unsigned int __cpm_get_pllout2(void)
-+{
-+	if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
-+		return __cpm_get_pllout();
-+	else
-+		return __cpm_get_pllout()/2;
-+}
-+
-+static inline void __cpm_select_msc_clk(int sd)
-+{
-+	unsigned int pllout2 = __cpm_get_pllout2();
-+	unsigned int div = 0;
-+
-+	if (sd) {
-+		div = pllout2 / 24000000;
-+	}
-+	else {
-+		div = pllout2 / 16000000;
-+	}
-+
-+	REG_CPM_MSCCDR = div - 1;
-+}
-+#define __msc_reset() 						\
-+do { 								\
-+	REG_MSC_STRPCL = MSC_STRPCL_RESET;			\
-+ 	while (REG_MSC_STAT & MSC_STAT_IS_RESETTING);		\
-+} while (0)
-+
- #endif	/* !__ASSEMBLY__ */
- #endif	/* __JZ4740_H__ */
-diff --git a/board/qi/qi_lb60/qi_lb60.c b/board/qi/qi_lb60/qi_lb60.c
-index 3bd4e2f..a2ba648 100644
---- a/board/qi/qi_lb60/qi_lb60.c
-+++ b/board/qi/qi_lb60/qi_lb60.c
-@@ -40,8 +40,13 @@ static void gpio_init(void)
- 		__gpio_clear_pin(GPIO_KEYOUT_BASE + i);
- 	}
- 
--	__gpio_as_input(GPIO_KEYIN_8);
--	__gpio_enable_pull(GPIO_KEYIN_8);
-+	if (__gpio_get_pin(GPIO_KEYIN_BASE + 2) == 0){
-+		printf("[S] pressed, enable UART0\n");
-+		__gpio_as_uart0();
-+	} else {
-+		__gpio_as_input(GPIO_KEYIN_8);
-+		__gpio_enable_pull(GPIO_KEYIN_8);
-+	}
- 
- 	/* enable the TP4, TP5 as UART0 */
- 	__gpio_jtag_to_uart0();
-diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
-index 565ba6a..3c717b1 100644
---- a/drivers/mmc/Makefile
-+++ b/drivers/mmc/Makefile
-@@ -47,6 +47,7 @@ COBJS-$(CONFIG_SDHCI) += sdhci.o
- COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
- COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o
- COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
-+COBJS-$(CONFIG_JZ4740_MMC) += jz_mmc.o
- 
- COBJS	:= $(COBJS-y)
- SRCS	:= $(COBJS:.o=.c)
-diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c
-new file mode 100644
-index 0000000..642cecc
---- /dev/null
-+++ b/drivers/mmc/jz_mmc.c
-@@ -0,0 +1,1179 @@
-+/*
-+ * (C) Copyright 2003
-+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#include <config.h>
-+#include <common.h>
-+#include <part.h>
-+#include <mmc.h>
-+
-+#include <asm/io.h>
-+#include <asm/jz4740.h>
-+#include "jz_mmc.h"
-+
-+static int sd2_0 = 0;
-+static int mmc_ready = 0;
-+static int use_4bit;		/* Use 4-bit data bus */
-+/*
-+ *  MMC Events
-+ */
-+#define MMC_EVENT_NONE	        0x00	/* No events */
-+#define MMC_EVENT_RX_DATA_DONE	0x01	/* Rx data done */
-+#define MMC_EVENT_TX_DATA_DONE	0x02	/* Tx data done */
-+#define MMC_EVENT_PROG_DONE	0x04	/* Programming is done */
-+
-+
-+#define MMC_IRQ_MASK()				\
-+do {						\
-+      	REG_MSC_IMASK = 0xffff;			\
-+      	REG_MSC_IREG = 0xffff;			\
-+} while (0)
-+
-+/*
-+ * GPIO definition
-+ */
-+#if defined(CONFIG_SAKC)
-+
-+#define __msc_init_io()				\
-+do {						\
-+	__gpio_as_input(GPIO_SD_CD_N);		\
-+} while (0)
-+
-+#else
-+#define __msc_init_io()				\
-+do {						\
-+	__gpio_as_output(GPIO_SD_VCC_EN_N);	\
-+	__gpio_as_input(GPIO_SD_CD_N);		\
-+} while (0)
-+
-+#define __msc_enable_power()			\
-+do {						\
-+	__gpio_clear_pin(GPIO_SD_VCC_EN_N);	\
-+} while (0)
-+
-+#define __msc_disable_power()			\
-+do {						\
-+	__gpio_set_pin(GPIO_SD_VCC_EN_N);	\
-+} while (0)
-+	
-+#endif /* CONFIG_SAKE */
-+
-+#define __msc_card_detected()			\
-+({						\
-+	int detected = 1;			\
-+	__gpio_as_input(GPIO_SD_CD_N);		\
-+	__gpio_disable_pull(GPIO_SD_CD_N);	\
-+	if (!__gpio_get_pin(GPIO_SD_CD_N))	\
-+		detected = 0;			\
-+	detected;				\
-+})
-+
-+/*
-+ * Local functions
-+ */
-+
-+extern int
-+fat_register_device(block_dev_desc_t *dev_desc, int part_no);
-+
-+static block_dev_desc_t mmc_dev;
-+
-+block_dev_desc_t * mmc_get_dev(int dev)
-+{
-+	return ((block_dev_desc_t *)&mmc_dev);
-+}
-+
-+/* Stop the MMC clock and wait while it happens */
-+static inline int jz_mmc_stop_clock(void)
-+{
-+	int timeout = 1000;
-+
-+	REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP;
-+
-+	while (timeout && (REG_MSC_STAT & MSC_STAT_CLK_EN)) {
-+		timeout--;
-+		if (timeout == 0)
-+			return MMC_ERROR_TIMEOUT;
-+		udelay(1);
-+	}
-+        return MMC_NO_ERROR;
-+}
-+
-+/* Start the MMC clock and operation */
-+static inline int jz_mmc_start_clock(void)
-+{
-+	REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START | MSC_STRPCL_START_OP;
-+	return MMC_NO_ERROR;
-+}
-+
-+static inline u32 jz_mmc_calc_clkrt(int is_sd, u32 rate)
-+{
-+	u32 clkrt = 0;
-+	u32 clk_src = is_sd ? 24000000 : 16000000;
-+
-+  	while (rate < clk_src) {
-+      		clkrt ++;
-+      		clk_src >>= 1;
-+    	}
-+
-+	return clkrt;
-+}
-+
-+/* Set the MMC clock frequency */
-+void jz_mmc_set_clock(int sd, u32 rate)
-+{
-+	jz_mmc_stop_clock();
-+
-+	/* Select clock source of MSC */
-+	__cpm_select_msc_clk(sd);
-+
-+	/* Set clock dividor of MSC */
-+	REG_MSC_CLKRT = jz_mmc_calc_clkrt(sd, rate);
-+}
-+
-+static int jz_mmc_check_status(struct mmc_request *request)
-+{
-+	u32 status = REG_MSC_STAT;
-+
-+	/* Checking for response or data timeout */
-+	if (status & (MSC_STAT_TIME_OUT_RES | MSC_STAT_TIME_OUT_READ)) {
-+		printf("MMC/SD timeout, MMC_STAT 0x%x CMD %d\n", status, request->cmd);
-+		return MMC_ERROR_TIMEOUT;
-+	}
-+
-+	/* Checking for CRC error */
-+	if (status & (MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR | MSC_STAT_CRC_RES_ERR)) {
-+		printf("MMC/CD CRC error, MMC_STAT 0x%x\n", status);
-+		return MMC_ERROR_CRC;
-+	}
-+
-+	return MMC_NO_ERROR;
-+}
-+
-+/* Obtain response to the command and store it to response buffer */
-+static void jz_mmc_get_response(struct mmc_request *request)
-+{
-+	int i;
-+	u8 *buf;
-+	u32 data;
-+
-+	debug("fetch response for request %d, cmd %d\n", 
-+	      request->rtype, request->cmd);
-+
-+	buf = request->response;
-+	request->result = MMC_NO_ERROR;
-+
-+	switch (request->rtype) {
-+	case RESPONSE_R1: case RESPONSE_R1B: case RESPONSE_R6:
-+	case RESPONSE_R3: case RESPONSE_R4: case RESPONSE_R5:
-+	{
-+		data = REG_MSC_RES;
-+		buf[0] = (data >> 8) & 0xff;
-+		buf[1] = data & 0xff;
-+		data = REG_MSC_RES;
-+		buf[2] = (data >> 8) & 0xff;
-+		buf[3] = data & 0xff;
-+		data = REG_MSC_RES;
-+		buf[4] = data & 0xff;
-+
-+		debug("request %d, response [%02x %02x %02x %02x %02x]\n",
-+		      request->rtype, buf[0], buf[1], buf[2], buf[3], buf[4]);
-+		break;
-+	}
-+	case RESPONSE_R2_CID: case RESPONSE_R2_CSD:
-+	{
-+		for (i = 0; i < 16; i += 2) {
-+			data = REG_MSC_RES;
-+			buf[i] = (data >> 8) & 0xff;
-+			buf[i+1] = data & 0xff;
-+		}
-+		debug("request %d, response [", request->rtype);
-+#if CONFIG_MMC_DEBUG_VERBOSE > 2
-+		if (g_mmc_debug >= 3) {
-+			int n;
-+			for (n = 0; n < 17; n++)
-+				printk("%02x ", buf[n]);
-+			printk("]\n");
-+		}
-+#endif
-+		break;
-+	}
-+	case RESPONSE_NONE:
-+		debug("No response\n");
-+		break;
-+
-+	default:
-+		debug("unhandled response type for request %d\n", request->rtype);
-+		break;
-+	}
-+}
-+
-+static int jz_mmc_receive_data(struct mmc_request *req)
-+{
-+	u32  stat, timeout, data, cnt;
-+	u8 *buf = req->buffer;
-+	u32 wblocklen = (u32)(req->block_len + 3) >> 2; /* length in word */
-+
-+	timeout = 0x3ffffff;
-+
-+	while (timeout) {
-+		timeout--;
-+		stat = REG_MSC_STAT;
-+
-+		if (stat & MSC_STAT_TIME_OUT_READ)
-+			return MMC_ERROR_TIMEOUT;
-+		else if (stat & MSC_STAT_CRC_READ_ERROR)
-+			return MMC_ERROR_CRC;
-+		else if (!(stat & MSC_STAT_DATA_FIFO_EMPTY)
-+			 || (stat & MSC_STAT_DATA_FIFO_AFULL)) {
-+			/* Ready to read data */
-+			break;
-+		}
-+		udelay(1);
-+	}
-+	if (!timeout)
-+		return MMC_ERROR_TIMEOUT;
-+
-+	/* Read data from RXFIFO. It could be FULL or PARTIAL FULL */
-+	cnt = wblocklen;
-+	while (cnt) {
-+		data = REG_MSC_RXFIFO;
-+		{
-+			*buf++ = (u8)(data >> 0);
-+			*buf++ = (u8)(data >> 8);
-+			*buf++ = (u8)(data >> 16);
-+			*buf++ = (u8)(data >> 24);
-+		}
-+		cnt --;
-+		while (cnt && (REG_MSC_STAT & MSC_STAT_DATA_FIFO_EMPTY))
-+			;
-+	}
-+	return MMC_NO_ERROR;
-+}
-+
-+static int jz_mmc_transmit_data(struct mmc_request *req)
-+{
-+#if 0
-+	u32 nob = req->nob;
-+	u32 wblocklen = (u32)(req->block_len + 3) >> 2; /* length in word */
-+	u8 *buf = req->buffer;
-+	u32 *wbuf = (u32 *)buf;
-+	u32 waligned = (((u32)buf & 0x3) == 0); /* word aligned ? */
-+	u32 stat, timeout, data, cnt;
-+
-+	for (nob; nob >= 1; nob--) {
-+		timeout = 0x3FFFFFF;
-+
-+		while (timeout) {
-+			timeout--;
-+			stat = REG_MSC_STAT;
-+
-+			if (stat & (MSC_STAT_CRC_WRITE_ERROR | MSC_STAT_CRC_WRITE_ERROR_NOSTS))
-+				return MMC_ERROR_CRC;
-+			else if (!(stat & MSC_STAT_DATA_FIFO_FULL)) {
-+				/* Ready to write data */
-+				break;
-+			}
-+
-+			udelay(1);
-+		}
-+
-+		if (!timeout)
-+			return MMC_ERROR_TIMEOUT;
-+
-+		/* Write data to TXFIFO */
-+		cnt = wblocklen;
-+		while (cnt) {
-+			while (REG_MSC_STAT & MSC_STAT_DATA_FIFO_FULL)
-+				;
-+
-+			if (waligned) {
-+				REG_MSC_TXFIFO = *wbuf++;
-+			}
-+			else {
-+				data = *buf++ | (*buf++ << 8) | (*buf++ << 16) | (*buf++ << 24);
-+				REG_MSC_TXFIFO = data;
-+			}
-+
-+			cnt--;
-+		}
-+	}
-+#endif
-+	return MMC_NO_ERROR;
-+}
-+
-+
-+/*
-+ * Name:	  int jz_mmc_exec_cmd()
-+ * Function:      send command to the card, and get a response
-+ * Input:	  struct mmc_request *req	: MMC/SD request
-+ * Output:	  0:  right		>0:  error code
-+ */
-+int jz_mmc_exec_cmd(struct mmc_request *request)
-+{
-+	u32 cmdat = 0, events = 0;
-+	int retval, timeout = 0x3fffff;
-+
-+	/* Indicate we have no result yet */
-+	request->result = MMC_NO_RESPONSE;
-+	if (request->cmd == MMC_CIM_RESET) {
-+		/* On reset, 1-bit bus width */
-+		use_4bit = 0;
-+
-+		/* Reset MMC/SD controller */
-+		__msc_reset();
-+
-+		/* On reset, drop MMC clock down */
-+		jz_mmc_set_clock(0, MMC_CLOCK_SLOW);
-+
-+		/* On reset, stop MMC clock */
-+		jz_mmc_stop_clock();
-+	}
-+	if (request->cmd == MMC_CMD_SEND_OP_COND) {
-+		debug("Have an MMC card\n");
-+		/* always use 1bit for MMC */
-+		use_4bit = 0;
-+	}
-+	if (request->cmd == SET_BUS_WIDTH) {
-+		if (request->arg == 0x2) {
-+			printf("Use 4-bit bus width\n");
-+			use_4bit = 1;
-+		} else {
-+			printf("Use 1-bit bus width\n");
-+			use_4bit = 0;
-+		}
-+	}
-+
-+	/* stop clock */
-+	jz_mmc_stop_clock();
-+
-+	/* mask all interrupts */
-+	REG_MSC_IMASK = 0xffff;
-+
-+	/* clear status */
-+	REG_MSC_IREG = 0xffff;
-+
-+	/* use 4-bit bus width when possible */
-+	if (use_4bit)
-+		cmdat |= MSC_CMDAT_BUS_WIDTH_4BIT;
-+
-+        /* Set command type and events */
-+	switch (request->cmd) {
-+	/* MMC core extra command */
-+	case MMC_CIM_RESET:
-+		cmdat |= MSC_CMDAT_INIT; /* Initialization sequence sent prior to command */
-+		break;
-+
-+	/* bc - broadcast - no response */
-+	case MMC_CMD_GO_IDLE_STATE:
-+	case MMC_CMD_SET_DSR:
-+		break;
-+
-+	/* bcr - broadcast with response */
-+	case MMC_CMD_SEND_OP_COND:
-+	case MMC_CMD_ALL_SEND_CID:
-+	case MMC_GO_IRQ_STATE:
-+		break;
-+
-+	/* adtc - addressed with data transfer */
-+	case MMC_READ_DAT_UNTIL_STOP:
-+	case MMC_CMD_READ_SINGLE_BLOCK:
-+	case MMC_CMD_READ_MULTIPLE_BLOCK:
-+	case SD_CMD_APP_SEND_SCR:
-+		cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ;
-+		events = MMC_EVENT_RX_DATA_DONE;
-+		break;
-+
-+	case MMC_WRITE_DAT_UNTIL_STOP:
-+	case MMC_CMD_WRITE_SINGLE_BLOCK:
-+	case MMC_CMD_WRITE_MULTIPLE_BLOCK:
-+	case MMC_PROGRAM_CID:
-+	case MMC_PROGRAM_CSD:
-+	case MMC_SEND_WRITE_PROT:
-+	case MMC_GEN_CMD:
-+	case MMC_LOCK_UNLOCK:
-+		cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE;
-+		events = MMC_EVENT_TX_DATA_DONE | MMC_EVENT_PROG_DONE;
-+
-+		break;
-+
-+	case MMC_CMD_STOP_TRANSMISSION:
-+		events = MMC_EVENT_PROG_DONE;
-+		break;
-+
-+	/* ac - no data transfer */
-+	default:
-+		break;
-+	}
-+
-+	/* Set response type */
-+	switch (request->rtype) {
-+	case RESPONSE_NONE:
-+		break;
-+
-+	case RESPONSE_R1B:
-+		cmdat |= MSC_CMDAT_BUSY;
-+		/*FALLTHRU*/
-+	case RESPONSE_R1:
-+		cmdat |= MSC_CMDAT_RESPONSE_R1;
-+		break;
-+	case RESPONSE_R2_CID:
-+	case RESPONSE_R2_CSD:
-+		cmdat |= MSC_CMDAT_RESPONSE_R2;
-+		break;
-+	case RESPONSE_R3:
-+		cmdat |= MSC_CMDAT_RESPONSE_R3;
-+		break;
-+	case RESPONSE_R4:
-+		cmdat |= MSC_CMDAT_RESPONSE_R4;
-+		break;
-+	case RESPONSE_R5:
-+		cmdat |= MSC_CMDAT_RESPONSE_R5;
-+		break;
-+	case RESPONSE_R6:
-+		cmdat |= MSC_CMDAT_RESPONSE_R6;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	/* Set command index */
-+	if (request->cmd == MMC_CIM_RESET) {
-+		REG_MSC_CMD = MMC_CMD_GO_IDLE_STATE;
-+	} else {
-+		REG_MSC_CMD = request->cmd;