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080-arm64-allwinner-a64-add-SPI-nodes.patch

080-arm64-allwinner-a64-add-SPI-nodes.patch 2.2 KB
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  1. From b518bb159032aac33503fd4cf98706dc84cc1266 Mon Sep 17 00:00:00 2001
    2. 

  2. From: =?UTF-8?q?Stefan=20Br=C3=BCns?= <stefan.bruens@rwth-aachen.de>
    3. 

  3. Date: Thu, 31 Aug 2017 01:06:37 +0200
    4. 

  4. Subject: [PATCH] arm64: allwinner: a64: add SPI nodes
    5. 

  5. MIME-Version: 1.0
    6. 

  6. Content-Type: text/plain; charset=UTF-8
    7. 

  7. Content-Transfer-Encoding: 8bit
    8. 

  8. 

  9. The A64 SPI controllers are register compatible to the h3/h5 SPI
    10. 

  10. controllers.
    11. 

  11. 

  12. The A64 has two SPI controllers, each with a single chip select.
    13. 

  13. The handles for the DMA channels (23/24 for SPI0/SPI1) are omitted,
    14. 

  14. as the A64 DMA support is currently missing.
    15. 

  15. 

  16. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
    17. 

  17. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
    18. 

  18. ---
    19. 

  19.  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 41 +++++++++++++++++++
    20. 

  20.  1 file changed, 41 insertions(+)
    21. 

  21. 

  22. --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
    23. 

  23. +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
    24. 

  24. @@ -326,6 +326,16 @@
    25. 

  25.  				drive-strength = <40>;
    26. 

  26.  			};
    27. 

  27.  
    28. 

  28. +			spi0_pins: spi0 {
    29. 

  29. +				pins = "PC0", "PC1", "PC2", "PC3";
    30. 

  30. +				function = "spi0";
    31. 

  31. +			};
    32. 

  32. +
    33. 

  33. +			spi1_pins: spi1 {
    34. 

  34. +				pins = "PD0", "PD1", "PD2", "PD3";
    35. 

  35. +				function = "spi1";
    36. 

  36. +			};
    37. 

  37. +
    38. 

  38.  			uart0_pins_a: uart0@0 {
    39. 

  39.  				pins = "PB8", "PB9";
    40. 

  40.  				function = "uart0";
    41. 

  41. @@ -471,6 +481,37 @@
    42. 

  42.  			};
    43. 

  43.  		};
    44. 

  44.  
    45. 

  45. +
    46. 

  46. +		spi0: spi@01c68000 {
    47. 

  47. +			compatible = "allwinner,sun8i-h3-spi";
    48. 

  48. +			reg = <0x01c68000 0x1000>;
    49. 

  49. +			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
    50. 

  50. +			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
    51. 

  51. +			clock-names = "ahb", "mod";
    52. 

  52. +			pinctrl-names = "default";
    53. 

  53. +			pinctrl-0 = <&spi0_pins>;
    54. 

  54. +			resets = <&ccu RST_BUS_SPI0>;
    55. 

  55. +			status = "disabled";
    56. 

  56. +			num-cs = <1>;
    57. 

  57. +			#address-cells = <1>;
    58. 

  58. +			#size-cells = <0>;
    59. 

  59. +		};
    60. 

  60. +
    61. 

  61. +		spi1: spi@01c69000 {
    62. 

  62. +			compatible = "allwinner,sun8i-h3-spi";
    63. 

  63. +			reg = <0x01c69000 0x1000>;
    64. 

  64. +			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
    65. 

  65. +			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
    66. 

  66. +			clock-names = "ahb", "mod";
    67. 

  67. +			pinctrl-names = "default";
    68. 

  68. +			pinctrl-0 = <&spi1_pins>;
    69. 

  69. +			resets = <&ccu RST_BUS_SPI1>;
    70. 

  70. +			status = "disabled";
    71. 

  71. +			num-cs = <1>;
    72. 

  72. +			#address-cells = <1>;
    73. 

  73. +			#size-cells = <0>;
    74. 

  74. +		};
    75. 

  75. +
    76. 

  76.  		gic: interrupt-controller@1c81000 {
    77. 

  77.  			compatible = "arm,gic-400";
    78. 

  78.  			reg = <0x01c81000 0x1000>,
    79.