071-v4.8-0004-net-ethernet-bgmac-convert-to-feature-flags.patch 13 KB

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  1. From db791eb2970bad193b1dc95a4461b222dd22cb64 Mon Sep 17 00:00:00 2001
  2. From: Jon Mason <jon.mason@broadcom.com>
  3. Date: Thu, 7 Jul 2016 19:08:56 -0400
  4. Subject: [PATCH 4/5] net: ethernet: bgmac: convert to feature flags
  5. The bgmac driver is using the bcma provides device ID and revision, as
  6. well as the SoC ID and package, to determine which features are
  7. necessary to enable, reset, etc in the driver. In anticipation of
  8. removing the bcma requirement for this driver, these must be changed to
  9. not reference that struct. In place of that, each "feature" has been
  10. given a flag, and the flags are enabled for their respective device and
  11. SoC.
  12. Signed-off-by: Jon Mason <jon.mason@broadcom.com>
  13. Acked-by: Arnd Bergmann <arnd@arndb.de>
  14. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
  15. Tested-by: Florian Fainelli <f.fainelli@gmail.com>
  16. Signed-off-by: David S. Miller <davem@davemloft.net>
  17. ---
  18. drivers/net/ethernet/broadcom/bgmac.c | 167 ++++++++++++++++++++++++----------
  19. drivers/net/ethernet/broadcom/bgmac.h | 21 ++++-
  20. 2 files changed, 140 insertions(+), 48 deletions(-)
  21. --- a/drivers/net/ethernet/broadcom/bgmac.c
  22. +++ b/drivers/net/ethernet/broadcom/bgmac.c
  23. @@ -109,7 +109,7 @@ static void bgmac_dma_tx_enable(struct b
  24. u32 ctl;
  25. ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
  26. - if (bgmac->core->id.rev >= 4) {
  27. + if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) {
  28. ctl &= ~BGMAC_DMA_TX_BL_MASK;
  29. ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
  30. @@ -335,7 +335,7 @@ static void bgmac_dma_rx_enable(struct b
  31. /* preserve ONLY bits 16-17 from current hardware value */
  32. ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
  33. - if (bgmac->core->id.rev >= 4) {
  34. + if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) {
  35. ctl &= ~BGMAC_DMA_RX_BL_MASK;
  36. ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
  37. @@ -772,14 +772,20 @@ static void bgmac_cmdcfg_maskset(struct
  38. {
  39. u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
  40. u32 new_val = (cmdcfg & mask) | set;
  41. + u32 cmdcfg_sr;
  42. - bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
  43. + if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
  44. + cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
  45. + else
  46. + cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
  47. +
  48. + bgmac_set(bgmac, BGMAC_CMDCFG, cmdcfg_sr);
  49. udelay(2);
  50. if (new_val != cmdcfg || force)
  51. bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
  52. - bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
  53. + bgmac_mask(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr);
  54. udelay(2);
  55. }
  56. @@ -808,7 +814,7 @@ static void bgmac_chip_stats_update(stru
  57. {
  58. int i;
  59. - if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
  60. + if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) {
  61. for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
  62. bgmac->mib_tx_regs[i] =
  63. bgmac_read(bgmac,
  64. @@ -827,7 +833,7 @@ static void bgmac_clear_mib(struct bgmac
  65. {
  66. int i;
  67. - if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
  68. + if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)
  69. return;
  70. bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
  71. @@ -870,9 +876,8 @@ static void bgmac_mac_speed(struct bgmac
  72. static void bgmac_miiconfig(struct bgmac *bgmac)
  73. {
  74. struct bcma_device *core = bgmac->core;
  75. - u8 imode;
  76. - if (bgmac_is_bcm4707_family(bgmac)) {
  77. + if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) {
  78. bcma_awrite32(core, BCMA_IOCTL,
  79. bcma_aread32(core, BCMA_IOCTL) | 0x40 |
  80. BGMAC_BCMA_IOCTL_SW_CLKEN);
  81. @@ -880,6 +885,8 @@ static void bgmac_miiconfig(struct bgmac
  82. bgmac->mac_duplex = DUPLEX_FULL;
  83. bgmac_mac_speed(bgmac);
  84. } else {
  85. + u8 imode;
  86. +
  87. imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
  88. BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
  89. if (imode == 0 || imode == 1) {
  90. @@ -894,9 +901,7 @@ static void bgmac_miiconfig(struct bgmac
  91. static void bgmac_chip_reset(struct bgmac *bgmac)
  92. {
  93. struct bcma_device *core = bgmac->core;
  94. - struct bcma_bus *bus = core->bus;
  95. - struct bcma_chipinfo *ci = &bus->chipinfo;
  96. - u32 flags;
  97. + u32 cmdcfg_sr;
  98. u32 iost;
  99. int i;
  100. @@ -919,15 +924,12 @@ static void bgmac_chip_reset(struct bgma
  101. }
  102. iost = bcma_aread32(core, BCMA_IOST);
  103. - if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
  104. - (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
  105. - (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
  106. + if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED)
  107. iost &= ~BGMAC_BCMA_IOST_ATTACHED;
  108. /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */
  109. - if (ci->id != BCMA_CHIP_ID_BCM4707 &&
  110. - ci->id != BCMA_CHIP_ID_BCM47094) {
  111. - flags = 0;
  112. + if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) {
  113. + u32 flags = 0;
  114. if (iost & BGMAC_BCMA_IOST_ATTACHED) {
  115. flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
  116. if (!bgmac->has_robosw)
  117. @@ -937,7 +939,7 @@ static void bgmac_chip_reset(struct bgma
  118. }
  119. /* Request Misc PLL for corerev > 2 */
  120. - if (core->id.rev > 2 && !bgmac_is_bcm4707_family(bgmac)) {
  121. + if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) {
  122. bgmac_set(bgmac, BCMA_CLKCTLST,
  123. BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
  124. bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
  125. @@ -946,9 +948,7 @@ static void bgmac_chip_reset(struct bgma
  126. 1000);
  127. }
  128. - if (ci->id == BCMA_CHIP_ID_BCM5357 ||
  129. - ci->id == BCMA_CHIP_ID_BCM4749 ||
  130. - ci->id == BCMA_CHIP_ID_BCM53572) {
  131. + if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) {
  132. struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
  133. u8 et_swtype = 0;
  134. u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
  135. @@ -962,11 +962,9 @@ static void bgmac_chip_reset(struct bgma
  136. et_swtype &= 0x0f;
  137. et_swtype <<= 4;
  138. sw_type = et_swtype;
  139. - } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) {
  140. + } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) {
  141. sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
  142. - } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
  143. - (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
  144. - (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) {
  145. + } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) {
  146. sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
  147. BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
  148. }
  149. @@ -986,6 +984,11 @@ static void bgmac_chip_reset(struct bgma
  150. * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
  151. * be keps until taking MAC out of the reset.
  152. */
  153. + if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
  154. + cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
  155. + else
  156. + cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
  157. +
  158. bgmac_cmdcfg_maskset(bgmac,
  159. ~(BGMAC_CMDCFG_TE |
  160. BGMAC_CMDCFG_RE |
  161. @@ -1003,13 +1006,13 @@ static void bgmac_chip_reset(struct bgma
  162. BGMAC_CMDCFG_PROM |
  163. BGMAC_CMDCFG_NLC |
  164. BGMAC_CMDCFG_CFE |
  165. - BGMAC_CMDCFG_SR(core->id.rev),
  166. + cmdcfg_sr,
  167. false);
  168. bgmac->mac_speed = SPEED_UNKNOWN;
  169. bgmac->mac_duplex = DUPLEX_UNKNOWN;
  170. bgmac_clear_mib(bgmac);
  171. - if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
  172. + if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL)
  173. bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
  174. BCMA_GMAC_CMN_PC_MTE);
  175. else
  176. @@ -1035,46 +1038,48 @@ static void bgmac_chip_intrs_off(struct
  177. /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
  178. static void bgmac_enable(struct bgmac *bgmac)
  179. {
  180. - struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
  181. + u32 cmdcfg_sr;
  182. u32 cmdcfg;
  183. u32 mode;
  184. - u32 rxq_ctl;
  185. - u32 fl_ctl;
  186. - u16 bp_clk;
  187. - u8 mdp;
  188. +
  189. + if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
  190. + cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
  191. + else
  192. + cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
  193. cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
  194. bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
  195. - BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
  196. + cmdcfg_sr, true);
  197. udelay(2);
  198. cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
  199. bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
  200. mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
  201. BGMAC_DS_MM_SHIFT;
  202. - if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
  203. + if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0)
  204. bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
  205. - if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
  206. + if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST && mode == 2)
  207. bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
  208. BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
  209. - switch (ci->id) {
  210. - case BCMA_CHIP_ID_BCM5357:
  211. - case BCMA_CHIP_ID_BCM4749:
  212. - case BCMA_CHIP_ID_BCM53572:
  213. - case BCMA_CHIP_ID_BCM4716:
  214. - case BCMA_CHIP_ID_BCM47162:
  215. - fl_ctl = 0x03cb04cb;
  216. - if (ci->id == BCMA_CHIP_ID_BCM5357 ||
  217. - ci->id == BCMA_CHIP_ID_BCM4749 ||
  218. - ci->id == BCMA_CHIP_ID_BCM53572)
  219. + if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 |
  220. + BGMAC_FEAT_FLW_CTRL2)) {
  221. + u32 fl_ctl;
  222. +
  223. + if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1)
  224. fl_ctl = 0x2300e1;
  225. + else
  226. + fl_ctl = 0x03cb04cb;
  227. +
  228. bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
  229. bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
  230. - break;
  231. }
  232. - if (!bgmac_is_bcm4707_family(bgmac)) {
  233. + if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) {
  234. + u32 rxq_ctl;
  235. + u16 bp_clk;
  236. + u8 mdp;
  237. +
  238. rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
  239. rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
  240. bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
  241. @@ -1606,6 +1611,74 @@ static int bgmac_probe(struct bcma_devic
  242. if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
  243. dev_warn(bgmac->dev, "Support for ADMtek ethernet switch not implemented\n");
  244. + /* Feature Flags */
  245. + switch (core->bus->chipinfo.id) {
  246. + case BCMA_CHIP_ID_BCM5357:
  247. + bgmac->feature_flags |= BGMAC_FEAT_SET_RXQ_CLK;
  248. + bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
  249. + bgmac->feature_flags |= BGMAC_FEAT_FLW_CTRL1;
  250. + bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_PHY;
  251. + if (core->bus->chipinfo.pkg == BCMA_PKG_ID_BCM47186) {
  252. + bgmac->feature_flags |= BGMAC_FEAT_IOST_ATTACHED;
  253. + bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_RGMII;
  254. + }
  255. + if (core->bus->chipinfo.pkg == BCMA_PKG_ID_BCM5358)
  256. + bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_EPHYRMII;
  257. + break;
  258. + case BCMA_CHIP_ID_BCM53572:
  259. + bgmac->feature_flags |= BGMAC_FEAT_SET_RXQ_CLK;
  260. + bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
  261. + bgmac->feature_flags |= BGMAC_FEAT_FLW_CTRL1;
  262. + bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_PHY;
  263. + if (core->bus->chipinfo.pkg == BCMA_PKG_ID_BCM47188) {
  264. + bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_RGMII;
  265. + bgmac->feature_flags |= BGMAC_FEAT_IOST_ATTACHED;
  266. + }
  267. + break;
  268. + case BCMA_CHIP_ID_BCM4749:
  269. + bgmac->feature_flags |= BGMAC_FEAT_SET_RXQ_CLK;
  270. + bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
  271. + bgmac->feature_flags |= BGMAC_FEAT_FLW_CTRL1;
  272. + bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_PHY;
  273. + if (core->bus->chipinfo.pkg == 10) {
  274. + bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_RGMII;
  275. + bgmac->feature_flags |= BGMAC_FEAT_IOST_ATTACHED;
  276. + }
  277. + break;
  278. + case BCMA_CHIP_ID_BCM4716:
  279. + bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
  280. + /* fallthrough */
  281. + case BCMA_CHIP_ID_BCM47162:
  282. + bgmac->feature_flags |= BGMAC_FEAT_FLW_CTRL2;
  283. + bgmac->feature_flags |= BGMAC_FEAT_SET_RXQ_CLK;
  284. + break;
  285. + /* bcm4707_family */
  286. + case BCMA_CHIP_ID_BCM4707:
  287. + case BCMA_CHIP_ID_BCM47094:
  288. + case BCMA_CHIP_ID_BCM53018:
  289. + bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
  290. + bgmac->feature_flags |= BGMAC_FEAT_NO_RESET;
  291. + bgmac->feature_flags |= BGMAC_FEAT_FORCE_SPEED_2500;
  292. + break;
  293. + default:
  294. + bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
  295. + bgmac->feature_flags |= BGMAC_FEAT_SET_RXQ_CLK;
  296. + }
  297. +
  298. + if (!bgmac_is_bcm4707_family(bgmac) && core->id.rev > 2)
  299. + bgmac->feature_flags |= BGMAC_FEAT_MISC_PLL_REQ;
  300. +
  301. + if (core->id.id == BCMA_CORE_4706_MAC_GBIT) {
  302. + bgmac->feature_flags |= BGMAC_FEAT_CMN_PHY_CTL;
  303. + bgmac->feature_flags |= BGMAC_FEAT_NO_CLR_MIB;
  304. + }
  305. +
  306. + if (core->id.rev >= 4) {
  307. + bgmac->feature_flags |= BGMAC_FEAT_CMDCFG_SR_REV4;
  308. + bgmac->feature_flags |= BGMAC_FEAT_TX_MASK_SETUP;
  309. + bgmac->feature_flags |= BGMAC_FEAT_RX_MASK_SETUP;
  310. + }
  311. +
  312. netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
  313. if (!bgmac_is_bcm4707_family(bgmac)) {
  314. --- a/drivers/net/ethernet/broadcom/bgmac.h
  315. +++ b/drivers/net/ethernet/broadcom/bgmac.h
  316. @@ -190,7 +190,6 @@
  317. #define BGMAC_CMDCFG_HD_SHIFT 10
  318. #define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for core rev 0-3 */
  319. #define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, for core rev >= 4 */
  320. -#define BGMAC_CMDCFG_SR(rev) ((rev >= 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0)
  321. #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
  322. #define BGMAC_CMDCFG_AE 0x00400000
  323. #define BGMAC_CMDCFG_CFE 0x00800000
  324. @@ -376,6 +375,24 @@
  325. #define ETHER_MAX_LEN 1518
  326. +/* Feature Flags */
  327. +#define BGMAC_FEAT_TX_MASK_SETUP BIT(0)
  328. +#define BGMAC_FEAT_RX_MASK_SETUP BIT(1)
  329. +#define BGMAC_FEAT_IOST_ATTACHED BIT(2)
  330. +#define BGMAC_FEAT_NO_RESET BIT(3)
  331. +#define BGMAC_FEAT_MISC_PLL_REQ BIT(4)
  332. +#define BGMAC_FEAT_SW_TYPE_PHY BIT(5)
  333. +#define BGMAC_FEAT_SW_TYPE_EPHYRMII BIT(6)
  334. +#define BGMAC_FEAT_SW_TYPE_RGMII BIT(7)
  335. +#define BGMAC_FEAT_CMN_PHY_CTL BIT(8)
  336. +#define BGMAC_FEAT_FLW_CTRL1 BIT(9)
  337. +#define BGMAC_FEAT_FLW_CTRL2 BIT(10)
  338. +#define BGMAC_FEAT_SET_RXQ_CLK BIT(11)
  339. +#define BGMAC_FEAT_CLKCTLST BIT(12)
  340. +#define BGMAC_FEAT_NO_CLR_MIB BIT(13)
  341. +#define BGMAC_FEAT_FORCE_SPEED_2500 BIT(14)
  342. +#define BGMAC_FEAT_CMDCFG_SR_REV4 BIT(15)
  343. +
  344. struct bgmac_slot_info {
  345. union {
  346. struct sk_buff *skb;
  347. @@ -430,6 +447,8 @@ struct bgmac {
  348. struct device *dev;
  349. struct device *dma_dev;
  350. + u32 feature_flags;
  351. +
  352. struct net_device *net_dev;
  353. struct napi_struct napi;
  354. struct mii_bus *mii_bus;