544-ath9k-ar933x-usb-hang-workaround.patch 2.1 KB

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  1. --- a/drivers/net/wireless/ath/ath9k/hw.c
  2. +++ b/drivers/net/wireless/ath/ath9k/hw.c
  3. @@ -246,6 +246,19 @@ void ath9k_hw_get_channel_centers(struct
  4. centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
  5. }
  6. +static inline void ath9k_hw_disable_pll_lock_detect(struct ath_hw *ah)
  7. +{
  8. + /* On AR9330 and AR9340 devices, some PHY registers must be
  9. + * tuned to gain better stability/performance. These registers
  10. + * might be changed while doing wlan reset so the registers must
  11. + * be reprogrammed after each reset.
  12. + */
  13. + REG_CLR_BIT(ah, AR_PHY_USB_CTRL1, BIT(20));
  14. + REG_RMW(ah, AR_PHY_USB_CTRL2,
  15. + (1 << 21) | (0xf << 22),
  16. + (1 << 21) | (0x3 << 22));
  17. +}
  18. +
  19. /******************/
  20. /* Chip Revisions */
  21. /******************/
  22. @@ -1386,6 +1399,9 @@ static bool ath9k_hw_set_reset(struct at
  23. if (AR_SREV_9100(ah))
  24. udelay(50);
  25. + if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
  26. + ath9k_hw_disable_pll_lock_detect(ah);
  27. +
  28. return true;
  29. }
  30. @@ -1485,6 +1501,9 @@ static bool ath9k_hw_chip_reset(struct a
  31. ar9003_hw_internal_regulator_apply(ah);
  32. ath9k_hw_init_pll(ah, chan);
  33. + if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
  34. + ath9k_hw_disable_pll_lock_detect(ah);
  35. +
  36. return true;
  37. }
  38. @@ -1786,8 +1805,14 @@ static int ath9k_hw_do_fastcc(struct ath
  39. if (AR_SREV_9271(ah))
  40. ar9002_hw_load_ani_reg(ah, chan);
  41. + if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
  42. + ath9k_hw_disable_pll_lock_detect(ah);
  43. +
  44. return 0;
  45. fail:
  46. + if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
  47. + ath9k_hw_disable_pll_lock_detect(ah);
  48. +
  49. return -EINVAL;
  50. }
  51. @@ -2041,6 +2066,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
  52. ath9k_hw_set_radar_params(ah);
  53. }
  54. + if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
  55. + ath9k_hw_disable_pll_lock_detect(ah);
  56. +
  57. return 0;
  58. }
  59. EXPORT_SYMBOL(ath9k_hw_reset);
  60. --- a/drivers/net/wireless/ath/ath9k/phy.h
  61. +++ b/drivers/net/wireless/ath/ath9k/phy.h
  62. @@ -48,6 +48,9 @@
  63. #define AR_PHY_PLL_CONTROL 0x16180
  64. #define AR_PHY_PLL_MODE 0x16184
  65. +#define AR_PHY_USB_CTRL1 0x16c84
  66. +#define AR_PHY_USB_CTRL2 0x16c88
  67. +
  68. enum ath9k_ant_div_comb_lna_conf {
  69. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
  70. ATH_ANT_DIV_COMB_LNA2,