736-MIPS-ath79-fix-chained-irq-disable.patch 3.1 KB

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  1. --- a/arch/mips/ath79/irq.c
  2. +++ b/arch/mips/ath79/irq.c
  3. @@ -26,6 +26,8 @@
  4. static void (*ath79_ip2_handler)(void);
  5. static void (*ath79_ip3_handler)(void);
  6. +static struct irq_chip ip2_chip;
  7. +static struct irq_chip ip3_chip;
  8. static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
  9. {
  10. @@ -149,8 +151,7 @@ static void ar934x_ip2_irq_init(void)
  11. for (i = ATH79_IP2_IRQ_BASE;
  12. i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  13. - irq_set_chip_and_handler(i, &dummy_irq_chip,
  14. - handle_level_irq);
  15. + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
  16. irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
  17. }
  18. @@ -182,7 +183,7 @@ static void qca953x_irq_init(void)
  19. for (i = ATH79_IP2_IRQ_BASE;
  20. i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  21. - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
  22. + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
  23. irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
  24. }
  25. @@ -256,15 +257,13 @@ static void qca955x_irq_init(void)
  26. for (i = ATH79_IP2_IRQ_BASE;
  27. i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  28. - irq_set_chip_and_handler(i, &dummy_irq_chip,
  29. - handle_level_irq);
  30. + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
  31. irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
  32. for (i = ATH79_IP3_IRQ_BASE;
  33. i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
  34. - irq_set_chip_and_handler(i, &dummy_irq_chip,
  35. - handle_level_irq);
  36. + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
  37. irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
  38. }
  39. @@ -345,13 +344,13 @@ static void qca956x_irq_init(void)
  40. for (i = ATH79_IP2_IRQ_BASE;
  41. i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  42. - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
  43. + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
  44. irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
  45. for (i = ATH79_IP3_IRQ_BASE;
  46. i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
  47. - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
  48. + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
  49. irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
  50. @@ -466,8 +465,35 @@ static void qca953x_ip3_handler(void)
  51. do_IRQ(ATH79_CPU_IRQ(3));
  52. }
  53. +static void ath79_ip2_disable(struct irq_data *data)
  54. +{
  55. + disable_irq(ATH79_CPU_IRQ(2));
  56. +}
  57. +
  58. +static void ath79_ip2_enable(struct irq_data *data)
  59. +{
  60. + enable_irq(ATH79_CPU_IRQ(2));
  61. +}
  62. +
  63. +static void ath79_ip3_disable(struct irq_data *data)
  64. +{
  65. + disable_irq(ATH79_CPU_IRQ(3));
  66. +}
  67. +
  68. +static void ath79_ip3_enable(struct irq_data *data)
  69. +{
  70. + enable_irq(ATH79_CPU_IRQ(3));
  71. +}
  72. +
  73. void __init arch_init_irq(void)
  74. {
  75. + ip2_chip = dummy_irq_chip;
  76. + ip3_chip = dummy_irq_chip;
  77. + ip2_chip.irq_disable = ath79_ip2_disable;
  78. + ip2_chip.irq_enable = ath79_ip2_enable;
  79. + ip3_chip.irq_disable = ath79_ip3_disable;
  80. + ip3_chip.irq_enable = ath79_ip3_enable;
  81. +
  82. if (soc_is_ar71xx()) {
  83. ath79_ip2_handler = ar71xx_ip2_handler;
  84. ath79_ip3_handler = ar71xx_ip3_handler;