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101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch 1.0 KB

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  1. From: Felix Fietkau <nbd@nbd.name>
  2. Date: Sat, 14 May 2016 20:20:04 +0200
  3. Subject: [PATCH] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer
  4. SoCs
  5. AR913x, AR724x and AR933x are the only SoCs where the
  6. ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c
  7. Invert the logic to make the code compatible with AR95xx
  8. Signed-off-by: Felix Fietkau <nbd@nbd.name>
  9. ---
  10. --- a/arch/mips/ath79/common.c
  11. +++ b/arch/mips/ath79/common.c
  12. @@ -46,12 +46,12 @@ void ath79_ddr_ctrl_init(void)
  13. {
  14. ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
  15. AR71XX_DDR_CTRL_SIZE);
  16. - if (soc_is_ar71xx() || soc_is_ar934x()) {
  17. - ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
  18. - ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
  19. - } else {
  20. + if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) {
  21. ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
  22. ath79_ddr_pci_win_base = 0;
  23. + } else {
  24. + ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
  25. + ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
  26. }
  27. }
  28. EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);