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- From: Felix Fietkau <nbd@nbd.name>
- Date: Wed, 18 May 2016 18:03:31 +0200
- Subject: [PATCH] MIPS: ath79: fix register address in ath79_ddr_wb_flush()
- ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets
- need to be a multiple of 4.
- Cc: Alban Bedel <albeu@free.fr>
- Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface")
- Signed-off-by: Felix Fietkau <nbd@nbd.name>
- ---
- --- a/arch/mips/ath79/common.c
- +++ b/arch/mips/ath79/common.c
- @@ -58,7 +58,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
-
- void ath79_ddr_wb_flush(u32 reg)
- {
- - void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
- + void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg * 4;
-
- /* Flush the DDR write buffer. */
- __raw_writel(0x1, flush_reg);
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