640-MIPS-ath79-add-QCA955x-wmac-reset.patch 2.2 KB

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  1. --- a/arch/mips/ath79/common.c
  2. +++ b/arch/mips/ath79/common.c
  3. @@ -38,7 +38,7 @@ unsigned int ath79_soc_rev;
  4. void __iomem *ath79_pll_base;
  5. void __iomem *ath79_reset_base;
  6. EXPORT_SYMBOL_GPL(ath79_reset_base);
  7. -static void __iomem *ath79_ddr_base;
  8. +void __iomem *ath79_ddr_base;
  9. static void __iomem *ath79_ddr_wb_flush_base;
  10. static void __iomem *ath79_ddr_pci_win_base;
  11. --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  12. +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  13. @@ -32,7 +32,7 @@
  14. #define AR71XX_SPI_SIZE 0x01000000
  15. #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
  16. -#define AR71XX_DDR_CTRL_SIZE 0x100
  17. +#define AR71XX_DDR_CTRL_SIZE 0x200
  18. #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
  19. #define AR71XX_UART_SIZE 0x100
  20. #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
  21. @@ -218,6 +218,9 @@
  22. #define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
  23. #define QCA953X_DDR_REG_FLUSH_WMAC 0xac
  24. +#define QCA955X_DDR_CTL_CONFIG 0x108
  25. +#define QCA955X_DDR_CTL_CONFIG_ACT_WMAC BIT(23)
  26. +
  27. /*
  28. * PLL block
  29. */
  30. --- a/arch/mips/ath79/dev-wmac.c
  31. +++ b/arch/mips/ath79/dev-wmac.c
  32. @@ -171,6 +171,27 @@ static void qca953x_wmac_setup(void)
  33. ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
  34. }
  35. +static int ar955x_wmac_reset(void)
  36. +{
  37. + int i;
  38. +
  39. + /* Try to wait for WMAC DDR activity to stop */
  40. + for (i = 0; i < 10; i++) {
  41. + if (!(__raw_readl(ath79_ddr_base + QCA955X_DDR_CTL_CONFIG) &
  42. + QCA955X_DDR_CTL_CONFIG_ACT_WMAC))
  43. + break;
  44. +
  45. + udelay(10);
  46. + }
  47. +
  48. + ath79_device_reset_set(QCA955X_RESET_RTC);
  49. + udelay(10);
  50. + ath79_device_reset_clear(QCA955X_RESET_RTC);
  51. + udelay(10);
  52. +
  53. + return 0;
  54. +}
  55. +
  56. static void qca955x_wmac_setup(void)
  57. {
  58. u32 t;
  59. @@ -187,6 +208,8 @@ static void qca955x_wmac_setup(void)
  60. ath79_wmac_data.is_clk_25mhz = false;
  61. else
  62. ath79_wmac_data.is_clk_25mhz = true;
  63. +
  64. + ath79_wmac_data.external_reset = ar955x_wmac_reset;
  65. }
  66. static void qca956x_wmac_setup(void)
  67. --- a/arch/mips/ath79/common.h
  68. +++ b/arch/mips/ath79/common.h
  69. @@ -19,6 +19,8 @@
  70. #define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024)
  71. #define ATH79_MEM_SIZE_MAX (256 * 1024 * 1024)
  72. +extern void __iomem *ath79_ddr_base;
  73. +
  74. void ath79_clocks_init(void);
  75. unsigned long ath79_get_sys_clk_rate(const char *id);