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refresh ramips patches from upstream for new kernel

RISCi_ATOM 6 years ago
parent
commit
032417eb7f

+ 4 - 4
target/linux/ramips/patches-4.4/0010-MIPS-ralink-Add-a-few-missing-clocks.patch

@@ -15,7 +15,7 @@ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 
 --- a/arch/mips/ralink/mt7620.c
 +++ b/arch/mips/ralink/mt7620.c
-@@ -436,7 +436,10 @@ void __init ralink_clk_init(void)
+@@ -456,7 +456,10 @@ void __init ralink_clk_init(void)
  	ralink_clk_add("10000100.timer", periph_rate);
  	ralink_clk_add("10000120.watchdog", periph_rate);
  	ralink_clk_add("10000b00.spi", sys_rate);
@@ -25,10 +25,10 @@ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 +	ralink_clk_add("10000e00.uart2", periph_rate);
  	ralink_clk_add("10180000.wmac", xtal_rate);
  
- 	if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {
+ 	if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
 --- a/arch/mips/ralink/rt305x.c
 +++ b/arch/mips/ralink/rt305x.c
-@@ -201,6 +201,7 @@ void __init ralink_clk_init(void)
+@@ -190,6 +190,7 @@ void __init ralink_clk_init(void)
  	ralink_clk_add("cpu", cpu_rate);
  	ralink_clk_add("sys", sys_rate);
  	ralink_clk_add("10000b00.spi", sys_rate);
@@ -38,7 +38,7 @@ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  	ralink_clk_add("10000500.uart", uart_rate);
 --- a/arch/mips/ralink/rt3883.c
 +++ b/arch/mips/ralink/rt3883.c
-@@ -109,6 +109,7 @@ void __init ralink_clk_init(void)
+@@ -99,6 +99,7 @@ void __init ralink_clk_init(void)
  	ralink_clk_add("10000120.watchdog", sys_rate);
  	ralink_clk_add("10000500.uart", 40000000);
  	ralink_clk_add("10000b00.spi", sys_rate);

+ 1 - 1
target/linux/ramips/patches-4.4/0022-MIPS-ralink-Fix-vendor-string-for-mt7620.patch

@@ -16,7 +16,7 @@ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 
 --- a/arch/mips/ralink/mt7620.c
 +++ b/arch/mips/ralink/mt7620.c
-@@ -555,7 +555,7 @@ void prom_soc_init(struct ralink_soc_inf
+@@ -575,7 +575,7 @@ void prom_soc_init(struct ralink_soc_inf
  	}
  
  	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,

+ 1 - 1
target/linux/ramips/patches-4.4/0031-uvc-add-iPassion-iP2970-support.patch

@@ -13,7 +13,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 
 --- a/drivers/media/usb/uvc/uvc_driver.c
 +++ b/drivers/media/usb/uvc/uvc_driver.c
-@@ -2559,6 +2559,18 @@ static struct usb_device_id uvc_ids[] =
+@@ -2665,6 +2665,18 @@ static struct usb_device_id uvc_ids[] =
  	  .bInterfaceSubClass	= 1,
  	  .bInterfaceProtocol	= 0,
  	  .driver_info		= UVC_QUIRK_FORCE_Y8 },

+ 2 - 2
target/linux/ramips/patches-4.4/0033-xhci-mediatek-support-MTK-xHCI-host-controller.patch

@@ -1420,7 +1420,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  
  /*
   * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
-@@ -3110,17 +3111,22 @@ static u32 xhci_td_remainder(struct xhci
+@@ -3113,17 +3114,22 @@ static u32 xhci_td_remainder(struct xhci
  {
  	u32 maxp, total_packet_count;
  
@@ -1447,7 +1447,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  	/* Queueing functions don't count the current TRB into transferred */
  	return (total_packet_count - ((transferred + trb_buff_len) / maxp));
  }
-@@ -3508,7 +3514,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
+@@ -3511,7 +3517,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
  		field |= 0x1;
  
  	/* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */

+ 3 - 3
target/linux/ramips/patches-4.4/0034-NET-multi-phy-support.patch

@@ -11,7 +11,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 
 --- a/drivers/net/phy/phy.c
 +++ b/drivers/net/phy/phy.c
-@@ -890,7 +890,8 @@ void phy_state_machine(struct work_struc
+@@ -893,7 +893,8 @@ void phy_state_machine(struct work_struc
  		/* If the link is down, give up on negotiation for now */
  		if (!phydev->link) {
  			phydev->state = PHY_NOLINK;
@@ -21,7 +21,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  			phydev->adjust_link(phydev->attached_dev);
  			break;
  		}
-@@ -973,7 +974,8 @@ void phy_state_machine(struct work_struc
+@@ -985,7 +986,8 @@ void phy_state_machine(struct work_struc
  			netif_carrier_on(phydev->attached_dev);
  		} else {
  			phydev->state = PHY_NOLINK;
@@ -31,7 +31,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		}
  
  		phydev->adjust_link(phydev->attached_dev);
-@@ -985,7 +987,8 @@ void phy_state_machine(struct work_struc
+@@ -997,7 +999,8 @@ void phy_state_machine(struct work_struc
  	case PHY_HALTED:
  		if (phydev->link) {
  			phydev->link = 0;

+ 2 - 2
target/linux/ramips/patches-4.4/0054-mtd-add-chunked-read-io-to-m25p80.patch

@@ -67,7 +67,7 @@
  static int macronix_quad_enable(struct spi_nor *nor)
  {
  	int ret, val;
-@@ -1194,10 +1254,12 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1201,10 +1261,12 @@ int spi_nor_scan(struct spi_nor *nor, co
  	}
  
  	/* sst nor chips use AAI word program */
@@ -82,7 +82,7 @@
  
  	if (info->flags & USE_FSR)
  		nor->flags |= SNOR_F_USE_FSR;
-@@ -1225,11 +1287,20 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1232,11 +1294,20 @@ int spi_nor_scan(struct spi_nor *nor, co
  	mtd->writebufsize = nor->page_size;
  
  	if (np) {

+ 0 - 166
target/linux/ramips/patches-4.4/0065-MIPS-ralink-MT7688-pinmux-fixes.patch

@@ -1,166 +0,0 @@
-From e906a5f67e5a3337d696ec848e9c28fc68b39aa3 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 4 Jan 2016 20:23:56 +0100
-Subject: [PATCH] MIPS: ralink: MT7688 pinmux fixes
-
-A few fixes to the pinmux data, 2 new muxes and a minor whitespace
-cleanup.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Patchwork: https://patchwork.linux-mips.org/patch/11991/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ralink/mt7620.c | 80 +++++++++++++++++++++++++++++------------------
- 1 file changed, 50 insertions(+), 30 deletions(-)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -107,31 +107,31 @@ static struct rt2880_pmx_group mt7620a_p
- };
- 
- static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
--	FUNC("sdcx", 3, 19, 1),
-+	FUNC("sdxc d6", 3, 19, 1),
- 	FUNC("utif", 2, 19, 1),
- 	FUNC("gpio", 1, 19, 1),
--	FUNC("pwm", 0, 19, 1),
-+	FUNC("pwm1", 0, 19, 1),
- };
- 
- static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
--	FUNC("sdcx", 3, 18, 1),
-+	FUNC("sdxc d7", 3, 18, 1),
- 	FUNC("utif", 2, 18, 1),
- 	FUNC("gpio", 1, 18, 1),
--	FUNC("pwm", 0, 18, 1),
-+	FUNC("pwm0", 0, 18, 1),
- };
- 
- static struct rt2880_pmx_func uart2_grp_mt7628[] = {
--	FUNC("sdcx", 3, 20, 2),
-+	FUNC("sdxc d5 d4", 3, 20, 2),
- 	FUNC("pwm", 2, 20, 2),
- 	FUNC("gpio", 1, 20, 2),
--	FUNC("uart", 0, 20, 2),
-+	FUNC("uart2", 0, 20, 2),
- };
- 
- static struct rt2880_pmx_func uart1_grp_mt7628[] = {
--	FUNC("sdcx", 3, 45, 2),
-+	FUNC("sw_r", 3, 45, 2),
- 	FUNC("pwm", 2, 45, 2),
- 	FUNC("gpio", 1, 45, 2),
--	FUNC("uart", 0, 45, 2),
-+	FUNC("uart1", 0, 45, 2),
- };
- 
- static struct rt2880_pmx_func i2c_grp_mt7628[] = {
-@@ -143,21 +143,21 @@ static struct rt2880_pmx_func i2c_grp_mt
- 
- static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) };
- static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) };
--static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 15, 38) };
-+static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) };
- static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
- 
- static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
- 	FUNC("jtag", 3, 22, 8),
- 	FUNC("utif", 2, 22, 8),
- 	FUNC("gpio", 1, 22, 8),
--	FUNC("sdcx", 0, 22, 8),
-+	FUNC("sdxc", 0, 22, 8),
- };
- 
- static struct rt2880_pmx_func uart0_grp_mt7628[] = {
- 	FUNC("-", 3, 12, 2),
- 	FUNC("-", 2, 12, 2),
- 	FUNC("gpio", 1, 12, 2),
--	FUNC("uart", 0, 12, 2),
-+	FUNC("uart0", 0, 12, 2),
- };
- 
- static struct rt2880_pmx_func i2s_grp_mt7628[] = {
-@@ -171,7 +171,7 @@ static struct rt2880_pmx_func spi_cs1_gr
- 	FUNC("-", 3, 6, 1),
- 	FUNC("refclk", 2, 6, 1),
- 	FUNC("gpio", 1, 6, 1),
--	FUNC("spi", 0, 6, 1),
-+	FUNC("spi cs1", 0, 6, 1),
- };
- 
- static struct rt2880_pmx_func spis_grp_mt7628[] = {
-@@ -188,28 +188,44 @@ static struct rt2880_pmx_func gpio_grp_m
- 	FUNC("gpio", 0, 11, 1),
- };
- 
--#define MT7628_GPIO_MODE_MASK	0x3
--
--#define MT7628_GPIO_MODE_PWM1	30
--#define MT7628_GPIO_MODE_PWM0	28
--#define MT7628_GPIO_MODE_UART2	26
--#define MT7628_GPIO_MODE_UART1	24
--#define MT7628_GPIO_MODE_I2C	20
--#define MT7628_GPIO_MODE_REFCLK	18
--#define MT7628_GPIO_MODE_PERST	16
--#define MT7628_GPIO_MODE_WDT	14
--#define MT7628_GPIO_MODE_SPI	12
--#define MT7628_GPIO_MODE_SDMODE	10
--#define MT7628_GPIO_MODE_UART0	8
--#define MT7628_GPIO_MODE_I2S	6
--#define MT7628_GPIO_MODE_CS1	4
--#define MT7628_GPIO_MODE_SPIS	2
--#define MT7628_GPIO_MODE_GPIO	0
-+static struct rt2880_pmx_func wled_kn_grp_mt7628[] = {
-+	FUNC("rsvd", 3, 35, 1),
-+	FUNC("rsvd", 2, 35, 1),
-+	FUNC("gpio", 1, 35, 1),
-+	FUNC("wled_kn", 0, 35, 1),
-+};
-+
-+static struct rt2880_pmx_func wled_an_grp_mt7628[] = {
-+	FUNC("rsvd", 3, 35, 1),
-+	FUNC("rsvd", 2, 35, 1),
-+	FUNC("gpio", 1, 35, 1),
-+	FUNC("wled_an", 0, 35, 1),
-+};
-+
-+#define MT7628_GPIO_MODE_MASK		0x3
-+
-+#define MT7628_GPIO_MODE_WLED_KN	48
-+#define MT7628_GPIO_MODE_WLED_AN	32
-+#define MT7628_GPIO_MODE_PWM1		30
-+#define MT7628_GPIO_MODE_PWM0		28
-+#define MT7628_GPIO_MODE_UART2		26
-+#define MT7628_GPIO_MODE_UART1		24
-+#define MT7628_GPIO_MODE_I2C		20
-+#define MT7628_GPIO_MODE_REFCLK		18
-+#define MT7628_GPIO_MODE_PERST		16
-+#define MT7628_GPIO_MODE_WDT		14
-+#define MT7628_GPIO_MODE_SPI		12
-+#define MT7628_GPIO_MODE_SDMODE		10
-+#define MT7628_GPIO_MODE_UART0		8
-+#define MT7628_GPIO_MODE_I2S		6
-+#define MT7628_GPIO_MODE_CS1		4
-+#define MT7628_GPIO_MODE_SPIS		2
-+#define MT7628_GPIO_MODE_GPIO		0
- 
- static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
- 	GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
- 				1, MT7628_GPIO_MODE_PWM1),
--	GRP_G("pmw1", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
-+	GRP_G("pmw0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
- 				1, MT7628_GPIO_MODE_PWM0),
- 	GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK,
- 				1, MT7628_GPIO_MODE_UART2),
-@@ -233,6 +249,10 @@ static struct rt2880_pmx_group mt7628an_
- 				1, MT7628_GPIO_MODE_SPIS),
- 	GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK,
- 				1, MT7628_GPIO_MODE_GPIO),
-+	GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
-+				1, MT7628_GPIO_MODE_WLED_AN),
-+	GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
-+				1, MT7628_GPIO_MODE_WLED_KN),
- 	{ 0 }
- };
- 

+ 0 - 30
target/linux/ramips/patches-4.4/0068-fix-ralink-prom.c

@@ -1,30 +0,0 @@
---- a/arch/mips/ralink/prom.c
-+++ b/arch/mips/ralink/prom.c
-@@ -30,8 +30,10 @@ const char *get_system_type(void)
- 	return soc_info.sys_type;
- }
- 
--static __init void prom_init_cmdline(int argc, char **argv)
-+static __init void prom_init_cmdline(void)
- {
-+	int argc;
-+	char **argv;
- 	int i;
- 
- 	pr_debug("prom: fw_arg0=%08x fw_arg1=%08x fw_arg2=%08x fw_arg3=%08x\n",
-@@ -60,14 +62,11 @@ static __init void prom_init_cmdline(int
- 
- void __init prom_init(void)
- {
--	int argc;
--	char **argv;
--
- 	prom_soc_init(&soc_info);
- 
- 	pr_info("SoC Type: %s\n", get_system_type());
- 
--	prom_init_cmdline(argc, argv);
-+	prom_init_cmdline();
- }
- 
- void __init prom_free_prom_memory(void)

+ 0 - 28
target/linux/ramips/patches-4.4/0080-MIPS-ralink-fix-USB-frequency-scaling.patch

@@ -1,28 +0,0 @@
-From ae28413b3b8901ea00af3571e1c90d0228976e16 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 4 Jan 2016 20:23:57 +0100
-Subject: [PATCH 80/81] MIPS: ralink: fix USB frequency scaling
-
-Commit 418d29c87061 ("MIPS: ralink: Unify SoC id handling") was not fully
-correct. The logic for the SoC check got inverted. We need to check if it
-is not a MT76x8.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Patchwork: https://patchwork.linux-mips.org/patch/11992/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ralink/mt7620.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -462,7 +462,7 @@ void __init ralink_clk_init(void)
- 	ralink_clk_add("10000e00.uart2", periph_rate);
- 	ralink_clk_add("10180000.wmac", xtal_rate);
- 
--	if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {
-+	if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
- 		/*
- 		 * When the CPU goes into sleep mode, the BUS clock will be
- 		 * too low for USB to function properly. Adjust the busses

+ 0 - 25
target/linux/ramips/patches-4.4/0081-MIPS-ralink-Fix-invalid-assignment-of-SoC-type.patch

@@ -1,25 +0,0 @@
-From 0af3a40f09a2a85089037a0b5b51471fa48b229e Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 4 Jan 2016 20:23:58 +0100
-Subject: [PATCH] MIPS: ralink: Fix invalid assignment of SoC type
-
-Commit 418d29c87061 ("MIPS: ralink: Unify SoC id handling") introduced
-broken code. We obviously need to assign the value.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Patchwork: https://patchwork.linux-mips.org/patch/11993/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ralink/rt288x.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/ralink/rt288x.c
-+++ b/arch/mips/ralink/rt288x.c
-@@ -119,5 +119,5 @@ void prom_soc_init(struct ralink_soc_inf
- 	soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
- 
- 	rt2880_pinmux_data = rt2880_pinmux_data_act;
--	ralink_soc == RT2880_SOC;
-+	ralink_soc = RT2880_SOC;
- }

+ 0 - 32
target/linux/ramips/patches-4.4/0082-MIPS-ralink-fix-MT7628-pinmux-typos.patch

@@ -1,32 +0,0 @@
-From d7146829c9da24e285cb1b1f2156b5b3e2d40c07 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
-Date: Thu, 19 May 2016 22:07:34 +0200
-Subject: [PATCH] MIPS: ralink: fix MT7628 pinmux typos
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
-Cc: john@phrozen.org
-Cc: linux-mips@linux-mips.org
-Cc: linux-kernel@vger.kernel.org
-Patchwork: https://patchwork.linux-mips.org/patch/13306/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ralink/mt7620.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -223,9 +223,9 @@ static struct rt2880_pmx_func wled_an_gr
- #define MT7628_GPIO_MODE_GPIO		0
- 
- static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
--	GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
-+	GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
- 				1, MT7628_GPIO_MODE_PWM1),
--	GRP_G("pmw0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
-+	GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
- 				1, MT7628_GPIO_MODE_PWM0),
- 	GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK,
- 				1, MT7628_GPIO_MODE_UART2),

+ 0 - 35
target/linux/ramips/patches-4.4/0083-MIPS-ralink-fix-MT7628-wled_an-pinmux-gpio.patch

@@ -1,35 +0,0 @@
-From 07b50db6e685172a41b9978aebffb2438166d9b6 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
-Date: Thu, 19 May 2016 22:07:35 +0200
-Subject: [PATCH] MIPS: ralink: fix MT7628 wled_an pinmux gpio
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
-Cc: john@phrozen.org
-Cc: linux-mips@linux-mips.org
-Cc: linux-kernel@vger.kernel.org
-Patchwork: https://patchwork.linux-mips.org/patch/13307/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ralink/mt7620.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -196,10 +196,10 @@ static struct rt2880_pmx_func wled_kn_gr
- };
- 
- static struct rt2880_pmx_func wled_an_grp_mt7628[] = {
--	FUNC("rsvd", 3, 35, 1),
--	FUNC("rsvd", 2, 35, 1),
--	FUNC("gpio", 1, 35, 1),
--	FUNC("wled_an", 0, 35, 1),
-+	FUNC("rsvd", 3, 44, 1),
-+	FUNC("rsvd", 2, 44, 1),
-+	FUNC("gpio", 1, 44, 1),
-+	FUNC("wled_an", 0, 44, 1),
- };
- 
- #define MT7628_GPIO_MODE_MASK		0x3

+ 43 - 0
target/linux/ramips/patches-4.4/0100-MIPS-ralink-allow-NULL-clock-for-clk_get_rate.patch

@@ -0,0 +1,43 @@
+From patchwork Tue Jul 18 10:17:29 2017
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+Subject: [8/9] MIPS: ralink: allow NULL clock for clk_get_rate
+X-Patchwork-Submitter: Jonas Gorski <jonas.gorski@gmail.com>
+X-Patchwork-Id: 16778
+Message-Id: <20170718101730.2541-9-jonas.gorski@gmail.com>
+To: unlisted-recipients:; (no To-header on input)
+Cc: John Crispin <john@phrozen.org>,
+ Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org,
+ linux-kernel@vger.kernel.org
+Date: Tue, 18 Jul 2017 12:17:29 +0200
+From: Jonas Gorski <jonas.gorski@gmail.com>
+List-Id: linux-mips <linux-mips.eddie.linux-mips.org>
+
+Make the behaviour of clk_get_rate consistent with common clk's
+clk_get_rate by accepting NULL clocks as parameter. Some device
+drivers rely on this, and will cause an OOPS otherwise.
+
+Fixes: 3f0a06b0368d ("MIPS: ralink: adds clkdev code")
+Cc: John Crispin <john@phrozen.org>
+Cc: Ralf Baechle <ralf@linux-mips.org>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Reported-by: Mathias Kresin <dev@kresin.me>
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/ralink/clk.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/mips/ralink/clk.c
++++ b/arch/mips/ralink/clk.c
+@@ -52,6 +52,9 @@ EXPORT_SYMBOL_GPL(clk_disable);
+ 
+ unsigned long clk_get_rate(struct clk *clk)
+ {
++	if (!clk)
++		return 0;
++
+ 	return clk->rate;
+ }
+ EXPORT_SYMBOL_GPL(clk_get_rate);

+ 3 - 3
target/linux/ramips/patches-4.4/0720-arch-mips-ralink-add-i2c-clocks.patch

@@ -35,7 +35,7 @@
  	ralink_clk_add("10000c00.uartlite", periph_rate);
 --- a/arch/mips/ralink/rt288x.c
 +++ b/arch/mips/ralink/rt288x.c
-@@ -75,6 +75,7 @@ void __init ralink_clk_init(void)
+@@ -65,6 +65,7 @@ void __init ralink_clk_init(void)
  	ralink_clk_add("300100.timer", cpu_rate / 2);
  	ralink_clk_add("300120.watchdog", cpu_rate / 2);
  	ralink_clk_add("300500.uart", cpu_rate / 2);
@@ -45,7 +45,7 @@
  	ralink_clk_add("480000.wmac", wmac_rate);
 --- a/arch/mips/ralink/rt305x.c
 +++ b/arch/mips/ralink/rt305x.c
-@@ -200,6 +200,8 @@ void __init ralink_clk_init(void)
+@@ -189,6 +189,8 @@ void __init ralink_clk_init(void)
  
  	ralink_clk_add("cpu", cpu_rate);
  	ralink_clk_add("sys", sys_rate);
@@ -56,7 +56,7 @@
  	ralink_clk_add("10000100.timer", wdt_rate);
 --- a/arch/mips/ralink/rt3883.c
 +++ b/arch/mips/ralink/rt3883.c
-@@ -108,6 +108,8 @@ void __init ralink_clk_init(void)
+@@ -98,6 +98,8 @@ void __init ralink_clk_init(void)
  	ralink_clk_add("10000100.timer", sys_rate);
  	ralink_clk_add("10000120.watchdog", sys_rate);
  	ralink_clk_add("10000500.uart", 40000000);

+ 98 - 0
target/linux/ramips/patches-4.4/101-mt7621-timer.patch

@@ -0,0 +1,98 @@
+--- a/arch/mips/ralink/mt7621.c
++++ b/arch/mips/ralink/mt7621.c
+@@ -21,6 +21,7 @@
+ #include <asm/mach-ralink/ralink_regs.h>
+ #include <asm/mach-ralink/mt7621.h>
+ #include <asm/mips-boards/launch.h>
++#include <asm/delay.h>
+ 
+ #include <pinmux.h>
+ 
+@@ -178,6 +179,58 @@ bool plat_cpu_core_present(int core)
+ 	return true;
+ }
+ 
++#define LPS_PREC 8
++/*
++*  Re-calibration lpj(loop-per-jiffy).
++*  (derived from kernel/calibrate.c)
++*/
++static int udelay_recal(void)
++{
++	unsigned int i, lpj = 0;
++	unsigned long ticks, loopbit;
++	int lps_precision = LPS_PREC;
++
++	lpj = (1<<12);
++
++	while ((lpj <<= 1) != 0) {
++		/* wait for "start of" clock tick */
++		ticks = jiffies;
++		while (ticks == jiffies)
++			/* nothing */;
++
++		/* Go .. */
++		ticks = jiffies;
++		__delay(lpj);
++		ticks = jiffies - ticks;
++		if (ticks)
++			break;
++	}
++
++	/*
++	 * Do a binary approximation to get lpj set to
++	 * equal one clock (up to lps_precision bits)
++	 */
++	lpj >>= 1;
++	loopbit = lpj;
++	while (lps_precision-- && (loopbit >>= 1)) {
++		lpj |= loopbit;
++		ticks = jiffies;
++		while (ticks == jiffies)
++			/* nothing */;
++		ticks = jiffies;
++		__delay(lpj);
++		if (jiffies != ticks)   /* longer than 1 tick */
++			lpj &= ~loopbit;
++	}
++	printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj);
++
++	for(i=0; i< NR_CPUS; i++)
++		cpu_data[i].udelay_val = lpj;
++
++	return 0;
++}
++device_initcall(udelay_recal);
++
+ void prom_soc_init(struct ralink_soc_info *soc_info)
+ {
+ 	void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -56,6 +56,7 @@ choice
+ 		select COMMON_CLK
+ 		select CLKSRC_MIPS_GIC
+ 		select HW_HAS_PCI
++		select GENERIC_CLOCKEVENTS_BROADCAST
+ endchoice
+ 
+ choice
+--- a/arch/mips/ralink/timer-gic.c
++++ b/arch/mips/ralink/timer-gic.c
+@@ -3,6 +3,7 @@
+ #include <linux/of.h>
+ #include <linux/clk-provider.h>
+ #include <linux/clocksource.h>
++#include <asm/time.h>
+ 
+ #include "common.h"
+ 
+@@ -10,6 +11,8 @@ void __init plat_time_init(void)
+ {
+ 	ralink_of_remap();
+ 
++	mips_hpt_frequency = 880000000 / 2;
++
+ 	of_clk_init(NULL);
+ 	clocksource_probe();
+ }

+ 0 - 21
target/linux/ramips/patches-4.4/200-rt3883-fix-pinctrl-typo.patch

@@ -1,21 +0,0 @@
-From 2583143af8111d430bdca0268b6cdb7ccc7c3f9d Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 13 Jan 2017 05:40:04 +0100
-Subject: [PATCH] mips: ralink/rt3883: fix typo in pinctrl lna_g_func
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- arch/mips/ralink/rt3883.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/ralink/rt3883.c
-+++ b/arch/mips/ralink/rt3883.c
-@@ -36,7 +36,7 @@ static struct rt2880_pmx_func uartlite_f
- static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
- static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
- static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
--static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
-+static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna g", 0, 35, 3) };
- static struct rt2880_pmx_func pci_func[] = {
- 	FUNC("pci-dev", 0, 40, 32),
- 	FUNC("pci-host2", 1, 40, 32),