0902-mediatek-4-byte-spi-reset.patch 1.2 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243
  1. diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
  2. index fe9ceb7..2151975 100644
  3. --- a/drivers/mtd/devices/m25p80.c
  4. +++ b/drivers/mtd/devices/m25p80.c
  5. @@ -27,6 +27,9 @@
  6. #include <linux/spi/flash.h>
  7. #include <linux/mtd/spi-nor.h>
  8. +#define OPCODE_RESET_ENABLE 0x66
  9. +#define OPCODE_RESET 0x99
  10. +
  11. #define MAX_CMD_SIZE 6
  12. struct m25p {
  13. struct spi_device *spi;
  14. @@ -168,6 +171,17 @@ static int m25p80_erase(struct spi_nor *nor, loff_t offset)
  15. return 0;
  16. }
  17. +void m25p80_reboot(struct mtd_info *mtd)
  18. +{
  19. + struct spi_nor *nor = container_of(mtd, struct spi_nor, mtd);
  20. + struct m25p *flash = nor->priv;
  21. +
  22. + flash->command[0] = OPCODE_RESET_ENABLE;
  23. + spi_write(flash->spi, flash->command, 1);
  24. + flash->command[0] = OPCODE_RESET;
  25. + spi_write(flash->spi, flash->command, 1);
  26. +}
  27. +
  28. /*
  29. * board specific setup should have ensured the SPI clock used here
  30. * matches what the READ command supports, at least until this driver
  31. @@ -197,6 +211,7 @@ static int m25p_probe(struct spi_device *spi)
  32. nor->erase = m25p80_erase;
  33. nor->write_reg = m25p80_write_reg;
  34. nor->read_reg = m25p80_read_reg;
  35. + nor->mtd._reboot = m25p80_reboot;
  36. nor->dev = &spi->dev;
  37. nor->flash_node = spi->dev.of_node;
  38. --
  39. 2.9.3